JP4458223B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Compound semiconductor device and manufacturing method thereof Download PDF

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JP4458223B2
JP4458223B2 JP2003022685A JP2003022685A JP4458223B2 JP 4458223 B2 JP4458223 B2 JP 4458223B2 JP 2003022685 A JP2003022685 A JP 2003022685A JP 2003022685 A JP2003022685 A JP 2003022685A JP 4458223 B2 JP4458223 B2 JP 4458223B2
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buffer layer
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JP2004235473A (en
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由佳里 鈴木
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信越半導体株式会社
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[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-110138 [Patent Document 2]
Japanese Patent Laid-Open No. 5-206513
As is well known, multilayer structures of compound semiconductors are applied to ultra-high-speed transistors such as MESFET (Metal-Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Transistor), and light-emitting elements such as light-emitting diodes and lasers. Has led to the acquisition. A semiconductor multi-layer structure that has attracted attention in recent years includes a heterojunction structure using a GaN-based compound semiconductor. GaN-based compound semiconductors have a band gap that can be changed from 2.0 eV to 6.2 eV at room temperature and are chemically stable, and thus are being applied to light-emitting elements such as blue and are becoming popular. In addition to the wide band gap, GaN-based compound semiconductors have high electron mobility and are easy to form heterojunctions, so they can operate in high-temperature environments, resulting in higher speed and higher output. Its application to next-generation ultra-high-speed transistors is also attracting attention and has been studied.
[0004]
GaN-based compound semiconductors, unlike GaAs-based compounds, are difficult to manufacture a semi-insulating single crystal substrate capable of homoepitaxial growth, so when forming an element layer having a heterojunction structure, SiC Single crystal substrates and sapphire (single crystal alumina) substrates are used. At this time, the quality of the element layer is improved by growing GaN (Patent Document 1) or AlN on the single crystal substrate as a buffer layer and then heteroepitaxially growing the element layer.
[0005]
[Problems to be solved by the invention]
In heteroepitaxial growth of a GaN-based compound semiconductor, the lattice constant difference between SiC or sapphire used as a single crystal substrate and GaN is very large (about 5% for SiC and about 15% for sapphire). Therefore, a high-quality element layer cannot be stably manufactured unless the buffer layer used for growth can absorb or relax this lattice constant difference. In addition, since the difference in coefficient of linear expansion between the single crystal substrate and the compound semiconductor layer is large (especially when an insulating sapphire substrate is used), the generation and growth of crystal defects are further promoted by the thermal stress derived therefrom. Because it tends to be easy to be done, attention is necessary.
[0006]
Conventionally, GaN, which has been used as a material for the buffer layer, has a large lattice constant difference from the substrate, and thus tends to cause crystal defects near the boundary between the buffer layer and the substrate. On the other hand, although the lattice constant difference between AlN and the substrate is smaller than that of GaN, on the other hand, the lattice mismatch rate with the element layer made of a GaN-based compound semiconductor increases, so the boundary between the buffer layer and the element layer or the element Crystal defects are likely to occur in the layer. As disclosed in Patent Document 2, a method using a buffer layer in which GaN layers and AlN layers are alternately stacked, or a buffer layer made of a mixed crystal of GaN and AlN is also conceivable. As long as the combination with AlN is used, it is difficult to avoid the occurrence of crystal defects due to lattice mismatch between the buffer layer and the element layer.
[0007]
An object of the present invention is to provide a semiconductor element structure and a method for manufacturing the same, in which crystal defects are unlikely to occur at the boundary between a buffer layer and an element layer, and thus a high-quality element layer can be stably realized.
[0008]
[Means for solving the problems and actions / effects]
In order to solve the above-described problems, the compound semiconductor device of the present invention is based on In x Ga y Al 1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1). The semiconductor element layer to be formed is connected to a SiC layer through a buffer layer in which at least a part of the layer thickness direction is an AlInN layer made of Al 1-a In a N (a is an InN mixed crystal ratio, 0 <a <1). And epitaxially grown on a single crystal substrate made of either sapphire or sapphire,
In the AlInN layer in the buffer layer, the InN mixed crystal ratio a increases stepwise or continuously from the boundary on the single crystal substrate side toward the boundary on the semiconductor element layer side,
The buffer layer is arranged such that an auxiliary layer in which GaN layers and InGaAlN layers are alternately stacked is disposed between the AlInN layer and the semiconductor element layer so as to be in contact with the AlInN layer and the semiconductor element layer. Features. By growing the semiconductor element layer using such a buffer layer, a high-quality element layer having a low crystal defect density can be stably realized.
In the AlInN layer in the buffer layer, the InN mixed crystal ratio a increases stepwise (preferably three or more steps) or continuously from the boundary on the single crystal substrate side to the boundary on the semiconductor element layer side. By forming the buffer layer, the lattice constant gradually increases from the single crystal substrate side to the semiconductor element layer side in the layer thickness direction, and the lattice constant does not increase discontinuously. As a result, stress based on the change in lattice constant is less likely to concentrate at a specific position in the layer thickness direction of the buffer layer, and crystal defects can be prevented more effectively.
Further, the buffer layer is arranged such that an auxiliary layer in which GaN layers and InGaAlN layers are alternately stacked is in contact with the AlInN layer and the semiconductor element layer between the AlInN layer and the semiconductor element layer. By forming the semiconductor element layer, it is possible to more effectively prevent a problem that a crystal defect due to lattice mismatch with the substrate occurs in the semiconductor element layer.
[0009]
The AlInN layer in the buffer layer can be formed so that the InN mixed crystal ratio a is larger at the boundary side with the semiconductor element layer than at the boundary side with the single crystal substrate, and the semiconductor is interposed through the buffer layer. The element layer can be epitaxially grown on a single crystal substrate made of any one of SiC, sapphire, and silicon.
[0010]
According to the above configuration, when heteroepitaxially growing a semiconductor element layer made of In x Ga y Al 1-xy N on a single crystal substrate made of SiC, sapphire, or silicon, the boundary with the semiconductor element layer On the side, an Al 1-a In a N layer formed so that the InN mixed crystal ratio a is larger than the boundary side with the single crystal substrate is used as a buffer layer. InN has a larger lattice constant than GaN, and by adjusting the InN mixed crystal ratio a, a buffer is provided on the boundary side with the semiconductor element layer as compared with a conventional buffer layer combining GaN, AlN, or a combination thereof. The lattice constant of the layer can be made closer to the lattice constant of the semiconductor element layer. As a result, crystal defects are less likely to occur at the boundary between the buffer layer and the element layer, and as a result, a high-quality element layer can be stably realized. In particular, when an SiC single crystal substrate is used, the lattice constant difference from the single crystal substrate can be effectively reduced by reducing the substrate-side InN mixed crystal ratio a of the buffer layer.
[0011]
The semiconductor element layer made of In x Ga y Al 1-xy N has a lattice constant, a band gap energy, and an energy ratio adjusted by adjusting the InN mixed crystal ratio x, the GaN mixed crystal ratio y, and the AlN mixed crystal ratio 1-xy. Can be adjusted to a desired value. For example, in a HEMT structure using a GaN-based compound, many attempts have been made to heterojunction a GaN channel layer to an n-type doped GaAlN electron supply layer in order to form a two-dimensional electron gas layer. In addition, the electron supply layer may be formed as an InGaAlN layer in order to further enhance lattice matching with the GaN channel layer.
[0012]
When the semiconductor element layer has the InN mixed crystal ratio x, the GaN mixed crystal ratio y, and the AlN mixed crystal ratio 1-xy adjusted so that the lattice constant difference with GaN is within ± 1%. (For example, y = 1 and x = 0 in the case of a GaN channel layer) In the AlInN layer in the buffer layer, the portion including the boundary with the semiconductor element layer has an InN mixed crystal ratio a of 0.1 or more and 0. By using Al 1-a In a N adjusted to .25 or less, the semiconductor element layer and the lattice constant can be substantially matched at the boundary. Thereby, the generation of crystal defects in the vicinity of the boundary between the buffer layer and the semiconductor element layer can be more effectively prevented.
[0013]
The AlInN layer in the buffer layer is formed such that the InN mixed crystal ratio a increases stepwise (preferably three or more steps) or continuously from the boundary on the single crystal substrate side toward the boundary on the semiconductor element layer side. It is desirable. By doing so, the lattice constant of the buffer layer increases gradually from the single crystal substrate side to the semiconductor element layer side in the layer thickness direction, and the lattice constant does not increase discontinuously. As a result, stress based on the change in lattice constant is less likely to concentrate at a specific position in the layer thickness direction of the buffer layer, and crystal defects can be prevented more effectively.
[0014]
In the present invention, a buffer layer having an AlInN layer can also be used in order to improve the crystallinity of the semiconductor element layer. In this case, the AlInN layer may be amorphous.
[0015]
In addition, the method for producing the compound semiconductor element of the present invention includes:
On the single crystal substrate made of either SiC or sapphire, at least a partial section in the layer thickness direction is Al 1-a In a N (where a is an InN mixed crystal ratio, 0 <a <1), and the single crystal substrate Epitaxially growing a buffer layer having an AlInN layer in which the InN mixed crystal ratio a is increased stepwise or continuously from the side boundary, and an auxiliary layer in which a GaN layer and an InGaAlN layer are alternately stacked on the AlInN layer And a process of
A step of epitaxially growing a semiconductor element layer made of In x Ga y Al 1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) on the buffer layer;
It is characterized by including. By growing a semiconductor element layer using such a buffer layer, a compound semiconductor element having a high-quality element layer with a low crystal defect density can be easily and stably manufactured.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an example in which the semiconductor element of the present invention is configured as a HEMT. The HEMT 200 is obtained by forming a semiconductor element layer 103 on a single crystal substrate 101 made of SiC through a buffer layer 102 by a heteroepitaxial growth method using a MOVPE method. Note that the single crystal substrate 101 may be a sapphire substrate or a silicon substrate instead of the SiC substrate.
[0017]
The semiconductor element layer 103 functions from the side close to the buffer layer 102 as a contact layer with an undoped GaN channel layer 119, an undoped GaAlN spacer layer 105, a GaAlN electron supply layer 110 doped n-type with Si or the like, and an electrode. N-type GaN layers 111 to be laminated in this order. A drain electrode 106 and a source electrode 107 are formed on the n-type GaN layer 111, and a gate electrode 108 is formed on the n-type GaAlN layer 110 exposed in a region where the n-type GaN layer 111 is not formed. The drain electrode 106 and the source electrode 107 are made of a metal (for example, Ti / Al) that forms an ohmic junction with the n-type GaN layer 111, and the gate electrode 108 is Schottky (with the n-type GaAlN electron supply layer 110). Each of them is made of a metal (for example, Pd / Au) forming a Schottky junction. The GaAlN spacer layer 105 is for preventing impurities such as Si as an n-type dopant from diffusing into the already formed GaN channel layer 119 when the n-type GaAlN electron supply layer 110 is grown. .
[0018]
A two-dimensional electron gas (2DEG) layer with high electron mobility is formed between the GaAlN spacer layer 105 and the GaN channel layer 119. Then, a voltage is applied between the drain electrode 106 and the source electrode 107, and the current value is controlled by the gate electrode 108, while energization is performed between the drain electrode 106 and the source electrode 107 via the GaN channel layer 119. Can be done.
[0019]
Next, in the buffer layer 102, at least a portion including the boundary with the semiconductor element layer 103 is Al 1−a In a N (a is an InN mixed crystal ratio, 0 <a <1), and the semiconductor element layer 103 The InN mixed crystal ratio a is larger on the boundary side than that on the boundary side with the SiC single crystal substrate 101. In the present embodiment, as shown in FIG. 2, each of InN mixed crystal ratios a1, a2,..., An (where a1 <a2 <... <An) is made of Al 1-a In a N. Unit layers 2-1, 2-2,..., 2-n are laminated in this order from the substrate 101 side. Thereby, for example, as shown in FIG. 3, the buffer layer 102 has a semiconductor element layer in which the InN mixed crystal ratio a in the layer thickness direction is a value a1 (0 in the present embodiment) on the boundary side with the substrate 101. The distribution increases stepwise toward the value an on the 103 side (0.17 in this embodiment). The number n of unit layers is 3 or more, and the thickness of each unit layer is appropriately determined according to the number of unit layers so that the layer thickness of the buffer layer 102 is 50 nm to 200 nm, for example.
[0020]
Hereinafter, the manufacturing method of said HEMT200 is demonstrated. The buffer layer 102 and the semiconductor element layer 103 can be formed by a vapor phase growth method using a known MOVPE method or MBE (Molecular Beam Epitaxy) method. When the MOVPE method is employed, the following can be used as the source gas. Ga source: trimethylgallium (TMGa), triethylgallium (TEGa), etc. In source: trimethylindium (TMIn), triethylindium (TEIn), etc.
-Al source; trimethylaluminum (TMAl), triethylaluminum (TEAl), etc .;
N source: ammonia (NH 3 ), etc.
Moreover, the following can be used for dopant gas used as a p-type dopant source and an n-type dopant source.
Mg source: biscyclopentadienyl magnesium (Cp 2 Mg), etc.
-Si source: silicon hydride such as silane;
In this embodiment, Si and Mg are used as dopant elements, but group IV elements such as C, Ge, and Sn are used as n-type dopants, and group II elements such as Ca, Sr, and Zn are used as p-type dopants. Elements can be used.
Each of the above source gases is supplied into a reaction vessel in which the substrate 101 is disposed in a form that is appropriately diluted with a carrier gas (for example, nitrogen gas).
[0021]
Specifically, the buffer layer 102 shown in FIG. 2 is grown on the main surface of the SiC single crystal substrate (having the crystal main axis [0001]) by using the MOVPE method. Each of the unit layers 2-1, 2-2,..., 2-n of the buffer layer 102 has a flow rate ratio of the organometallic gas serving as the In source and Al source for each layer according to the difference in the InN mixed crystal ratio a. Control is performed in a stepwise manner by a mass flow controller or the like. Note that at least the first one or more layers of the buffer layer 102 may be a polycrystalline layer or an amorphous layer. In addition, it is desirable that the last layer or the plurality of unit layers of the buffer layer 102 be a single crystal suitable for epitaxial growth of the semiconductor element layer 103 (the crystallinity of the unit layer is improved sequentially with repeated formation). To do).
[0022]
From the viewpoint of improving crystallinity, InN is desirably grown at a relatively low temperature (eg, 400 ° C. or more and 900 ° C. or less), and AlN is desirably grown at a relatively high temperature (eg, 900 ° C. or more and 1100 ° C. or less). It is said that. Therefore, it is desirable that the buffer layer 2 made of the mixed crystal of both is grown at a temperature range between 500 ° C. and 1000 ° C., which is an intermediate temperature range.
[0023]
Next, when the formation of the buffer layer 102 is finished, the GaN channel layer 119, the GaAlN spacer layer are continuously adjusted in the reaction vessel by adjusting the flow rate ratio of the organic metal gas serving as the source gas and the dopant gas for each layer. 105, GaAlN electron supply layer 110 and n-type GaN layer 111 are epitaxially grown sequentially. Thereafter, a part of the n-type GaN layer 111 is partially removed by photolithography or the like, the gate electrode 108 is formed on the exposed GaAlN electron supply layer 110, and the drain electrode 106 and the source electrode are formed on the remaining n-type GaN layer 111. 107 is formed. After that, dicing together with the substrate 101 to form a chip, and resin molding together with a lead frame conducting to each electrode, a final HEMT 200 is obtained.
[0024]
In the HEMT 200 obtained by the above method, the semiconductor element layer 103 is composed of In x Ga y Al 1-xy N having a lattice constant difference with GaN within ± 1%. In the buffer layer 102, the unit layer 2-n (FIG. 2) in contact with the semiconductor element layer 103 is made of Al 1-a In a N having an InN mixed crystal ratio a of 0.1 or more and 0.25 or less. The unit layer 2-n has substantially the same lattice constant as that of the semiconductor element layer 103, and can effectively prevent generation of crystal defects near the boundary between the buffer layer 102 and the semiconductor element layer 103. Further, the unit layer 2-1 (FIG. 2) in contact with the SiC single crystal substrate 101 of the buffer layer 102 is an Al 1-a In a N having an InN mixed crystal ratio a of 0, that is, an AlN layer, so that an SiC single layer is obtained. It is possible to effectively suppress the occurrence of crystal defects near the boundary with the SiC single crystal substrate 101 by reducing the lattice constant difference with the crystal substrate 101.
[0025]
Hereinafter, various modifications of the present invention will be described.
The InN mixed crystal ratio a of the buffer layer 102 may be continuously changed in the layer thickness direction as shown in FIG. In order to form such a buffer layer 102, the flow rate ratio of the organometallic gas serving as the In source and the Al source may be controlled to be continuously changed by a mass flow controller or the like during growth by the MOVPE method.
[0026]
As shown in FIG. 5, the buffer layer 102 has an InN mixed crystal ratio near the boundary with the substrate (single crystal substrate) as a1, and an InN mixed crystal ratio near the boundary with the semiconductor element layer an (wherein, an> a1), the distribution of the InN mixed crystal ratio a in the layer thickness direction increases and decreases from the single crystal substrate side toward the semiconductor element layer side while repeatedly increasing and decreasing with a fluctuation range smaller than an-a1. It can also be formed to show a tendency. When a layer having a higher InN mixed crystal ratio is formed on the preceding layer toward the semiconductor element layer side, the lattice constant is increased by an increment of the InN mixed crystal ratio. Stress acts. When the tensile stress level is high, crystal defects such as cracks and peeling are likely to occur between adjacent layers. Therefore, after a layer having a high InN mixed crystal ratio is formed, if a layer having a low InN mixed crystal ratio with a reduced lattice constant is grown on the layer, the above-mentioned high InN mixed crystal ratio is increased by the compressive stress caused by the layer. The tensile stress due to the layers is offset, and the generation of crystal defects between the layers can be made more difficult to occur. Specifically, the buffer layer of FIG. 5 has a structure in which a plurality of unit layers each having a constant InN mixed crystal ratio are laminated in such a manner that the InN mixed crystal ratio alternately increases and decreases toward the semiconductor element layer side. It has become.
[0027]
Further, in the above embodiment, the buffer layer 2 is almost entirely configured as an AlInN layer except that the vicinity of the boundary with the substrate 101 is AlN, and the AlInN layer is in contact with the semiconductor element layer. As shown in FIG. 6, the buffer layer is formed as having an auxiliary layer in which a GaN layer and an InGaAlN layer are alternately stacked between the AlInN layer and the semiconductor element layer. You can also. As a result, it is possible to more effectively prevent the semiconductor element layer from having a crystal defect due to lattice mismatch with the substrate.
[0028]
In the embodiment described above, the compound semiconductor element is configured as a HEMT. However, the present invention is also applied to other ultrahigh-speed transistors such as MESFET (Metal-Semiconductor Field Effect Transistor) and HBT (Hetero Bipolar Transistor). You can also. Further, the compound semiconductor element can be configured as a light emitting element as shown in FIG. The light-emitting element 1 (shown in a schematic cross section of the main part) is formed of In x Ga y Al 1-x- via a buffer layer 2 on a sapphire substrate (hereinafter also simply referred to as a substrate) 1 as a single crystal substrate. The semiconductor element layer 50 made of yN (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) is formed. The buffer layer 2 is configured in the same manner as the buffer layer 102 shown in FIG. 2, FIG. 3, FIG. 4, or FIG. The main part of the semiconductor element layer 50 is composed of an In a Ga b Al 1-ab N active layer (non-doped) 5, a p-type In x Ga y Al 1-xy N clad layer (p-type dopant). Is sandwiched between 6 and n-type In x Ga y Al 1-xy N layer (where n-type dopant is Si: hereinafter also referred to as n-type cladding layer) 4, for example. This is a light emitting layer portion 24 having a double hetero structure. In this embodiment, the p-type cladding layer 6 and the n-type cladding layer 4 contain AlN, and form a potential barrier that advantageously acts on the GaN active layer 5 to confine carriers in the active layer 5. ing.
[0029]
In this embodiment, light is extracted from the p-type cladding layer 6 side. On the p-type cladding layer 6, a current diffusion layer (p-type dopant concentration higher than that of the p-type cladding layer 6) ( 7 is formed, and an electrode 9 for light emission drive is provided on the current diffusion layer 7. On the other hand, between the buffer layer 2 and the n-type cladding layer 4, a backside low-resistance layer having a higher n-type dopant concentration than the n-type cladding layer 4 (for example, made of GaN: a part of the semiconductor element layer 50) 3) is arranged. The back surface low resistance layer 3 extends outward in the in-plane direction of the light emitting layer portion 24 on the main surface of the substrate 1, and an electrode 15 for light emission driving is provided in the extending region.
[0030]
In the light emitting device 100 of FIG. 7, the sapphire substrate 1 is incorporated as part of the device structure, but the insulating sapphire substrate 1 is peeled off and an electrode is formed on the peeled surface side of the light emitting layer portion. The formed element structure can also be used.
[0031]
Further, a SiC substrate may be used instead of the sapphire substrate 1. Since the SiC substrate has high conductivity, the back surface low resistance layer 3 is omitted, while an electrode 15 is provided on the back surface of the SiC substrate, and energization for light emission driving is performed by forming a conduction path in the thickness direction of the SiC substrate. It is possible to do.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a HEMT which is an example of a compound semiconductor device of the present invention.
2 is a schematic cross-sectional view showing details of a buffer layer in the HEMT of FIG. 1. FIG.
3 is a schematic diagram showing a layer thickness direction distribution of InN mixed crystal ratio in the buffer layer of FIG. 2; FIG.
FIG. 4 is a schematic diagram showing a first modification of the distribution in the layer thickness direction of the InN mixed crystal ratio of the buffer layer.
FIG. 5 is a schematic diagram showing a second modification of the distribution in the layer thickness direction of the InN mixed crystal ratio of the buffer layer.
FIG. 6 is a schematic diagram showing still another modified example of the buffer layer.
FIG. 7 is a cross-sectional view schematically showing a light emitting element which is another example of the compound semiconductor element of the present invention.
[Explanation of symbols]
1 Sapphire substrate (single crystal substrate)
2 Buffer layers 50 and 103 Semiconductor element layer 100 Light emitting element (compound semiconductor element)
101 SiC single crystal substrate 200 HEMT (compound semiconductor device)

Claims (2)

  1. The semiconductor element layer made of In x Ga y Al 1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) has at least a partial section in the layer thickness direction of Al 1. -A In a N (a is an InN mixed crystal ratio, 0 <a <1), and is epitaxially grown on a single crystal substrate made of either SiC or sapphire through a buffer layer made of an AlInN layer,
    In the AlInN layer in the buffer layer, the InN mixed crystal ratio a increases stepwise or continuously from the boundary on the single crystal substrate side toward the boundary on the semiconductor element layer side,
    The buffer layer is disposed between the AlInN layer and the semiconductor element layer such that an auxiliary layer in which a GaN layer and an InGaAlN layer are alternately stacked is in contact with the AlInN layer and the semiconductor element layer. compound semiconductor device, characterized in that there.
  2. On the single crystal substrate made of either SiC or sapphire, at least a partial section in the layer thickness direction is Al 1-a In a N (where a is an InN mixed crystal ratio, 0 <a <1), and the single crystal substrate Epitaxially growing a buffer layer having an AlInN layer in which the InN mixed crystal ratio a is increased stepwise or continuously from the side boundary, and an auxiliary layer in which a GaN layer and an InGaAlN layer are alternately stacked on the AlInN layer And a process of
    A step of epitaxially growing a semiconductor element layer made of In x Ga y Al 1-xy N (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) on the buffer layer;
    The manufacturing method of the compound semiconductor element characterized by the above-mentioned.
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* Cited by examiner, † Cited by third party
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JP4939014B2 (en) * 2005-08-30 2012-05-23 サムソン エレクトロ−メカニックス カンパニーリミテッド. Group III nitride semiconductor light emitting device and method for manufacturing group III nitride semiconductor light emitting device
JP5116977B2 (en) * 2006-02-17 2013-01-09 古河電気工業株式会社 Semiconductor element
JP4908886B2 (en) * 2006-03-23 2012-04-04 日本電信電話株式会社 Semiconductor device
JP2008085123A (en) * 2006-09-28 2008-04-10 Covalent Materials Corp Substrate for compound semiconductor device, and the compound semiconductor device using the same
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JP4514063B2 (en) * 2007-08-30 2010-07-28 古河電気工業株式会社 ED type inverter circuit and integrated circuit element
JP5477685B2 (en) * 2009-03-19 2014-04-23 サンケン電気株式会社 Semiconductor wafer, semiconductor element and manufacturing method thereof
KR101384071B1 (en) * 2009-03-20 2014-04-10 주식회사 엘지실트론 Nitride semiconductor substrate, method for fabricating the substrate and light emitting diode including the substrate
JP2011049271A (en) 2009-08-26 2011-03-10 Sanken Electric Co Ltd Semiconductor apparatus
JP2012004283A (en) * 2010-06-16 2012-01-05 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JP5672926B2 (en) * 2010-10-08 2015-02-18 富士通株式会社 Compound semiconductor device and manufacturing method thereof
KR101790054B1 (en) * 2011-05-13 2017-11-20 엘지이노텍 주식회사 Light emitting device
TWI587512B (en) 2011-05-16 2017-06-11 Renesas Electronics Corp Field effect transistor and semiconductor device
JP5495069B2 (en) * 2011-05-17 2014-05-21 古河電気工業株式会社 Semiconductor device and manufacturing method thereof
KR101824879B1 (en) * 2011-07-29 2018-03-14 엘지이노텍 주식회사 Light emitting device
US9165766B2 (en) 2012-02-03 2015-10-20 Transphorm Inc. Buffer layer structures suited for III-nitride devices with foreign substrates
US9583574B2 (en) 2012-09-28 2017-02-28 Intel Corporation Epitaxial buffer layers for group III-N transistors on silicon substrates
JP2015095605A (en) * 2013-11-13 2015-05-18 住友電気工業株式会社 Semiconductor device and semiconductor substrate

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