JP5824814B2

JP5824814B2 - Semiconductor wafer, semiconductor element, and manufacturing method thereof

Info

Publication number: JP5824814B2
Application number: JP2011010987A
Authority: JP
Inventors: 将貴柳原
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2011-01-21
Filing date: 2011-01-21
Publication date: 2015-12-02
Anticipated expiration: 2031-01-21
Also published as: JP2012151422A

Description

本発明は、半導体ウエーハ及び半導体素子及びその製造方法に関し、特に、シリコン又はシリコン化合物から成る基板上に窒化物半導体をエピタキシャル成長させた半導体ウエーハ、及びこの半導体ウエーハで形成されたＨＥＭＴ、ＭＥＳＦＥＴ、ＳＢＤ（ショットキーバリアーダイオード）、ＬＥＤ（発光ダイオード）等の半導体素子及びその製造方法に関するものである。 The present invention relates to a semiconductor wafer, a semiconductor element, and a manufacturing method thereof, and more particularly, a semiconductor wafer obtained by epitaxially growing a nitride semiconductor on a substrate made of silicon or a silicon compound, and HEMT, MESFET, SBD ( The present invention relates to a semiconductor element such as a Schottky barrier diode) and an LED (light emitting diode) and a manufacturing method thereof.

シリコン基板上に窒化物半導体をエピタキシャル成長させた半導体ウエーハは、特許文献１等に開示されている。シリコン基板はサファイア基板に比べて低コストであるという特長を有する。しかし、シリコン基板の線膨張係数は約３．５９×１０^−６／Ｋ、窒化物半導体としてのＧａＮの線膨張係数は約５．５９×１０^−６／Ｋであり、両者の間に比較的大きな差がある。なお、ＧａＮ以外の窒化物半導体の線膨張係数もシリコン基板の線膨張係数よりも大きい。また、シリコンと窒化物半導体は格子定数が互いに相違する。このため、シリコン基板上に窒化物半導体を形成すると、窒化物半導体に応力が加わり、ここにクラックや転位が発生し易い。 A semiconductor wafer obtained by epitaxially growing a nitride semiconductor on a silicon substrate is disclosed in Patent Document 1 and the like. A silicon substrate has a feature that the cost is lower than that of a sapphire substrate. However, the linear expansion coefficient of the silicon substrate is about 3.59 × 10 ⁻⁶ / K, and the linear expansion coefficient of GaN as a nitride semiconductor is about 5.59 × 10 ⁻⁶ / K. There is a big difference. In addition, the linear expansion coefficient of nitride semiconductors other than GaN is also larger than the linear expansion coefficient of a silicon substrate. Silicon and nitride semiconductors have different lattice constants. For this reason, when a nitride semiconductor is formed on a silicon substrate, stress is applied to the nitride semiconductor, and cracks and dislocations are likely to occur here.

この問題を解決するために上記特許文献１の技術では、シリコン基板上に多層構造バッファ領域が設けられ、このバッファ領域の上に半導体素子形成用の窒化物半導体領域がエピタキシャル成長されている。上記多層構造バッファ領域は良好な応力緩和効果を有するので、バッファ領域上の半導体素子形成用の窒化物半導体領域のクラックや転位が減少する。 In order to solve this problem, in the technique disclosed in Patent Document 1, a multilayer buffer region is provided on a silicon substrate, and a nitride semiconductor region for forming a semiconductor element is epitaxially grown on the buffer region. Since the multilayer buffer region has a good stress relaxation effect, cracks and dislocations in the nitride semiconductor region for forming a semiconductor element on the buffer region are reduced.

しかし、シリコン基板の上に比較的厚いバッファ領域を介して窒化物半導体から成る素子用の主半導体領域を形成すると、半導体ウエーハに反りが生じる。この半導体ウエーハの反りは、主半導体領域の厚みが増大するに従って増大する。また、半導体ウエーハの面積（直径）が増大するに従って反りも増大する。なお、主半導体領域の厚みを増大させることは、半導体素子の縦方向（厚み方向）における耐圧を高めるために要求される。周知のように主半導体領域の厚みが厚いほど主半導体領域の一方の主面と他方の主面との間の耐圧が高くなる。半導体ウエーハの面積（直径）を増大させることは、半導体素子のコストを低減するために要求される。半導体ウエーハの面積（直径）が増大すると、一枚の半導体ウエーハから形成できる半導体素子の個数が多くなり、半導体素子のコストを低減することが可能になる。 However, if a main semiconductor region for a device made of a nitride semiconductor is formed on a silicon substrate via a relatively thick buffer region, the semiconductor wafer is warped. The warpage of the semiconductor wafer increases as the thickness of the main semiconductor region increases. Further, the warpage increases as the area (diameter) of the semiconductor wafer increases. Increasing the thickness of the main semiconductor region is required to increase the breakdown voltage in the vertical direction (thickness direction) of the semiconductor element. As is well known, the greater the thickness of the main semiconductor region, the higher the breakdown voltage between one main surface and the other main surface of the main semiconductor region. Increasing the area (diameter) of the semiconductor wafer is required to reduce the cost of the semiconductor element. As the area (diameter) of the semiconductor wafer increases, the number of semiconductor elements that can be formed from one semiconductor wafer increases, and the cost of the semiconductor elements can be reduced.

シリコン基板の上に窒化物半導体を形成する別の方法として、ＡｌＧａＮ層とＧａＮ層とを繰り返し積層した構成をそれぞれ有する第１及び第２の超格子層とこれ等の間に配置したＧａＮ層とから成るバッファ領域をシリコン基板の上に設け、このバッフア領域の上に主半導体領域のためのＧａＮ層を設ける方法が非特許文献１に開示されている。また、非特許文献２には特許文献３のＡｌＧａＮ層とＧａＮ層とから成る超格子層の代わりにＡｌＮ層とＧａＮ層とから成る超格子層を設けることが開示されている。 As another method of forming a nitride semiconductor on a silicon substrate, first and second superlattice layers each having a configuration in which an AlGaN layer and a GaN layer are repeatedly stacked, and a GaN layer disposed between them, Non-Patent Document 1 discloses a method of providing a buffer region made of a silicon substrate on a silicon substrate and providing a GaN layer for a main semiconductor region on the buffer region. Non-Patent Document 2 discloses that a superlattice layer composed of an AlN layer and a GaN layer is provided instead of the superlattice layer composed of an AlGaN layer and a GaN layer in Patent Document 3.

非特許文献１及び２の方法を採用すると、主半導体領域のためのＧａＮ層のクラック及び結晶性が改善される。しかし、主半導体領域を厚く形成すると反りの問題が発生する。 When the methods of Non-Patent Documents 1 and 2 are adopted, the crack and crystallinity of the GaN layer for the main semiconductor region are improved. However, when the main semiconductor region is formed thick, a problem of warpage occurs.

そこで、特許文献２では、第１の多層構造バッファ領域の他に、平均的に見た格子定数が第１の多層構造バッファ領域よりも大きい第２の多層構造バッファ領域を主半導体領域と第１の多層構造バッファ領域との間に設けるようにした。それにより、半導体ウエーハの反りが改善されるのみでなく、バッファ領域及び主半導体領域を厚くすることができるようになった。 Therefore, in Patent Document 2, in addition to the first multilayer structure buffer area, a second multilayer structure buffer area having an average lattice constant larger than that of the first multilayer structure buffer area is defined as a main semiconductor area and a first semiconductor area. The multi-layer structure buffer area is provided. As a result, not only the warpage of the semiconductor wafer is improved, but also the buffer region and the main semiconductor region can be made thicker.

特開２００３−５９９４８号公報JP 2003-59948 A 特開２００８−２１８４７９号公報JP 2008-218479 A

Applied Physics Letters, Volume 75,Number 14, October 4,1999, S.A.Nikishin, High quality GaN grown on Si(111) by gas source molecular beam epitaxy with ammoniaApplied Physics Letters, Volume 75, Number 14, October 4,1999, S.A.Nikishin, High quality GaN grown on Si (111) by gas source molecular beam epitaxy with ammonia Applied Physics Letters, Volume 79, Number 20, November 12, 2001, Eric Feltin, et.al.「Stree control in GaN grown on Si(111) by metalorganic vapor phase epitaxy」Applied Physics Letters, Volume 79, Number 20, November 12, 2001, Eric Feltin, et.al.``Stree control in GaN grown on Si (111) by metalorganic vapor phase epitaxy ''

半導体デバイスの応用範囲を広げるためには、更に優れた特性を実現することが重要である。ＬＥＤ等の発光デバイスでは発光層を約２ｎｍ程度の非常に薄い膜で形成しており、この膜を品質良く作製することが発光デバイスの特性向上に重要である。薄い膜を品質良く成膜するには下地の平坦性が十分保たれていることが必要であり、発光層（主半導体領域）の平坦性を向上させることは重要である。スイッチング素子等の電子デバイスにおいても、同様にキャリアが流れるチャネル領域は１０ｎｍ以下と非常に薄く、この電子密度と移動度を上げることが特性向上に重要である。ここでも主半導体領域の平坦性を向上させることで、特性を改善することができる。しかしながら、従来の技術を用いてはクラックの少ないウエーハ作製を実現できたが、多層構造バッファ領域が厚くなることで表面の平坦性が悪化するという問題があった。 In order to expand the application range of semiconductor devices, it is important to realize even better characteristics. In a light emitting device such as an LED, the light emitting layer is formed with a very thin film of about 2 nm, and it is important to improve the characteristics of the light emitting device to produce this film with high quality. In order to form a thin film with good quality, it is necessary that the flatness of the base is sufficiently maintained, and it is important to improve the flatness of the light emitting layer (main semiconductor region). Similarly, in an electronic device such as a switching element, the channel region in which carriers flow is very thin as 10 nm or less, and it is important to improve the characteristics to increase the electron density and mobility. Again, the characteristics can be improved by improving the flatness of the main semiconductor region. However, although the wafer fabrication with few cracks can be realized by using the conventional technique, there is a problem that the flatness of the surface is deteriorated due to the thick multilayer structure buffer region.

本発明の目的は、上記の課題に鑑み、クラックが少なく表面の平坦性が良好な半導体ウエーハ及び半導体素子及びその製造方法を提供することにある。 In view of the above-described problems, an object of the present invention is to provide a semiconductor wafer, a semiconductor element, and a method for manufacturing the same, with few cracks and good surface flatness.

本発明に係る半導体ウエーハ及び半導体素子及びその製造方法は、上記の目的を達成するため、次のように構成される。 In order to achieve the above object, a semiconductor wafer, a semiconductor element, and a manufacturing method thereof according to the present invention are configured as follows.

第１の半導体ウエーハ（請求項１に対応）は、基板と、前記基板の一方の主面上に配置され且つ化合物半導体で形成されたバッファ領域と、前記バッファ領域の上に配置され且つ化合物半導体で形成された主半導体領域とを有する半導体ウエーハであって、前記バッファ領域は、第１の多層構造バッファ領域と、前記基板と前記第１の多層構造バッファ領域との間に配置された第２の多層構造バッファ領域とから成り、前記第１の多層構造バッファ領域はサブ多層構造バッファ領域と単層構造バッファ領域が交互に４組〜２０組積層された交互積層体から成り、前記サブ多層構造バッファ領域は交互に配置された複数の第１及び第２の層を含み、前記第１の層は前記基板を構成する材料よりも小さい格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第２の層は前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記単層構造バッファ領域は前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記第１の層及び前記第２の層よりも厚く形成され、前記第２の多層構造バッファ領域は交互に配置された複数の第３及び第４の層を含み、前記第３の層は前記基板を構成する材料よりも小さい格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第４の層は前記第３の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第１の多層構造バッファ領域は前記主半導体領域の平均的に見た格子定数よりも小さい平均的に見た格子定数を有し、前記第２の多層構造バッファ領域は、前記主半導体領域と前記サブ多層構造バッファ領域の平均的に見た格子定数よりも小さい平均的に見た格子定数を有していることを特徴とする。
第２の半導体ウエーハ（請求項２に対応）は、上記の構成において、好ましくは、前記第２の多層構造バッファ領域は、少なくとも第３の層及び第４の層をそれぞれ３層以上含んでいることを特徴とする。
第３の半導体ウエーハ（請求項３に対応）は、上記の構成において、好ましくは、前記第２の多層構造バッファ領域に含まれる複数の第３の層は、前記基板から前記第１の多層構造バッファ領域に向かって徐々に減少するように互いに異なる厚みを有していることを特徴とする。
第４の半導体ウエーハ（請求項４に対応）は、上記の構成において、好ましくは、前記第２の多層構造バッファ領域に含まれる複数の第４の層は、前記基板から前記第１の多層構造バッファ領域に向かって徐々に増大するように互いに異なる厚みを有していることを特徴とする。
第１の半導体素子（請求項５に対応）は、基板と、前記基板の一方の主面上に配置され且つ化合物半導体で形成されたバッファ領域と、前記バッファ領域の上に配置され且つ化合物半導体で形成された主半導体領域と、前記主半導体領域上に配置された少なくとも第１及び第２の主電極と、前記主半導体領域上に配置され且つ前記第１及び第２の主電極間の電流の流れを制御する機能を有している制御電極と、前記基板の他方の主面に形成され且つ前記第１又は第２の主電極に電気的にされている補助電極とを備えた半導体素子であって、前記バッファ領域は、第１の多層構造バッファ領域と、前記基板と前記第１の多層構造バッファ領域の間に配置された第２の多層構造バッファ領域とから成り、前記第１の多層構造バッファ領域はサブ多層構造バッファ領域と単層構造バッファ領域が交互に４組〜２０組積層された交互積層体から成り、前記サブ多層構造バッファ領域は交互に配置された複数の第１及び第２の層を含み、前記第１の層は前記基板を構成する材料よりも小さい格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第２の層は前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記単層構造バッファ領域は前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記第１の層及び前記第２の層よりも厚く形成され、前記第２の多層構造バッファ領域は交互に配置された複数の第３及び第４の層を含み、前記第３の層は前記基板を構成する材料よりも小さい格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第４の層は前記第３の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成り且つ前記単層構造バッファ領域よりも薄く形成され、前記第１の多層構造バッファ領域は前記主半導体領域の平均的に見た格子定数よりも小さい平均的に見た格子定数を有し、前記第２の多層構造バッファ領域は、前記主半導体領域と前記サブ多層構造バッファ領域の平均的に見た格子定数よりも小さい平均的に見た格子定数を有していることを特徴とする。
第１の半導体ウエーハの製造方法（請求項６に対応）は、基板の一方の主面上に化合物半導体から成るバッファ領域と、前記バッファ領域の上に配置され且つ化合物半導体で形成された主半導体領域とを有する半導体ウエーハを製造する方法において、前記基板の上に、前記基板を構成する材料よりも小さい格子定数を有する化合物半導体から成る第３の層と前記第３の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成る第４の層との積層体を含み、且つ平均的に見た格子定数が、第１の多層構造バッファ領域の平均的に見た格子定数よりも小さい第２の多層構造バッファ領域を形成する第１の工程と、前記基板を構成する材料の格子定数よりも小さい格子定数を有する化合物半導体から成る第１の層と前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成る第２の層との交互積層体から成るサブ多層構造バッファ領域を前記基板の一方の主面上に形成する第２の工程と、前記サブ多層構造バッファ領域の上に、前記第１の層の格子定数と前記基板の格子定数との間の格子定数を有する化合物半導体から成る単層構造バッファ領域を前記第２の層よりも厚く形成する第３の工程と、前記第２及び第３の工程と同一の方法で前記サブ多層構造バッファ領域と実質的に同一の構成を有する別のサブ多層構造バッファ領域及び前記単層構造バッファ領域と実質的に同一の構成を有する別の単層構造バッファ領域を繰り返して形成して前記サブ多層構造バッファ領域と前記単層構造バッファ領域とが交互に４組〜２０組積層された第１の多層構造バッファ領域を得る第４の工程と、前記バッファ領域の上に化合物半導体から成り且つ平均的に見た格子定数が、前記第１及び第２の多層構造バッファ領域の平均的に見た格子定数よりも大きい主半導体領域を形成する第５の工程と、を有していることを特徴とする。
A first semiconductor wafer (corresponding to claim 1) includes a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and a compound semiconductor disposed on the buffer region. A semiconductor wafer having a main semiconductor region formed by the first semiconductor layer, wherein the buffer region is a first multilayer structure buffer region, and a second multilayer disposed between the substrate and the first multilayer structure buffer region. The first multi-layer structure buffer region is composed of an alternating laminate in which 4 to 20 sets of sub-multi-layer structure buffer regions and single-layer structure buffer regions are alternately laminated, and the sub-multi-layer structure is provided. The buffer region includes a plurality of first and second layers arranged alternately, and the first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate. The second layer is formed of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed thinner than the single layer structure buffer region. The single-layer structure buffer region is formed of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed of the first layer and the second layer. The second multilayer buffer region includes a plurality of third and fourth layers arranged alternately, and the third layer is a lattice smaller than the material constituting the substrate. A compound semiconductor made of a compound semiconductor having a constant and formed thinner than the single layer structure buffer region, wherein the fourth layer has a lattice constant between the lattice constant of the third layer and the lattice constant of the substrate Made of And the first multi-layer structure buffer region has an average lattice constant smaller than an average lattice constant of the main semiconductor region, and The multilayer buffer region 2 has an average lattice constant smaller than an average lattice constant of the main semiconductor region and the sub multilayer buffer region.
In the above structure, the second semiconductor wafer (corresponding to claim 2) is preferably configured such that the second multilayer buffer region includes at least a third layer and a fourth layer, respectively. It is characterized by that.
In the above structure, the third semiconductor wafer (corresponding to claim 3) is preferably configured such that the plurality of third layers included in the second multilayer buffer region are formed from the substrate to the first multilayer structure. The thicknesses are different from each other so as to gradually decrease toward the buffer region.
The fourth semiconductor wafer (corresponding to claim 4) is preferably configured such that the plurality of fourth layers included in the second multilayer buffer region are formed from the substrate to the first multilayer structure. The thicknesses are different from each other so as to gradually increase toward the buffer region.
A first semiconductor element (corresponding to claim 5) includes a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and a compound semiconductor disposed on the buffer region. A main semiconductor region formed on the main semiconductor region, at least first and second main electrodes disposed on the main semiconductor region, and a current between the first and second main electrodes disposed on the main semiconductor region. A semiconductor device comprising a control electrode having a function of controlling the flow of the liquid and an auxiliary electrode formed on the other main surface of the substrate and electrically connected to the first or second main electrode The buffer region includes a first multilayer structure buffer region, and a second multilayer structure buffer region disposed between the substrate and the first multilayer structure buffer region. Multi-layer buffer area is sub-many Consists alternate laminate structure buffer region and a single-layer structure buffer area is four sets 20 sets stacked alternately, the sub-multi-layer structure buffer region includes a plurality of first and second layers which are alternately arranged, The first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single layer structure buffer region, and the second layer has a lattice constant of the first layer. And a single layer structure buffer region formed of a compound semiconductor having a lattice constant between the lattice constant of the first layer and that of the substrate. The second multilayer buffer region is made of a compound semiconductor having a lattice constant between the first layer and the second layer, and the second multilayer structure buffer regions are alternately arranged. The third layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single-layer structure buffer region, and the fourth layer is The first multilayer buffer region is made of a compound semiconductor having a lattice constant between the lattice constant of the third layer and the lattice constant of the substrate and is formed thinner than the single layer structure buffer region. The second multilayer buffer region has an average lattice constant smaller than an average lattice constant of the semiconductor region, and the second multilayer buffer region is an average of the main semiconductor region and the sub multilayer buffer region. It has an average lattice constant smaller than the lattice constant.
A first semiconductor wafer manufacturing method (corresponding to claim 6) includes a buffer region made of a compound semiconductor on one main surface of a substrate, and a main semiconductor disposed on the buffer region and formed of the compound semiconductor. In the method of manufacturing a semiconductor wafer having a region, a third layer made of a compound semiconductor having a lattice constant smaller than a material constituting the substrate, a lattice constant of the third layer, and the third layer are formed on the substrate. Including a stacked body with a fourth layer made of a compound semiconductor having a lattice constant between the lattice constant of the substrate and an average lattice constant seen in the first multilayer buffer region A first step of forming a second multilayer structure buffer region smaller than the lattice constant, a first layer made of a compound semiconductor having a lattice constant smaller than the lattice constant of the material constituting the substrate, and A sub-multilayer structure buffer region composed of an alternating laminate of a second layer made of a compound semiconductor having a lattice constant between the lattice constant of one layer and the lattice constant of the substrate is formed on one main surface of the substrate. A second step of forming, and a single-layer structure buffer region made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate on the sub-multilayer structure buffer region A third step of forming a thicker layer than the second layer, and another sub-multilayer structure buffer having substantially the same configuration as the sub-multilayer structure buffer region by the same method as the second and third steps And another single-layer structure buffer region having substantially the same configuration as the single-layer structure buffer region is repeatedly formed, and the sub-multilayer structure buffer region and the single-layer structure buffer region are alternately set in four sets to 20 A fourth step of obtaining a laminated first multilayer buffer area, and average seen lattice constant consists of a compound semiconductor on said buffer area, said first and second multi-layer structure buffer region And a fifth step of forming a main semiconductor region larger than the lattice constant viewed on average.

本発明によれば、クラックが少なく表面の平坦性が良好な半導体ウエーハ及び半導体装置及びその製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor wafer, a semiconductor device, and a method for manufacturing the same, with few cracks and good surface flatness.

本発明の第１実施形態に係る半導体素子としての高電子移動度トランジスタ即ちＨＥＭＴ（High Electron Mobility Transistor ）を形成するための半導体ウエーハ１を示す図である。1 is a diagram showing a semiconductor wafer 1 for forming a high electron mobility transistor (HEMT) as a semiconductor element according to a first embodiment of the present invention. 図１の半導体ウエーハ１をその厚み方向に拡大してバッファ領域３及び主半導体領域４を詳しく示した半導体ウエーハ１を示す図である。FIG. 2 is a view showing a semiconductor wafer 1 in which the semiconductor wafer 1 of FIG. 図２のバッファ領域３の一部を更に拡大したものを示す図である。It is a figure which shows what expanded a part of buffer area | region 3 of FIG. 図１〜図３に示した半導体ウエーハ１を使用して製作したＨＥＭＴを示す図である。It is a figure which shows HEMT manufactured using the semiconductor wafer 1 shown in FIGS. 本発明の第２実施形態に係る半導体ウエーハのバッファ領域３の一部を拡大したものを示す図である。It is a figure showing what expanded a part of buffer field 3 of a semiconductor wafer concerning a 2nd embodiment of the present invention. 本発明の第３実施形態に係る半導体ウエーハのバッファ領域３の一部を拡大したものを示す図である。It is a figure which shows what expanded a part of buffer area | region 3 of the semiconductor wafer which concerns on 3rd Embodiment of this invention.

以下に、本発明の好適な実施形態を添付図面に基づいて説明する。 Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

図１は、本発明の第１実施形態に係る半導体素子としての高電子移動度トランジスタ即ちＨＥＭＴ（High Electron Mobility Transistor ）を形成するための半導体ウエーハ１を示す図である。半導体ウエーハ１は、図１に概略的に示すようにシリコン基板２と、この基板２の一方の主面上に配置され且つ窒化物半導体で形成されたバッファ領域３と、バッファ領域３の上に配置され且つ窒化物半導体で形成された半導体素子形成用の主半導体領域４とを有する。この半導体ウエーハ１は複数個のＨＥＭＴを形成できる面積を有する。 FIG. 1 is a view showing a semiconductor wafer 1 for forming a high electron mobility transistor (HEMT) as a semiconductor element according to the first embodiment of the present invention. As schematically shown in FIG. 1, the semiconductor wafer 1 includes a silicon substrate 2, a buffer region 3 disposed on one main surface of the substrate 2 and formed of a nitride semiconductor, and a buffer region 3. And a main semiconductor region 4 for forming a semiconductor element, which is disposed and formed of a nitride semiconductor. The semiconductor wafer 1 has an area where a plurality of HEMTs can be formed.

基板２は、例えば３５０〜１２００μｍの厚みを有し且つバッファ領域３及び主半導体領域４よりも大きい格子定数（例えば０．５４３ｎｍ）を有し且つバッファ領域３の線膨張係数（例えば４．１５×１０^−６／Ｋ）及び主半導体領域４の線膨張係数（例えば５．５９×１０^−６／Ｋ）よりも小さい線膨張係数（例えば３．５９×１０^−６／Ｋ）を有する単結晶シリコンから成っている。そして、基板２は、バッファ領域３及び主半導体領域４の成長基板としての機能と機械的支持基板としての機能とを有している。また、基板２は、主半導体領域４に形成される半導体素子の動作を安定化させるための補助電極を支持する機能を有する。なお、このシリコン基板２に、必要に応じてボロン（Ｂ）等の３族元素又はリン（Ｐ）等の５族元素からなる導電型決定不純物を添加することができる。また、基板２をＳｉＣ等のシリコン化合物で形成することもできる。 The substrate 2 has a thickness of, for example, 350 to 1200 μm, a lattice constant (for example, 0.543 nm) larger than that of the buffer region 3 and the main semiconductor region 4, and a linear expansion coefficient (for example, 4.15 ×) of the buffer region 3. 10 ⁻⁶ / K) and a single crystal silicon having a linear expansion coefficient (for example, 3.59 × 10 ⁻⁶ / K) smaller than that of the main semiconductor region 4 (for example, 5.59 × 10 ⁻⁶ / K). Consists of. The substrate 2 has a function as a growth substrate for the buffer region 3 and the main semiconductor region 4 and a function as a mechanical support substrate. The substrate 2 has a function of supporting an auxiliary electrode for stabilizing the operation of the semiconductor element formed in the main semiconductor region 4. A conductivity determining impurity composed of a Group 3 element such as boron (B) or a Group 5 element such as phosphorus (P) can be added to the silicon substrate 2 as necessary. The substrate 2 can also be formed of a silicon compound such as SiC.

図２は、図１の半導体ウエーハ１をその厚み方向に拡大してバッファ領域３及び主半導体領域４を詳しく示した半導体ウエーハ１を示す図である。図３は、図２のバッファ領域３の一部を更に拡大したものを示す図である。なお、図１及び図２における基板２及び各領域３，４の厚み、及び図３における多層構造バッファ領域の厚みは説明的に示されており、実際の厚みとは異なる。 FIG. 2 is a view showing the semiconductor wafer 1 in which the semiconductor wafer 1 of FIG. 1 is enlarged in the thickness direction and the buffer region 3 and the main semiconductor region 4 are shown in detail. FIG. 3 is a diagram showing a further enlarged portion of the buffer area 3 of FIG. Note that the thicknesses of the substrate 2 and each of the regions 3 and 4 in FIGS. 1 and 2 and the thickness of the multilayer structure buffer region in FIG. 3 are shown in an explanatory manner and are different from the actual thickness.

バッファ領域３は、図２に示すように厚みＴａの第１の多層構造バッファ領域５と、基板２と第１の多層構造バッファ領域５との間に配置された厚みＴｂの第２の多層構造バッファ領域８を有する。また、バッファ領域３は、基板２と第２の多層構造バッファ領域８との間にバッファ層９，１０を有する。第１の多層構造バッファ領域５は、図２においてサブ（下位又は副）多層構造バッファ領域６と単層構造バッファ領域７との交互積層体から成る。図２では図示の都合上第１の多層構造バッファ領域５の一部が省かれ、７個のサブ多層構造バッファ領域６と７個の第１の単層構造バッファ領域７とで示されているが、第１の多層構造バッファ領域５におけるサブ多層構造バッファ領域６と第１の単層構造バッファ領域７とのペアの数を任意に変えることができる。しかし、第１の多層構造バッファ領域５におけるサブ多層構造バッファ領域６と第１の単層構造バッファ領域７とのペアの数を、好ましくは４〜２０、より好ましくは８〜１５にすることが望ましい。このペア数が４よりも少ない場合、及び２０よりも大きい場合には半導体ウエーハの反り及び主半導体領域４の結晶性の改善効果が低下する。 As shown in FIG. 2, the buffer region 3 includes a first multilayer structure buffer region 5 having a thickness Ta and a second multilayer structure having a thickness Tb disposed between the substrate 2 and the first multilayer structure buffer region 5. It has a buffer area 8. The buffer region 3 includes buffer layers 9 and 10 between the substrate 2 and the second multilayer structure buffer region 8. The first multilayer structure buffer region 5 is composed of an alternating stack of sub (lower or sub) multilayer structure buffer regions 6 and single layer structure buffer regions 7 in FIG. In FIG. 2, a part of the first multilayer buffer area 5 is omitted for convenience of illustration, and is shown by seven sub multilayer buffer areas 6 and seven first single-layer buffer areas 7. However, the number of pairs of the sub multilayer buffer region 6 and the first single layer buffer region 7 in the first multilayer buffer region 5 can be arbitrarily changed. However, the number of pairs of the sub multi-layer structure buffer region 6 and the first single layer structure buffer region 7 in the first multi-layer structure buffer region 5 is preferably 4 to 20, more preferably 8 to 15. desirable. If the number of pairs is less than 4 or greater than 20, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is reduced.

図２においては、各サブ多層構造バッファ領域６が互いに同一の厚さＴｄを有し且つ同一の構成を有するが、本発明の目的を達成できる範囲で厚さ及び構成を互いに相違させることもできる。また、図２においては、各単層構造バッファ領域７が互いに同一の厚さＴｅを有し且つ同一の構成を有するが、本発明の目的を達成できる範囲で厚さ及び構成を互いに相違させることもできる。 In FIG. 2, each sub-multilayer structure buffer region 6 has the same thickness Td and the same configuration, but the thickness and the configuration can be different from each other as long as the object of the present invention can be achieved. . In FIG. 2, each single layer structure buffer region 7 has the same thickness Te and the same configuration, but the thickness and the configuration are different from each other within a range in which the object of the present invention can be achieved. You can also.

図２の１つのサブ多層構造バッファ領域６が図３に更に詳しく示されている。図３から明らかようにサブ多層構造バッファ領域６は、第１及び第２のサブレイヤーと呼ぶこともできる第１及び第２の層６１、６２の交互積層体から成る。なお、サブ多層構造バッファ領域６を超格子バッファとなるように形成することもできる。図３では１つのサブ多層構造バッファ領域６が第１の層６１と第２の層６２とのペアを４つ積層することによって形成されているが、このペア数を任意に変えることができる。サブ多層構造バッファ領域６の厚みＴｄは、好ましくは１０〜１０００ｎｍ、より好ましくは４０〜４００ｎｍである。 One sub-multilayer buffer region 6 of FIG. 2 is shown in more detail in FIG. As can be seen from FIG. 3, the sub-multilayer structure buffer region 6 is composed of an alternating stack of first and second layers 61 and 62, which can also be called first and second sublayers. The sub multilayer buffer region 6 can also be formed to be a superlattice buffer. In FIG. 3, one sub-multilayer structure buffer region 6 is formed by stacking four pairs of the first layer 61 and the second layer 62, but the number of pairs can be arbitrarily changed. The thickness Td of the sub multilayer structure buffer region 6 is preferably 10 to 1000 nm, more preferably 40 to 400 nm.

第１の層６１はアルミニウムを第１の割合で含む窒化物半導体から成り、例えば、化学式Ａｌ_ｘＩｎ_ｙＧａ_{１−ｘ−ｙ}Ｎで表される窒化物半導体材料から成る。ここで、前記ｘ及びｙは、０＜ｘ≦１、０≦ｙ＜１、ｘ＋ｙ≦１を満足する数値、で示される窒化物半導体材料から成る。 The first layer 61 is made of a nitride semiconductor containing aluminum at a first ratio, for example, a nitride semiconductor material represented by the chemical formula Al _x In _y Ga _1-xy N. Here, x and y are made of a nitride semiconductor material represented by numerical values satisfying 0 <x ≦ 1, 0 ≦ y <1, and x + y ≦ 1.

第１の層６１の厚さＴｆは１〜２０ｎｍであることが望ましい。第１の層６１の厚さＴｆが１ｎｍよりも薄い場合、及び２０ｎｍよりも厚い場合には、半導体ウエーハの反り及び主半導体領域４の結晶性の改善効果が低下する。本実施形態では第１の層６１がＡｌＮ（窒化アルミニウム）から成り、この厚さＴｆは５ｎｍに設定されている。 The thickness Tf of the first layer 61 is desirably 1 to 20 nm. When the thickness Tf of the first layer 61 is thinner than 1 nm and thicker than 20 nm, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered. In the present embodiment, the first layer 61 is made of AlN (aluminum nitride), and the thickness Tf is set to 5 nm.

図３では全部の第１の層６１が同一の材料（ＡｌＮ）で形成されているが、複数の第１の層６１を互いに異なる材料で形成することができる。また、図３では全部の第１の層６１が同一の厚みに形成されているが、複数の第１の層６１を互いに異なる厚みに形成することができる。 In FIG. 3, all the first layers 61 are formed of the same material (AlN), but the plurality of first layers 61 can be formed of different materials. In FIG. 3, all the first layers 61 are formed with the same thickness, but the plurality of first layers 61 can be formed with different thicknesses.

ＡｌＮから成る第１の層６１の結晶軸ａ及びｃの格子定数はシリコンから成る基板２の格子定数よりも小さい値（例えばａ軸で０．３１１ｎｍ、ｃ軸で０．４９８ｎｍ）である。また、第１の層６１の線膨張係数は基板２の線膨張係数よりも大きい値（例えば４．１５×１０^−６／Ｋ）である。なお、第１の層６１に必要に応じてｎ型又はｐ型の導電型決定不純物をドープすることができる。 The lattice constant of crystal axes a and c of the first layer 61 made of AlN is smaller than the lattice constant of the substrate 2 made of silicon (for example, 0.311 nm for the a axis and 0.498 nm for the c axis). Further, the linear expansion coefficient of the first layer 61 is larger than the linear expansion coefficient of the substrate 2 (for example, 4.15 × 10 ⁻⁶ / K). The first layer 61 can be doped with an n-type or p-type conductivity determining impurity as necessary.

第１の層６１の上に配置された第２の層６２は、アルミニウムの含有割合が第２の割合（ゼロを含む）の窒化物半導体からなり、例えば、化学式Ａｌ_ａＩｎ_ｂＧａ_{１−ａ−ｂ}Ｎで表される窒化物半導体材料から成る。ここで、前記ａ及びｂは、０≦ａ≦１、０≦ｂ＜１、ａ＋ｂ≦１、ａ＜ｘを満足させる数値、で示される窒化物半導体材料から成る。上記の化学式から明らかなように第２の層６２はＡｌ（アルミニウム）を含んでも良いし、含まなくとも良い。第２の層６２にＡｌ（アルミニウム）を含める場合には、第１の層６１のＡｌ（アルミニウム）の割合よりも小さい第２の割合とする。本発明においてＡｌの第２の割合はゼロを含むものとして定義されている。 The second layer 62 disposed on the first layer 61 is made of a nitride semiconductor having an aluminum content ratio of a second ratio (including zero). For example, the chemical formula Al _a In _b Ga _{1-a -B} It is made of a nitride semiconductor material represented by N. Here, a and b are made of a nitride semiconductor material represented by numerical values satisfying 0 ≦ a ≦ 1, 0 ≦ b <1, a + b ≦ 1, and a <x. As apparent from the above chemical formula, the second layer 62 may or may not contain Al (aluminum). In the case where Al (aluminum) is included in the second layer 62, the second ratio is set to be smaller than the ratio of Al (aluminum) in the first layer 61. In the present invention, the second proportion of Al is defined as including zero.

第２の層６２の厚みＴｇは、好ましくは１〜２０ｎｍであり、より好ましくは２〜１０ｎｍである。第２の層６２の厚みＴｇが１よりも薄い場合、及び２０ｎｍよりも厚い場合、半導体ウエーハの反り及び主半導体領域４の結晶性の改善効果が低下する。本実施例では第２の層６２がＧａＮ（窒化ガリウム）から成り、この厚さＴｇは３．０ｎｍに設定されている。第２の層６２の厚みＴｇは、好ましくは第１の層６１の厚みＴｆよりも薄く決定される。なお、第１及び第２の層６１、６２を超格子バッファを構成するように形成することができる。 The thickness Tg of the second layer 62 is preferably 1 to 20 nm, and more preferably 2 to 10 nm. When the thickness Tg of the second layer 62 is thinner than 1 and thicker than 20 nm, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered. In this embodiment, the second layer 62 is made of GaN (gallium nitride), and the thickness Tg is set to 3.0 nm. The thickness Tg of the second layer 62 is preferably determined to be thinner than the thickness Tf of the first layer 61. Note that the first and second layers 61 and 62 can be formed to constitute a superlattice buffer.

また、図３では全部の第２の層６２が同一の材料で形成されているが、本発明の効果を得ることができる範囲内で、複数の第２の層６２を互いに異なる材料で形成することができる。また、図３では全部の第２の層６２が同一の厚みに形成されているが、本発明の効果を得ることができる範囲内で、複数の第２の層６２を互いに異なる厚みに形成することができる。 In FIG. 3, all the second layers 62 are formed of the same material. However, the plurality of second layers 62 are formed of different materials within a range in which the effect of the present invention can be obtained. be able to. In FIG. 3, all the second layers 62 are formed to have the same thickness. However, the plurality of second layers 62 are formed to have different thicknesses within a range in which the effect of the present invention can be obtained. be able to.

第２の層６２は、Ａｌ（アルミニウム）を含まないか、又は第１の層６１の第１の割合よりも少ない第２の割合で含む。従って、ＧａＮからなる第２の層６２の結晶軸ａ及びｃの格子定数は、第１の層６１の格子定数よりも大きく且つ基板２の格子定数よりも小さい値（例えばａ軸で０．３１８ｎｍ、ｃ軸で０．５１８ｎｍ）である。また、第２の層６２の線膨張係数は基板２の線膨張係数よりも大きい値（例えば５．５９×１０^−６／Ｋ）である。第２の層６２に必要に応じてｎ型又はｐ型の導電型決定不純物をドープすることができる。 The second layer 62 does not include Al (aluminum) or includes a second ratio smaller than the first ratio of the first layer 61. Accordingly, the lattice constants of the crystal axes a and c of the second layer 62 made of GaN are larger than the lattice constant of the first layer 61 and smaller than the lattice constant of the substrate 2 (for example, 0.318 nm on the a axis). , C axis is 0.518 nm). Further, the linear expansion coefficient of the second layer 62 is larger than the linear expansion coefficient of the substrate 2 (for example, 5.59 × 10 ⁻⁶ / K). The second layer 62 can be doped with n-type or p-type conductivity determining impurities as required.

単層構造バッファ領域７は、アルミニウムの含有割合が第３の割合（ゼロを含む）の窒化物半導体からなり、例えば、化学式Ａｌ_ｃＩｎ_ｄＧａ_{１−ｃ−ｄ}Ｎで表される窒化物半導体材料から成る。ここで、前記ｃ及びｄは、０≦ｃ≦１、０≦ｄ＜１、ｃ＋ｄ≦１、ｃ＜ｘを満足させる数値、で示される窒化物半導体材料からなる。 The single-layer structure buffer region 7 is made of a nitride semiconductor having a third aluminum content ratio (including zero), for example, a nitride semiconductor represented by the chemical formula Al _c In _d Ga _1-cd N Made of material. Here, c and d are made of a nitride semiconductor material represented by numerical values satisfying 0 ≦ c ≦ 1, 0 ≦ d <1, c + d ≦ 1, and c <x.

上記化学式から明らかなように、この単層構造バッファ領域７は、アルミニウムを含んでも良いし、含まなくとも良い。単層構造バッファ領域７がアルミニウムを含む場合には、サブ多層構造バッファ領域６の平均的（又は巨視的）に見たＡｌの含有割合よりも小さい第３の割合とする。なお、本発明においてＡｌの第３の割合はゼロを含むものとして定義されている。 As is clear from the above chemical formula, the single layer structure buffer region 7 may or may not contain aluminum. In the case where the single layer structure buffer region 7 contains aluminum, the third ratio is set to be smaller than the Al content rate seen from the average (or macroscopic) of the sub multilayer structure buffer region 6. In the present invention, the third proportion of Al is defined as including zero.

単層構造バッファ領域７のアルミニウムの含有割合がサブ多層構造バッファ領域６の平均値よりも小さいので、単層構造バッファ領域７の結晶軸ａ及びｃの格子定数は、第１の層６１の格子定数及びサブ多層構造バッファ領域６の平均的（又は巨視的）に見た格子定数よりも大きく且つ基板２の格子定数よりも小さい。 Since the aluminum content of the single layer structure buffer region 7 is smaller than the average value of the sub multilayer structure buffer region 6, the lattice constants of the crystal axes a and c of the single layer structure buffer region 7 are the lattices of the first layer 61. The constant and the sub-multilayer structure buffer region 6 are larger than the average (or macroscopic) lattice constant of the buffer region 6 and smaller than the lattice constant of the substrate 2.

製造工程を簡略化するために単層構造バッファ領域７を第２の層６２と同一の半導体材料（例えばＧａＮ）で形成することが望ましい。
単層構造バッファ領域７が第２の層６２と同一の半導体材料である場合には、単層構造バッファ領域７がサブ多層構造バッファ領域６の最も上の第２の層６２に連続的に形成される。このため、サブ多層構造バッファ領域６の最も上の第２の層６２と単層構造バッファ領域７との境界は実質的に存在しない。従って、サブ多層構造バッファ領域６の最も上の第２の層６２を単層構造バッファ領域７に含めて示すこともできる。このようにサブ多層構造バッファ領域６の最も上の第２の層６２を単層構造バッファ領域７に含めて示す場合には、サブ多層構造バッファ領域６に含まれる第１の層６１の合計は第２の層６２の合計よりも１つ多くなる。 In order to simplify the manufacturing process, the single layer structure buffer region 7 is desirably formed of the same semiconductor material (for example, GaN) as the second layer 62.
When the single layer structure buffer region 7 is made of the same semiconductor material as that of the second layer 62, the single layer structure buffer region 7 is continuously formed in the second layer 62 on the uppermost side of the sub multilayer structure buffer region 6. Is done. For this reason, there is substantially no boundary between the uppermost second layer 62 and the single layer structure buffer region 7 in the sub multilayer structure buffer region 6. Therefore, the uppermost second layer 62 of the sub multilayer structure buffer region 6 can be included in the single layer structure buffer region 7. Thus, when the uppermost second layer 62 of the sub multi-layer structure buffer region 6 is included in the single layer structure buffer region 7, the total of the first layers 61 included in the sub multi-layer structure buffer region 6 is One more than the total of the second layers 62.

単層構造バッファ領域７の厚みＴｅは、サブ多層構造バッファ領域６の厚みＴｄよりも厚い好ましくは２０〜２０００ｎｍ、より好ましくは１００〜５００ｎｍに決定される。単層構造バッファ領域７の厚さ２０ｎｍよりも薄い場合、及び２０００ｎｍよりも厚い場合には、半導体ウエーハの反り及び主半導体領域４の結晶性の改善効果が低下する。本実施例では単層構造バッファ領域７がＧａＮから成り、この厚さＴｅは２００ｎｍに設定されている。 The thickness Te of the single layer structure buffer region 7 is determined to be preferably 20 to 2000 nm, more preferably 100 to 500 nm, which is thicker than the thickness Td of the sub multilayer structure buffer region 6. When the thickness of the single layer structure buffer region 7 is thinner than 20 nm and thicker than 2000 nm, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered. In this embodiment, the single layer structure buffer region 7 is made of GaN, and the thickness Te is set to 200 nm.

なお、図２では全部の単層構造バッファ領域７が同一の材料で形成されているが、本発明の効果を得ることができる範囲内で、複数の単層構造バッファ領域７を互いに異なる材料で形成することができる。また、図２では全部の単層構造バッファ領域７が同一の厚みに形成されているが、本発明の効果を得ることができる範囲内で、複数の単層構造バッファ領域７を互いに異なる厚みに形成することができる。 In FIG. 2, all the single-layer structure buffer regions 7 are formed of the same material. However, a plurality of single-layer structure buffer regions 7 are formed of different materials within a range in which the effects of the present invention can be obtained. Can be formed. In FIG. 2, all the single-layer structure buffer regions 7 are formed with the same thickness. However, within the range where the effects of the present invention can be obtained, the plurality of single-layer structure buffer regions 7 have different thicknesses. Can be formed.

第２の多層構造バッファ領域８は、本発明に従って主半導体領域４の平坦性を向上させるためのものであり、図３に示すように第３及び第４のサブレイヤーと呼ぶこともできる第３及び第４の層８１、８２の交互積層体から成る。この第２の多層構造バッファ領域８は、平均的又は巨視的に見たアルミニウムの含有率がサブ多層構造バッファ領域６よりも大きく、且つ平均的又は巨視的に見た格子定数がサブ多層構造バッファ領域６と主半導体領域４よりも小さくなるように形成されている。 The second multilayer structure buffer region 8 is for improving the flatness of the main semiconductor region 4 according to the present invention, and can be called a third and fourth sublayer as shown in FIG. And the fourth and second layers 81 and 82 are alternately laminated. The second multilayer structure buffer region 8 has an average or macroscopic aluminum content rate larger than that of the sub multilayer structure buffer region 6 and an average or macroscopic lattice constant of the sub multilayer structure buffer. It is formed to be smaller than region 6 and main semiconductor region 4.

ここで、第２の多層構造バッファ領域８の平均的又は巨視的に見たアルミニウムの含有率とは、第２の多層構造バッファ領域８のＧａ，Ｉｎ及びＡｌの原子数に対する第２の多層構造バッファ領域８に含まれるＡｌの原子数の割合である。また、サブ多層構造バッファ領域６の平均的又は巨視的に見たアルミニウムの含有率とは、サブ多層構造バッファ領域６のＧａ，Ｉｎ及びＡｌの原子数に対する第１の多層構造バッファ領域５に含まれるＡｌの原子数の割合である。 Here, the average or macroscopic aluminum content of the second multilayer structure buffer region 8 is the second multilayer structure with respect to the number of atoms of Ga, In, and Al in the second multilayer structure buffer region 8. This is the ratio of the number of Al atoms contained in the buffer region 8. The average or macroscopic aluminum content of the sub multilayer buffer region 6 includes the first multilayer buffer region 5 with respect to the number of Ga, In and Al atoms in the sub multilayer buffer region 6. The ratio of the number of Al atoms.

また、第２の多層構造バッファ領域８の平均的又は巨視的に見た格子定数とは、第２の多層構造バッファ領域８の第３及び第４の層８１，８２の各格子定数（Ｃ３，Ｃ４）に各層の厚み（Ｔｈ，Ｔｉ）を乗算した値（Ｃ３×Ｔｈ、Ｃ４×Ｔｉ）をそれぞれ求め、この乗算で得られた各値の合計値｛ｍ（Ｃ３×Ｔｈ）＋ｎ（Ｃ４×Ｔｉ）｝を求め、この合計値を第２の多層構造バッファ領域８の全体の厚み（Ｔｂ）で除算した値に相当する。なお、ｍは第３の層８１の数、ｎは第４の層８２の数を示す。 The average or macroscopic lattice constant of the second multilayer structure buffer region 8 refers to the lattice constants (C3, C3) of the third and fourth layers 81 and 82 of the second multilayer structure buffer region 8. C4) is multiplied by the thickness (Th, Ti) of each layer (C3 × Th, C4 × Ti), and the total value {m (C3 × Th) + n (C4 × Ti)}, which corresponds to a value obtained by dividing the total value by the total thickness (Tb) of the second multilayer structure buffer region 8. Note that m represents the number of third layers 81, and n represents the number of fourth layers 82.

また、サブ多層構造バッファ領域６の平均的又は巨視的に見た格子定数とは、サブ多層構造バッファ領域６の第１及び第２の層６１、６２の各格子定数（Ｃ１，Ｃ２）に各層の厚み（Ｔｆ，Ｔg）を乗算した値（Ｃ１×Ｔｆ、Ｃ２×Ｔｇ）をそれぞれ求め、この乗算で得られた各値の合計値｛Ａ（Ｃ１×Ｔｆ）＋Ｂ（Ｃ２×Ｔg）｝を求め、この合計値をサブ多層構造バッファ領域６の全体の厚み（Ｔｄ）で除算した値に相当する。なお、Ａは第１の層６１の数、Ｂは第２の層６２の数を示す。また、主半導体領域４の平均的又は巨視的に見たアルミニウムの含有率、及び平均的又は巨視的に見た格子定数も、サブ多層構造バッファ領域６及び第２の多層構造バッファ領域５、８におけるこれらと同様に定義されている。 The average or macroscopic lattice constant of the sub-multilayer structure buffer region 6 refers to the lattice constants (C1, C2) of the first and second layers 61 and 62 of the sub-multilayer structure buffer region 6. The values (C1 × Tf, C2 × Tg) obtained by multiplying the thicknesses (Tf, Tg) are obtained, and the total value {A (C1 × Tf) + B (C2 × Tg)} obtained by this multiplication is obtained. This total value corresponds to a value obtained by dividing the total value by the total thickness (Td) of the sub multilayer structure buffer region 6. A represents the number of first layers 61 and B represents the number of second layers 62. Further, the average or macroscopic aluminum content of the main semiconductor region 4 and the average or macroscopic lattice constant are also shown in the sub-multilayer buffer region 6 and the second multilayer buffer regions 5 and 8. As well as these in

図３には第２の多層構造バッファ領域８が第３の層８１と第２の層８２とのペアを７つ積層することによって形成されている。なお、第３及び第４の層８１、８２のペア数を任意に変えることが可能である。しかし、第３及び第４の層８１、８２のペア数を３〜１００にすることが望ましい。このペア数が３より少ない場合、及び１００よりも多い場合には、半導体ウエーハの反り及び主半導体領域４の結晶性の改善効果が低下する。第２の多層構造バッファ領域８の厚みＴｂの好ましい値は５〜１０００ｎｍ、より好ましい値は２０〜４００ｎｍである。なお、この第２の多層構造バッファ領域８を超格子バッファとして機能する様に構成することもできる。 In FIG. 3, the second multilayer buffer region 8 is formed by laminating seven pairs of the third layer 81 and the second layer 82. Note that the number of pairs of the third and fourth layers 81 and 82 can be arbitrarily changed. However, it is desirable that the number of pairs of the third and fourth layers 81 and 82 is 3 to 100. When the number of pairs is less than 3 or more than 100, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered. A preferable value of the thickness Tb of the second multilayer structure buffer region 8 is 5 to 1000 nm, and a more preferable value is 20 to 400 nm. The second multilayer buffer region 8 can be configured to function as a superlattice buffer.

第３の層８１はアルミニウムを第４の割合で含む窒化物半導体から成り、例えば、化学式Ａｌx'Ｉｎy'Ｇａ1-x'-y'Ｎで表される窒化物半導体材料から成る。ここで、前記ｘ’及びｙ’は、０＜ｘ’≦１、０≦ｙ’＜１、ｘ’＋ｙ’≦１、ｘ’≦ｘを満足する数値、で示される窒化物半導体材料から成る。 The third layer 81 is made of a nitride semiconductor containing aluminum in a fourth ratio. For example, the third layer 81 is made of a nitride semiconductor material represented by the chemical formula Alx'Iny'Ga1-x'-y'N. Here, x ′ and y ′ are made of a nitride semiconductor material represented by the following values: 0 <x ′ ≦ 1, 0 ≦ y ′ <1, x ′ + y ′ ≦ 1, and x ′ ≦ x. .

上記化学式から明らかなように、前記ｘ’に相当する第３の層８１におけるアルミニウムの含有割合（第４の割合）を、第１の層６１におけるアルミニウムの含有割合（前記ｘに相当する第１の割合）と同一にすることができる。しかし、既に説明したように平均的又は巨視的に見たアルミニウムの含有率がサブ多層構造バッファ領域６よりも大きく、且つ平均的又は巨視的に見た格子定数がサブ多層構造バッファ領域６よりも小さくなるように第２の多層構造バッファ領域８を形成することが要求される。 As is clear from the above chemical formula, the aluminum content ratio (fourth ratio) in the third layer 81 corresponding to x ′ is set to the aluminum content ratio (first ratio corresponding to x in the first layer 61). Ratio). However, as described above, the average or macroscopic aluminum content rate is larger than that of the sub-multilayer buffer region 6, and the average or macroscopic lattice constant is larger than that of the sub-multilayer buffer region 6. It is required to form the second multilayer structure buffer region 8 to be small.

第３の層８１におけるアルミニウムの含有割合（第４の割合）が、第１の層６１におけるアルミニウムの含有割合（前記ｘに相当する第１の割合）と同一であっても、第２の多層構造バッファ領域８の厚みＴｂに対する第３の層８１の厚みＴｈの合計の割合（ｍ×Ｔｈ／Ｔｂ）がサブ多層構造バッファ領域６の厚みＴdに対する第１の層６１の厚みＴfの合計の割合（ａ×Ｔf／Ｔｂ）よりも大きい場合には、第２の多層構造バッファ領域８の平均的に見たアルミニウムの含有割合はサブ多層構造バッファ領域６の平均的に見たアルミニウムの含有割合よりも大きくなる。 Even if the aluminum content ratio (fourth ratio) in the third layer 81 is the same as the aluminum content ratio (first ratio corresponding to x) in the first layer 61, the second multilayer The ratio (m × Th / Tb) of the total thickness Th of the third layer 81 to the thickness Tb of the structure buffer region 8 is the ratio of the total thickness Tf of the first layer 61 to the thickness Td of the sub-multilayer structure buffer region 6 When the ratio is larger than (a × Tf / Tb), the average aluminum content in the second multilayer buffer region 8 is higher than the average aluminum content in the sub-multilayer buffer region 6. Also grows.

第３の層８１の厚さＴｈは単層構造バッファ領域７よりも薄い例えば１〜２０ｎｍであることが望ましい。この実施例では、厚さ５ｎｍのＡｌＮで第３の層８１が形成されている。図３では全部の第３の層８１が同一の材料で形成されているが、本発明の効果を得ることができる範囲内で、複数の第３の層８１を互いに異なる材料で形成することができる。また、第３の層８１に必要に応じてｎ型又はｐ型の導電型決定不純物をドープすることができる。 The thickness Th of the third layer 81 is preferably thinner than the single layer structure buffer region 7, for example, 1 to 20 nm. In this embodiment, the third layer 81 is formed of AlN having a thickness of 5 nm. In FIG. 3, all the third layers 81 are formed of the same material, but a plurality of third layers 81 can be formed of different materials within a range where the effects of the present invention can be obtained. it can. The third layer 81 can be doped with an n-type or p-type conductivity determining impurity as necessary.

第３の層８１の上に配置された第４の層８２は、アルミニウムの含有割合が第５の割合（ゼロを含む）の窒化物半導体からなり、例えば、化学式Ａｌa'Ｉｎb'Ｇａ1-a'-b'Ｎで表される窒化物半導体材料から成る。ここで、前記ａ’及びｂ’は、０≦ａ’≦１、０≦ｂ’＜１、ａ’＋ｂ’≦１、ａ’＜ｘ’を満足させる数値、で示される窒化物半導体材料から成る。 The fourth layer 82 disposed on the third layer 81 is made of a nitride semiconductor having an aluminum content ratio of a fifth ratio (including zero). For example, the chemical formula Ala'Inb'Ga1-a ' It is made of a nitride semiconductor material represented by -b'N. Here, a ′ and b ′ are from a nitride semiconductor material represented by the following values: 0 ≦ a ′ ≦ 1, 0 ≦ b ′ <1, a ′ + b ′ ≦ 1, and a ′ <x ′. Become.

上記の化学式から明らかなように第４の層８２はＡｌ（アルミニウム）を含んでも良いし、含まなくとも良い。第４の層８２にＡｌ（アルミニウム）を含める場合には、第３の層８１のＡｌ（アルミニウム）の割合よりも大きい第５の割合とする。本発明においてＡｌの第５の割合はゼロを含むものとして定義されている。なお、第４の層８２にＡｌ（アルミニウム）を含める場合には、第２の層６２のＡｌ（アルミニウム）の割合と同一又はこれよりも多いことが望ましい。 As apparent from the above chemical formula, the fourth layer 82 may or may not contain Al (aluminum). When Al (aluminum) is included in the fourth layer 82, the fifth ratio is set to be a fifth ratio that is larger than the ratio of Al (aluminum) in the third layer 81. In the present invention, the fifth proportion of Al is defined as including zero. In addition, when Al (aluminum) is included in the fourth layer 82, it is desirable that the ratio of Al (aluminum) in the second layer 62 is equal to or greater than that.

第４の層８２は、Ａｌ（アルミニウム）を含まないか、又は第３の層８１の第４の割合よりも少ない第５の割合で含む。従って、第４の層８２の結晶軸ａ及びｃの格子定数は、第３の層８１の格子定数よりも大きく且つ基板２の格子定数よりも小さい。第４の層８２がＧａＮの場合には、この格子定数はａ軸で０．３１８ｎｍ、ｃ軸で０．５１８ｎｍである。第２の多層構造バッファ領域８の平均的又は巨視的に見た格子定数は、サブ多層構造バッファ領域６よりも小さい。 The fourth layer 82 does not include Al (aluminum) or includes a fifth ratio smaller than the fourth ratio of the third layer 81. Accordingly, the lattice constant of the crystal axes a and c of the fourth layer 82 is larger than the lattice constant of the third layer 81 and smaller than the lattice constant of the substrate 2. When the fourth layer 82 is GaN, the lattice constant is 0.318 nm for the a-axis and 0.518 nm for the c-axis. The average or macroscopic lattice constant of the second multilayer structure buffer region 8 is smaller than that of the sub multilayer structure buffer region 6.

また、第４の層８２の線膨張係数は基板２の線膨張係数よりも大きい値（例えば５．５９×１０^−６／Ｋ）である。第２の多層構造バッファ領域８の第４の層８２の厚みＴｉは単層構造バッファ領域７よりも薄い１〜５０ｎｍであることが望ましい。 Further, the linear expansion coefficient of the fourth layer 82 is larger than the linear expansion coefficient of the substrate 2 (for example, 5.59 × 10 ⁻⁶ / K). The thickness Ti of the fourth layer 82 of the second multilayer structure buffer region 8 is preferably 1 to 50 nm, which is thinner than the single layer structure buffer region 7.

なお、第２の多層構造バッファ領域８の第３及び第４の層８１、８２を超格子バッファを構成するように形成することが望ましい。また、図３では全部の第４の層８２が同一の材料で形成されているが、本発明の効果を得ることができる範囲内で、複数の第４の層８２を互いに異なる材料で形成することができる。また、図３では全部の第４の層８２が同一の厚みに形成されているが、本発明の効果を得ることができる範囲内で、複数の第４の層８２を互いに異なる厚みに形成することができる。また、第４の層８２に必要に応じてｎ型又はｐ型の導電型決定不純物をドープすることができる。 The third and fourth layers 81 and 82 of the second multilayer buffer region 8 are preferably formed so as to constitute a superlattice buffer. In FIG. 3, all the fourth layers 82 are formed of the same material. However, the plurality of fourth layers 82 are formed of different materials within a range in which the effects of the present invention can be obtained. be able to. In FIG. 3, all the fourth layers 82 are formed to have the same thickness. However, the plurality of fourth layers 82 are formed to have different thicknesses within a range in which the effect of the present invention can be obtained. be able to. The fourth layer 82 can be doped with n-type or p-type conductivity-determining impurities as necessary.

図１の実施形態に従う主半導体領域４は、ＨＥＭＴを形成するために不純物非ドープのＧａＮから成る電子走行層４１と、不純物非ドープのＡｌ_０．２Ｇａ_０．８Ｎから成る電子供給層４２とを有している。なお、電子供給層４２にｎ型不純物をドープすることもできる。また、電子供給層４２のＡｌの割合を任意に変えることができる。バッファ領域３の上に配置された電子走行層４１はチャネル領域を含み、例えば、１８００ｎｍ（１．８μｍ）の厚みを有する。 The main semiconductor region 4 according to the embodiment of FIG. 1 includes an electron transit layer 41 made of undoped GaN and an electron supply layer 42 made of undoped Al _0.2 Ga _0.8 N to form a HEMT. And have. The electron supply layer 42 can be doped with n-type impurities. Further, the proportion of Al in the electron supply layer 42 can be arbitrarily changed. The electron transit layer 41 disposed on the buffer region 3 includes a channel region, and has a thickness of 1800 nm (1.8 μm), for example.

電子走行層４１の上に配置された電子供給層４２は電子走行層４１とのヘテロ接合に基づくピエゾ分極によって電子走行層４１と電子供給層４２との界面近傍に周知の２次元電子ガス層を形成させるものであって、例えば３０ｎｍの厚みを有する。 The electron supply layer 42 disposed on the electron transit layer 41 is formed with a well-known two-dimensional electron gas layer in the vicinity of the interface between the electron transit layer 41 and the electron supply layer 42 by piezoelectric polarization based on a heterojunction with the electron transit layer 41. For example, it has a thickness of 30 nm.

Ａｌを含む電子供給層４２はＡｌを含まない電子走行層４１に比べて極めて薄い。従って、主半導体領域４における平均的に見たＡｌの割合は電子走行層４１におけるＡｌの割合とほぼ同一になり、第１の多層構造バッファ領域５よりも小さい。主半導体領域４における平均的に見た格子定数は、電子走行層４１における格子定数とほぼ同一になり、多層構造バッファ領域５よりも大きく且つ基板２よりも小さい。 The electron supply layer 42 containing Al is extremely thinner than the electron transit layer 41 not containing Al. Accordingly, the average Al ratio in the main semiconductor region 4 is substantially the same as the Al ratio in the electron transit layer 41 and is smaller than that in the first multilayer buffer region 5. The average lattice constant in the main semiconductor region 4 is substantially the same as the lattice constant in the electron transit layer 41, which is larger than the multilayer buffer region 5 and smaller than the substrate 2.

主半導体領域４は、ＧａＮから成る電子走行層４１とＡｌＧａＮから成る電子供給層４２とに限定されるものでなく、種々の化合物半導体、好ましくは窒化物半導体で形成することができる。しかし、主半導体領域４における平均的に見たＡｌの割合は、第１及び第２の多層構造バッファ領域５、８よりも小さいことが望ましい。また、主半導体領域４における平均的に見た格子定数は、第１及び第２の多層構造バッファ領域５、８よりも大きいことが望ましい。図２の主半導体領域４のＧａＮから成る電子走行層４１はＡｌＧａＮから成る電子供給層４２よりも大幅に厚いので、主半導体領域４の平均的に見たＡｌの割合、及び平均的に見た格子定数は上記の要求を満たしている。 The main semiconductor region 4 is not limited to the electron transit layer 41 made of GaN and the electron supply layer 42 made of AlGaN, and can be formed of various compound semiconductors, preferably nitride semiconductors. However, it is desirable that the average Al ratio in the main semiconductor region 4 is smaller than that in the first and second multilayer structure buffer regions 5 and 8. The average lattice constant of the main semiconductor region 4 is desirably larger than that of the first and second multilayer structure buffer regions 5 and 8. The electron transit layer 41 made of GaN in the main semiconductor region 4 in FIG. 2 is significantly thicker than the electron supply layer 42 made of AlGaN. The lattice constant satisfies the above requirements.

図４は、図１〜図３に示した半導体ウエーハ１を使用して製作したＨＥＭＴを示す。説明を簡略化するために図４において図１と実質的に同一の部分に同一の符号を付し、その説明を省略する。第１の電極としてのソース電極９１及び第２の電極としてのドレイン電極９２は電子供給層４２にオーミック（低抵抗）接触し、制御電極としてのゲート電極９３は電子供給層４２にショットキー接触している。なお、ソース電極９１及びドレイン電極９２と電子供給層４２との間にｎ型不純物濃度の高いコンタクト層を設けることができる。ＨＥＭＴの動作の安定化を図るために基板２の下面に補助電極９４が設けられ、これが導体９５によってソース電極９１に接続されている。 FIG. 4 shows a HEMT manufactured using the semiconductor wafer 1 shown in FIGS. In order to simplify the description, the same reference numerals in FIG. 4 denote the same parts as in FIG. 1, and a description thereof will be omitted. The source electrode 91 as the first electrode and the drain electrode 92 as the second electrode are in ohmic (low resistance) contact with the electron supply layer 42, and the gate electrode 93 as the control electrode is in Schottky contact with the electron supply layer 42. ing. Note that a contact layer having a high n-type impurity concentration can be provided between the source electrode 91 and the drain electrode 92 and the electron supply layer 42. In order to stabilize the operation of the HEMT, an auxiliary electrode 94 is provided on the lower surface of the substrate 2, and this is connected to the source electrode 91 by a conductor 95.

次に、図１の半導体ウエーハ１の製造方法の一例を説明する。
まず、ミラー指数で示す結晶の面方位において（１１１）面とされた主面を有し、シリコン基板２を用意する。 Next, an example of a method for manufacturing the semiconductor wafer 1 of FIG. 1 will be described.
First, a silicon substrate 2 having a main surface which is a (111) plane in the crystal plane orientation indicated by the Miller index is prepared.

次に、基板２を周知のMOCVD（Ｍetal Organic Chemical Depositioｎ）即ち有機金属気相成長装置の反応室に投入し、基板２の表面の酸化膜を取り除いた後、反応室にＴＭＡ（トリメチルアルミニウム）、及びアンモニアを流して、シリコン基板２の上にＡｌＮ（窒化アルミニウム）から成るバッファ層１０をエピタキシャル成長させる。その後、ＴＭＡの供給を止め、アンモニアの供給は継続し、これと共にＴＭＧ（トリメチルガリウム）を流してＧａＮから成るバッファ層９をエピタキシャル成長させる。 Next, the substrate 2 is put into a reaction chamber of a well-known MOCVD (Metal Organic Chemical Deposition), that is, an organic metal vapor phase growth apparatus, and after removing the oxide film on the surface of the substrate 2, TMA (trimethylaluminum), Then, the buffer layer 10 made of AlN (aluminum nitride) is epitaxially grown on the silicon substrate 2 by flowing ammonia. Thereafter, the supply of TMA is stopped, and the supply of ammonia is continued. At the same time, TMG (trimethylgallium) is flowed to epitaxially grow the buffer layer 9 made of GaN.

次に、反応室にアンモニアとＴＭＡ（トリメチルアルミニウム）及びアンモニアとＴＭＧ（トリメチルガリウム）を交互に流してＡｌＮから成る第３の層８１とＧａＮから成る第４の層８２との交互積層体から成る第２の多層構造バッファ領域８を形成する。 Next, ammonia and TMA (trimethylaluminum) and ammonia and TMG (trimethylgallium) are alternately flowed into the reaction chamber, and the third layer 81 made of AlN and the fourth layer 82 made of GaN are alternately stacked. A second multilayer structure buffer region 8 is formed.

次に、第２の多層構造バッファ領域８の上にＧａＮからなる単層構造バッファ領域７をエピタキシャル成長させる。その後ＡｌＮ（窒化アルミニウム）から成る第１の層６１をエピタキシャル成長させる。その後、ＴＭＡの供給を止め、アンモニアの供給は継続し、これと共にＴＭＧ（トリメチルガリウム）を流してＧａＮから成る第２の層６２をエピタキシャル成長させる。第１及び第２の層６１，６２の形成工程を所望回数繰返して図３に示すサブ多層構造バッファ領域６を得る。 Next, the single layer structure buffer region 7 made of GaN is epitaxially grown on the second multilayer structure buffer region 8. Thereafter, a first layer 61 made of AlN (aluminum nitride) is epitaxially grown. Thereafter, the supply of TMA is stopped, and the supply of ammonia is continued. At the same time, TMG (trimethylgallium) is flowed to epitaxially grow the second layer 62 made of GaN. The formation process of the first and second layers 61 and 62 is repeated a desired number of times to obtain the sub multilayer structure buffer region 6 shown in FIG.

次に、反応室にアンモニアとＴＭＧ（トリメチルガリウム）を流してＧａＮから成る単層構造バッファ領域７をエピタキシャル成長させる。 Next, ammonia and TMG (trimethylgallium) are allowed to flow through the reaction chamber to epitaxially grow the single layer structure buffer region 7 made of GaN.

次に、単層構造バッファ領域７の上にサブ多層構造バッファ領域６及び単層構造バッファ領域７を所望回数繰り返して形成して第１の多層構造バッファ領域５を得る。 Next, the sub multilayer structure buffer area 6 and the single layer structure buffer area 7 are repeatedly formed a desired number of times on the single layer structure buffer area 7 to obtain the first multilayer structure buffer area 5.

この実施例では、第２の多層構造バッファ領域８の第３の層８１と第１の多層構造バッファ領域５のサブ多層構造バッファ領域第６に含まれる第１の層６１が共に５ｎｍのＡｌＮから成る。しかし、第２の多層構造バッファ領域８の第４の層８２がサブ多層構造バッファ領域第６に含まれる第２の層６２よりも薄く形成されている。これにより、この第２の多層構造バッファ領域８の平均的又は巨視的に見たアルミニウムの含有率はサブ多層構造バッファ領域６よりも小さい。 In this embodiment, the third layer 81 of the second multilayer structure buffer region 8 and the first layer 61 included in the sub multilayer structure buffer region 6 of the first multilayer structure buffer region 5 are both made of 5 nm AlN. Become. However, the fourth layer 82 of the second multilayer structure buffer region 8 is formed thinner than the second layer 62 included in the sub multilayer structure buffer region sixth. Thereby, the average or macroscopic aluminum content of the second multilayer structure buffer region 8 is smaller than that of the sub multilayer structure buffer region 6.

しかる後、周知のエピタキシャル成長法で主半導体領域４を第２の多層構造バッファ領域８の上に形成し、半導体ウエーハを完成させる。 Thereafter, the main semiconductor region 4 is formed on the second multilayer structure buffer region 8 by a known epitaxial growth method to complete the semiconductor wafer.

上記実施形態での第３の層８１をＡｌｘＧａ１−ｘＮで形成する場合は、Ｘは好ましくはＸ＞０．７，さらに好ましくはｘ＞０．８５、さらに好ましくはｘ＞０．９５であり、膜厚は、０．５〜１００ｎｍ、さらに好ましくは１〜２０ｎｍ、さらに好ましくは、１〜１０ｎｍである。また、第４の層８２はＡｌｘＧａ１−ｘＮであって、ｘ＜０．３、さらに好ましくはｘ＜０．１５、さらに好ましくはｘ＜０．０５であり、膜厚は、０．５〜１００ｎｍ、さらに好ましくは１〜２０ｎｍ、さらに好ましくは１〜１０ｎｍである。 In the case where the third layer 81 in the above embodiment is formed of AlxGa1-xN, X is preferably X> 0.7, more preferably x> 0.85, more preferably x> 0.95, The film thickness is 0.5 to 100 nm, more preferably 1 to 20 nm, and still more preferably 1 to 10 nm. The fourth layer 82 is AlxGa1-xN, and x <0.3, more preferably x <0.15, more preferably x <0.05, and the film thickness is 0.5 to 100 nm. More preferably, it is 1-20 nm, More preferably, it is 1-10 nm.

また、成膜条件は、平坦性が良好な成膜条件が好ましく、ＴＭＡ、ＴＭＧを用いたＭＯＣＶＤ成膜では、成膜温度は、１０００℃以上が好ましく、さらに好ましくは１０５０℃以上、さらに好ましくは１１００℃以上である。さらに、成膜時の圧力は加圧もしくは常圧、減圧に設定することが可能で、好ましくは減圧、さらに好ましくは５０ｋＰａ以下、さらに好ましくは、２０ｋＰａ以下である。 The film formation conditions are preferably film formation conditions with good flatness, and in MOCVD film formation using TMA and TMG, the film formation temperature is preferably 1000 ° C. or higher, more preferably 1050 ° C. or higher, more preferably 1100 ° C or higher. Furthermore, the pressure at the time of film formation can be set to pressurization, normal pressure, or reduced pressure, preferably reduced pressure, more preferably 50 kPa or less, and further preferably 20 kPa or less.

実際に、例えば、サブ多層構造バッファ領域６の第１の層は、膜厚５ｎｍのＡｌＮで形成する。また、第２の層は、膜厚３ｎｍのＧａＮで形成する。そして、第１の層と第２の層をそれぞれ１０層形成する。さらに、単層構造バッファ領域７は、膜厚２００ｎｍのＧａＮで形成する。そして、第２の多層構造バッファ領域８の第３の層８１は、膜厚５ｎｍのＡｌＮで形成する。また、第４の層８２は、膜厚２ｎｍのＧａＮで形成する。そして、第３の層と第４の層をそれぞれ１０層形成する。また、このときバッファ層９は、膜厚５０ｎｍのＧａＮで形成する。さらに、バッファ層１０は、膜厚１５０ｎｍのＡｌＮで形成する。また、上記の構造では、Ｓｉ基板上に成長したＡｌＮ上にＧａＮ５０ｎｍを介して第２の多層構造バッファ領域８を形成しているが、５０ｎｍの膜厚のＧａＮで形成されたバッファ層９が無くても良い。 Actually, for example, the first layer of the sub multilayer buffer region 6 is formed of AlN having a thickness of 5 nm. The second layer is formed of GaN having a thickness of 3 nm. Then, 10 layers each of the first layer and the second layer are formed. Further, the single layer structure buffer region 7 is formed of GaN having a thickness of 200 nm. Then, the third layer 81 of the second multilayer structure buffer region 8 is formed of AlN having a thickness of 5 nm. The fourth layer 82 is formed of GaN having a thickness of 2 nm. Then, ten third layers and four fourth layers are formed. At this time, the buffer layer 9 is formed of GaN having a thickness of 50 nm. Further, the buffer layer 10 is formed of AlN having a thickness of 150 nm. In the above structure, the second multilayer structure buffer region 8 is formed on the AlN grown on the Si substrate via GaN 50 nm, but there is no buffer layer 9 formed of GaN having a thickness of 50 nm. May be.

上記のようにして製造したシリコン基板上の窒化物半導体エピタキシャルにおいて、原子間力顕微鏡（ＡＦＭ）でエピタキシャル表面の平坦性を評価した結果、第２の多層構造バッファ領域８が無い場合、平均荒さ（Ｒａ）は、３ｎｍ、第２の多層構造バッファ領域８が有る場合、平均荒さ（Ｒａ）は２ｎｍとなった。 As a result of evaluating the flatness of the epitaxial surface with an atomic force microscope (AFM) in the nitride semiconductor epitaxial layer on the silicon substrate manufactured as described above, the average roughness ( Ra) was 3 nm, and when the second multilayer structure buffer region 8 was present, the average roughness (Ra) was 2 nm.

以上のように、本発明によれば、クラックがなく表面の平坦性が良好な半導体ウエーハ及び半導体装置及びその製造方法を提供することができる。 As described above, according to the present invention, it is possible to provide a semiconductor wafer, a semiconductor device, and a method for manufacturing the same, which are free from cracks and have good surface flatness.

次に、図５を参照して本発明の第２の実施形態に係る半導体ウエーハ１ｂを説明する。但し、図５において図１〜図４と実質的に同一の部分には同一の参照符号を付してその説明を省略する。 Next, a semiconductor wafer 1b according to the second embodiment of the present invention will be described with reference to FIG. 5 that are substantially the same as those in FIGS. 1 to 4 are denoted by the same reference numerals and description thereof is omitted.

第２の多層構造バッファ領域８は、本発明に従って主半導体領域４の平坦性を向上させるためのものであり、図５に示すように第３及び第４のサブレイヤーと呼ぶこともできる第３及び第４の層８１（８１０，．．．８１３）、８２の交互積層体から成る。第２の多層構造バッファ領域８に含まれる複数の第３の層（８１０，．．．８１３）は、基板２から第１の多層構造バッファ領域５に向かって徐々に薄くなるように互いに異なる厚み（Ｔ８１０，．．．Ｔ８１３）を有している。この第２の多層構造バッファ領域８は、平均的又は巨視的に見たアルミニウムの含有率がサブ多層構造バッファ領域６よりも大きく、且つ平均的又は巨視的に見た格子定数がサブ多層構造バッファ領域６と主半導体領域４よりも小さくなるように形成されている。 The second multilayer structure buffer region 8 is for improving the flatness of the main semiconductor region 4 according to the present invention, and can also be called third and fourth sublayers as shown in FIG. And fourth layers 81 (810,... 813), 82. The plurality of third layers (810,... 813) included in the second multilayer structure buffer region 8 have different thicknesses so as to gradually become thinner from the substrate 2 toward the first multilayer structure buffer region 5. (T810, ... T813). The second multilayer structure buffer region 8 has an average or macroscopic aluminum content rate larger than that of the sub multilayer structure buffer region 6 and an average or macroscopic lattice constant of the sub multilayer structure buffer. It is formed to be smaller than region 6 and main semiconductor region 4.

上記のようにして製造したシリコン基板上の窒化物半導体エピタキシャルにおいて、原子間力顕微鏡（ＡＦＭ）でエピタキシャル表面の平坦性を評価した結果、第２の実施形態のようにしてさらに第２の多層構造バッファ領域８を基板に近い側で格子定数が小さいように、基板に遠い側で格子定数が大きいようにすると、平均荒さ（Ｒａ）は、１．５ｎｍとなった。 As a result of evaluating the flatness of the epitaxial surface with an atomic force microscope (AFM) in the nitride semiconductor epitaxial on the silicon substrate manufactured as described above, the second multilayer structure is further obtained as in the second embodiment. When the buffer region 8 was made to have a small lattice constant on the side close to the substrate and the lattice constant was made large on the side far from the substrate, the average roughness (Ra) was 1.5 nm.

次に、図６を参照して本発明の第３の実施形態に係る半導体ウエーハ１ｃを説明する。但し、図６において図１〜図４と実質的に同一の部分には同一の参照符号を付してその説明を省略する。 Next, a semiconductor wafer 1c according to a third embodiment of the present invention will be described with reference to FIG. 6 that are substantially the same as those in FIGS. 1 to 4 are denoted by the same reference numerals and description thereof is omitted.

第２の多層構造バッファ領域８は、本発明に従って主半導体領域４の平坦性を向上させるためのものであり、図６に示すように第３及び第４のサブレイヤーと呼ぶこともできる第３及び第４の層８１、８２（８２０，．．．８２３）の交互積層体から成る。第２の多層構造バッファ領域８に含まれる複数の第４の層（８２０，．．．８２３）は、基板２から第１の多層構造バッファ領域５に向かって徐々に増加するように互いに異なる厚み（Ｔ８２０，．．．Ｔ８２３）を有している。この第２の多層構造バッファ領域８は、平均的又は巨視的に見たアルミニウムの含有率がサブ多層構造バッファ領域６よりも大きく、且つ平均的又は巨視的に見た格子定数がサブ多層構造バッファ領域６と主半導体領域４よりも小さくなるように形成されている。 The second multilayer structure buffer region 8 is for improving the flatness of the main semiconductor region 4 according to the present invention, and can also be referred to as a third and a fourth sublayer as shown in FIG. And fourth layers 81, 82 (820, ..., 823). The plurality of fourth layers (820,..., 823) included in the second multilayer structure buffer region 8 have different thicknesses so as to gradually increase from the substrate 2 toward the first multilayer structure buffer region 5. (T820, ... T823). The second multilayer structure buffer region 8 has an average or macroscopic aluminum content rate larger than that of the sub multilayer structure buffer region 6 and an average or macroscopic lattice constant of the sub multilayer structure buffer. It is formed to be smaller than region 6 and main semiconductor region 4.

上記のようにして製造したシリコン基板上の窒化物半導体エピタキシャルにおいて、原子間力顕微鏡（ＡＦＭ）でエピタキシャル表面の平坦性を評価した結果、第３の実施形態のようにしてさらに第２の多層構造バッファ領域８を基板に近い側で格子定数が小さいように、基板に遠い側で格子定数が大きいようにすると、平均荒さ（Ｒａ）は、１．５ｎｍとなった。 As a result of evaluating the planarity of the epitaxial surface with an atomic force microscope (AFM) in the nitride semiconductor epitaxial on the silicon substrate manufactured as described above, the second multilayer structure is further obtained as in the third embodiment. When the buffer region 8 was made to have a small lattice constant on the side close to the substrate and the lattice constant was made large on the side far from the substrate, the average roughness (Ra) was 1.5 nm.

本発明は上述の第１及び第２の実施形態に限定されるものでなく、例えば次変形が可能なものである。
（１）主半導体領域４をＨＥＭＴ以外のＭＥＳＦＥＴ，ＳＢＤ，ＬＥＤ等の別の半導体素子を構成するように形成することができる。
（２）シリコン基板２とバッファ領域３との間に例えばＡｌＮ等の別のバッファ層を設けることができる。
（３）主半導体領域４の中に例えばＡｌＮ層等の別の層を付加することができる。
（４）主半導体領域４、及びバッファ領域３を窒化物半導体以外の化合物半導体、例えば３−５族化合物半導体で構成することができる。 The present invention is not limited to the first and second embodiments described above, and for example, the following modifications are possible.
(1) The main semiconductor region 4 can be formed to constitute another semiconductor element such as MESFET, SBD, LED, etc. other than HEMT.
(2) Another buffer layer such as AlN can be provided between the silicon substrate 2 and the buffer region 3.
(3) Another layer such as an AlN layer can be added in the main semiconductor region 4.
(4) The main semiconductor region 4 and the buffer region 3 can be composed of a compound semiconductor other than a nitride semiconductor, for example, a group 3-5 compound semiconductor.

以上の実施形態で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、また数値および各構成の組成（材質）等については例示にすぎない。従って本発明は、説明された実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。また、実施例同士を組み合わせても良い。 The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective components Is just an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims. Moreover, you may combine Example.

本発明に係る半導体ウエーハ及び半導体装置及びその製造方法は、ＨＥＭＴやＭＥＳＦＥＴ，ＳＢＤ，ＬＥＤ等を作製するための半導体ウエーハ及び半導体装置及びその製造方法に利用される。 The semiconductor wafer, the semiconductor device, and the manufacturing method thereof according to the present invention are used for a semiconductor wafer, a semiconductor device, and a manufacturing method thereof for manufacturing HEMT, MESFET, SBD, LED, and the like.

１半導体ウエーハ
１ｂ、１ｃ半導体ウエーハ
２基板
３バッファ領域
４主半導体領域
５第１の多層構造バッファ領域
６サブ多層構造バッファ領域
７単層構造バッファ領域
８第２の多層構造バッファ領域
９バッファ層
１０バッファ層
４１電子走行層
４２電子供給層
６１第１の層
６２第２の層
８１第３の層
８２第４の層
９１ソース電極
９２ドレイン電極
９３ゲート電極
９４補助電極
８１０〜８１３第３の層
８２０〜８２３第４の層 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1b, 1c Semiconductor wafer 2 Substrate 3 Buffer area 4 Main semiconductor area 5 First multilayer structure buffer area 6 Sub multilayer structure buffer area 7 Single layer structure buffer area 8 Second multilayer structure buffer area 9 Buffer layer 10 Buffer Layer 41 Electron travel layer 42 Electron supply layer 61 First layer 62 Second layer 81 Third layer 82 Fourth layer 91 Source electrode 92 Drain electrode 93 Gate electrode 94 Auxiliary electrode 810-813 Third layer 820 823 Fourth Layer

Claims

A semiconductor wafer having a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and a main semiconductor region disposed on the buffer region and formed of a compound semiconductor. And
The buffer region includes a first multilayer structure buffer region and a second multilayer structure buffer region disposed between the substrate and the first multilayer structure buffer region,
The first multilayer structure buffer region is composed of an alternating layered structure in which 4 to 20 pairs of sub multilayer structure buffer regions and single layer structure buffer regions are alternately stacked,
The sub-multilayer structure buffer region includes a plurality of first and second layers arranged alternately,
The first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single-layer structure buffer region,
The second layer is made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed thinner than the single layer structure buffer region,
The single layer structure buffer region is made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed thicker than the first layer and the second layer. ,
The second multilayer buffer region includes a plurality of third and fourth layers arranged alternately;
The third layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single-layer structure buffer region.
The fourth layer is made of a compound semiconductor having a lattice constant between the lattice constant of the third layer and the lattice constant of the substrate, and is formed thinner than the single layer structure buffer region,
The first multilayer buffer region has an average lattice constant smaller than an average lattice constant of the main semiconductor region;
The second multilayer structure buffer region has an average lattice constant smaller than an average lattice constant of the main semiconductor region and the sub multilayer structure buffer region. Wafer.

2. The semiconductor wafer according to claim 1, wherein the second multilayer buffer region includes at least a third layer and a fourth layer, respectively.

The plurality of third layers included in the second multilayer structure buffer region have different thicknesses so as to gradually decrease from the substrate toward the first multilayer structure buffer region. A semiconductor wafer according to claim 1 or 2.

The plurality of fourth layers included in the second multilayer structure buffer region have different thicknesses so as to gradually increase from the substrate toward the first multilayer structure buffer region. The semiconductor wafer according to any one of claims 1 to 3.

A substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, a main semiconductor region disposed on the buffer region and formed of a compound semiconductor, and the main semiconductor region And at least first and second main electrodes disposed on the main semiconductor region, and a control electrode disposed on the main semiconductor region and having a function of controlling a current flow between the first and second main electrodes; A semiconductor element comprising an auxiliary electrode formed on the other main surface of the substrate and electrically connected to the first or second main electrode,
The buffer region comprises a first multilayer structure buffer region, and a second multilayer structure buffer region disposed between the substrate and the first multilayer structure buffer region,
The first multilayer structure buffer region is composed of an alternating layered structure in which 4 to 20 pairs of sub multilayer structure buffer regions and single layer structure buffer regions are alternately stacked,
The sub-multilayer structure buffer region includes a plurality of first and second layers arranged alternately,
The first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single-layer structure buffer region,
The second layer is made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed thinner than the single layer structure buffer region,
The single layer structure buffer region is made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate, and is formed thicker than the first layer and the second layer. ,
The second multilayer buffer region includes a plurality of third and fourth layers arranged alternately;
The third layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate and is formed thinner than the single-layer structure buffer region.
The fourth layer is made of a compound semiconductor having a lattice constant between the lattice constant of the third layer and the lattice constant of the substrate, and is formed thinner than the single layer structure buffer region,
The first multilayer buffer region has an average lattice constant smaller than an average lattice constant of the main semiconductor region;
The second multilayer structure buffer region has an average lattice constant smaller than an average lattice constant of the main semiconductor region and the sub multilayer structure buffer region. element.

In a method of manufacturing a semiconductor wafer having a buffer region made of a compound semiconductor on one main surface of a substrate, and a main semiconductor region disposed on the buffer region and formed of a compound semiconductor,
A third layer made of a compound semiconductor having a lattice constant smaller than the material constituting the substrate, and a lattice constant between the lattice constant of the third layer and the lattice constant of the substrate are formed on the substrate. A second multilayer structure buffer region including a stacked body of a fourth layer made of a compound semiconductor and having an average lattice constant smaller than an average lattice constant of the first multilayer buffer region A first step of forming
A first layer made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate, and a compound semiconductor having a lattice constant between the lattice constant of the first layer and the lattice constant of the substrate. A second step of forming a sub-multilayer structure buffer region composed of an alternating laminate with the second layer formed on one main surface of the substrate;
A single layer structure buffer region made of a compound semiconductor having a lattice constant between the lattice constant of the first layer and the substrate is thicker than the second layer on the sub multilayer structure buffer region. A third step of forming;
Another sub-multilayer structure buffer region having substantially the same configuration as that of the sub-multilayer structure buffer region and the same configuration as that of the single-layer structure buffer region in the same manner as the second and third steps. A fourth multilayer structure is obtained by repeatedly forming another single-layer structure buffer area having the first multi-layer structure buffer area in which 4 to 20 pairs of the sub-multilayer structure buffer area and the single-layer structure buffer area are alternately stacked . And the process of
Forming a main semiconductor region made of a compound semiconductor on the buffer region and having an average lattice constant larger than an average lattice constant of the first and second multilayer buffer regions; And the process of
A method for producing a semiconductor wafer, comprising: