JP2012109344A - Nitride semiconductor element and nitride semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor element capable of reducing leakage current during an off time of transistor operation and to provide a nitride semiconductor element package with reduced leakage current and excellent reliability.SOLUTION: A buffer layer 44 composed of an AlN layer 47, a first AlGaN layer 48 (the average Al composition is 50%), and a second AlGaN layer 49 (the average Al composition is 20%) is formed on a substrate 41. An element operation layer composed of a GaN electron transit layer 45 and an AlGaN electron supply layer 46 is formed on the buffer layer 44. These constitute an HEMT element 3. In the HEMT element 3, a BGaN portion 50 composed of a mixed crystal of BN and GaN is formed at the middle in the thickness direction of the GaN electron transit layer 45.

Description

  The present invention relates to a nitride semiconductor device using a group III nitride semiconductor and a semiconductor package of the device.

The group III nitride semiconductor is a semiconductor using nitrogen as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are typical examples. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).
Such a group III nitride semiconductor has physical properties suitable for high-temperature / high-power devices and high-frequency devices. In view of such physical properties, group III nitride semiconductors are used as semiconductors constituting devices such as HEMTs (High Electron Mobility Transistors).

  For example, an SiN substrate, an AlN layer, an AlGaN layer (Al composition is 0.3 or more and 0.6 or less), a GaN layer and an AlGaN electron supply layer, and an AlGaN electron supply layer, which are sequentially stacked on the Si substrate by epitaxial growth. There has been proposed a HEMT including a source electrode and a drain electrode provided on the top with a space therebetween, and a gate electrode provided between the source electrode and the drain electrode (see, for example, Patent Document 1).

  In this HEMT, a two-dimensional electron gas is generated in the vicinity of the interface of the GaN layer with the AlGaN electron supply layer, and the two-dimensional electron gas functions as a channel that conducts between the source electrode and the drain electrode, thereby operating the transistor. Is done.

JP 2008-166349 A

However, in the conventional HEMT, the vertical direction (each layer is penetrated in the thickness direction) from the source electrode to the drain electrode through the Si substrate, even when the transistor operation is turned off (when the two-dimensional electron gas is pinched off). Direction) and a leakage current may flow between the source and the drain.
Accordingly, an object of the present invention is to provide a nitride semiconductor device capable of reducing leakage current when the transistor operation is off.

  Another object of the present invention is to provide a nitride semiconductor device package with low leakage current and excellent reliability.

  In order to achieve the above object, the invention according to claim 1 is directed to a semiconductor substrate, a GaN electron transit layer formed on the semiconductor substrate, and a thickness direction intermediate portion of the GaN electron transit layer. A BGaN portion formed in a layer shape in a direction perpendicular to the direction, an AlGaN electron supply layer formed on the GaN electron transit layer, and a source electrode formed on the AlGaN electron supply layer with a space therebetween And a drain electrode, and a gate electrode formed between the source electrode and the drain electrode on the AlGaN electron supply layer.

  According to this structure, the BGaN part is formed in the middle part of the GaN electron transit layer. BGaN is a mixed crystal of BN (boron nitride) and GaN (gallium nitride). Since BN having high insulation is included as a mixed crystal with GaN in the middle part of the GaN electron transit layer, in the GaN electron transit layer, the thickness direction AlGaN electron supply layer side and the semiconductor substrate with respect to the BGaN portion The conductivity between the sides can be reduced. Thus, when the gap between the source electrode and the drain electrode is off, generation of a vertical current path from the source electrode to the semiconductor substrate can be prevented or even if generated, the current path The current flowing through can be reduced. As a result, leakage current when the transistor operation is off can be reduced.

  For example, as in the invention of Patent Document 1, a nitride semiconductor layer having higher insulating properties than GaN (AlGaN layer and AlN layer in Patent Document 1) is interposed between the GaN electron transit layer and the semiconductor substrate. In this case, the leakage current may be reduced by increasing the series resistance of the layer by increasing the thickness of the nitride semiconductor layer. However, if these nitride semiconductor layers are too thick, cracks may occur in the wafer, which is not suitable for practical use.

Accordingly, in the present invention, by providing a BGaN portion that can exist as a mixed crystal with GaN in the GaN electron transit layer, leakage current can be reduced, and at the same time, generation of cracks in the wafer can be prevented. .
The BGaN of the BGaN portion preferably has a wurtzite crystal structure as described in claim 2.

If the BGaN in the BGaN part is a wurtzite crystal structure, the crystal structure of the BGaN part and the GaN electron transit layer can be made the same type (wurtzite crystal structure), so that the propagation of edge dislocations is suppressed. Can do. Therefore, the edge dislocation density can be reduced. As a result, a high quality device can be obtained.
In order to obtain BGaN having a wurtzite crystal structure, specifically, as described in claim 3, BGaN of the BGaN portion is B _x Ga _1-x N (0.0 <x <0 .02).

As the crystal structure of BN, hexagonal crystals (hBN) and rhombohedral crystals (rBN) of normal pressure stable phase, cubic zinc blende type (cBN) and hexagonal wurtzite type (cBN) of high temperature and high pressure stable phase ( Four crystal structures of wBN) are known.
If BGaN has a composition represented by B _x Ga _1-x N (0.0 <x <0.02), BN having a hexagonal wurtzite type (wBN) single crystal structure is favorably obtained. Obtainable. As a result, a BGaN portion having a wurtzite crystal structure can be obtained favorably.

For example, if the crystal structure of BN is a cubic zinc blende type (cBN) single crystal structure, the crystal structure is inherited by GaN on the AlGaN electron supply layer side with respect to the BGaN portion, and GaN originally has This is not preferable because the wurtzite crystal structure cannot be maintained.
The B composition x of BGaN is preferably 0.0 <x <0.005 as described in claim 4. If the B composition x is in the above range, the flatness of the BGaN portion can be maintained, and the quality (film quality) of the GaN electron transit layer can be improved.

Further, the thickness of the BGaN portion is preferably 5 nm or less as described in claim 5. If the thickness of the BGaN portion is in the above range, the flatness of the BGaN portion can be maintained, and the quality (film quality) of the GaN electron transit layer can be improved.
In addition, as described in claim 6, the BGaN portion is preferably formed closer to the semiconductor substrate than the center position in the thickness direction of the GaN electron transit layer. Specifically, as described in claim 7, when the GaN electron transit layer has a thickness of 500 nm to 1500 nm, the BGaN portion has a height of 100 nm to 300 nm from the lower end of the GaN electron transit layer. It is preferable that it is formed in this position.

Further, it is preferable that a buffer layer is interposed between the GaN electron transit layer and the semiconductor substrate as described in claim 8.
Thereby, for example, as described in claim 9, even when the semiconductor substrate is a different substrate (Si substrate) different from the nitride semiconductor substrate, the crystalline state of the GaN electron transit layer can be favorably maintained. .

  When the semiconductor substrate is a Si substrate, the buffer layer includes an AlN layer formed on the semiconductor substrate and a plurality of AlGaN layers formed on the AlN layer, as recited in claim 10. In the AlGaN stacked structure, the Al composition of a certain reference AlGaN layer is preferably smaller than the Al composition of the AlGaN layer closer to the AlN layer than the reference AlGaN layer. . In other words, the plurality of AlGaN layers are arranged on the opposite side of the first AlGaN layer and the first AlGaN layer to the AlN layer (on the GaN electron transit layer side), and have an Al composition smaller than that of the first AlGaN layer. A second AlGaN layer is preferably included.

  For example, simply by providing an AlGaN layer single layer between an AlN layer and a GaN electron transit layer, the difference in lattice constant between AlGaN and GaN is large, so when a GaN electron transit layer having a large thickness is laminated, GaN lattice relaxation occurs. Therefore, it becomes difficult to give sufficient pressure resistance to the HEMT. As a result, the thickness of the GaN electron transit layer is limited, and the degree of freedom in device design is small.

  Therefore, according to the configuration of claim 10, the composition of the plurality of AlGaN layers is determined so that the Al composition becomes smaller as the layer is closer to the GaN electron transit layer. Thereby, the lattice constant of the AlGaN layer can be increased stepwise from a value close to the lattice constant of AlN to a value close to the lattice constant of GaN. Therefore, the difference in lattice constant between the GaN electron transit layer and the uppermost AlGaN layer in contact with the GaN electron transit layer can be reduced. As a result, the thickness of the GaN electron transit layer can be designed freely. Therefore, the device breakdown voltage can be improved by designing the GaN electron transit layer to be thick.

  By the way, when a GaN crystal is laminated on a Si substrate by epitaxial growth, for example, the difference in linear expansion coefficient between the Si substrate and the GaN layer (that is, the difference in shrinkage rate when the temperature is lowered) during or after cooling after epitaxial growth. ) May cause a large tensile stress in the GaN layer. As a result, cracks in the GaN layer and warpage of the Si substrate may occur.

  According to the invention of claim 10, the AlN layer is formed on the Si substrate, and the AlGaN laminated structure is provided between the AlN layer and the GaN electron transit layer. In the AlGaN stacked structure, the composition of the plurality of AlGaN layers is determined such that the closer the layer is to the GaN electron transit layer, the smaller the Al composition. Therefore, the compressive stress (strain) applied to the AlGaN layer due to the lattice constant difference between the AlN layer and the lowermost AlGaN layer can be propagated to the uppermost AlGaN layer. As a result, even if a tensile stress is generated in the GaN electron transit layer, the tensile stress can be relaxed by the compressive stress applied to the GaN electron transit layer from the AlN layer and the AlGaN buffer layer. Therefore, cracks in the GaN electron transit layer and warpage of the Si substrate can be reduced.

Further, in the AlGaN laminated structure, as described in claim 11, the Al composition (%) of the reference AlGaN layer and the AlGaN layer Al disposed in contact with the surface of the reference AlGaN layer on the AlN layer side. The difference from the composition (%) is preferably 10% or more.
Thereby, a lattice constant difference can be reliably generated between the reference AlGaN layer and the AlGaN layer in contact with the reference AlGaN layer.

  For example, if the difference between the Al composition (%) of the reference AlGaN layer and the Al composition (%) of the AlGaN layer disposed in contact with the AlN layer side surface of the reference AlGaN layer is about 1%, the reference AlGaN In some cases, the lattice constant of the layer is aligned with the lattice constant of the AlGaN layer in contact therewith. As a result, the difference in lattice constant between the uppermost AlGaN layer and the GaN electron transit layer increases, and complete lattice relaxation occurs. Therefore, compressive stress (strain) is transmitted from the buffer layer to the GaN electron transit layer. Becomes difficult.

  Therefore, with the configuration of the invention according to claim 11, the difference in lattice constant between the GaN electron transit layer and the uppermost AlGaN layer can be made smaller than in the case where the lattice constants are uniform. Therefore, compressive stress (strain) can be transmitted from the buffer layer to the GaN electron transit layer, and as a result, cracks in the GaN electron transit layer and warpage of the Si substrate can be reduced well.

For example, as described in claim 12, the AlGaN layered structure has a structure in which a first AlGaN layer having an Al composition of 50% and a second AlGaN layer having an Al composition of 20% are stacked in order from the AlN layer. Also good.
In the invention according to claim 13, the plane orientation of the main surface of the buffer layer is c-plane, and in the AlGaN laminated structure, the a-axis average lattice constant of the reference AlGaN layer is the AlN of the reference AlGaN layer. The a-axis in-plane lattice constant of the AlGaN layer arranged in contact with the layer-side surface is larger than the a-axis average lattice constant inherent in the reference AlGaN layer, according to any one of claims 10 to 12. The nitride semiconductor device described.

  According to this configuration, the a-axis average lattice constant of the reference AlGaN layer is larger than the a-axis in-plane lattice constant of the AlGaN layer in contact with the reference AlGaN layer, and the a-axis average lattice constant inherent to the reference AlGaN layer (none Smaller than (a-axis lattice constant in the strained state). As a result, an a-axis compressive stress is applied to the reference AlGaN layer that does not match the a-axis lattice constant of the AlGaN layer disposed in contact with the surface of the reference AlGaN layer on the AlN layer side. This a-axis compressive stress can be propagated to the uppermost AlGaN layer. Therefore, even if an a-axis tensile stress is generated in the GaN electron transit layer, the a-axis tensile stress can be relaxed by the a-axis compressive stress applied to the GaN electron transit layer from the AlN layer and the AlGaN buffer layer.

The in-plane lattice constant is the lattice constant at the interface with the reference AlGaN layer in the AlGaN layer in contact with the surface of the reference AlGaN layer on the AlN layer side.
Further, the main surface of the Si substrate may be a (111) surface as described in claim 14.
Further, the degree of distortion of the c-axis lattice constant of the GaN electron transit layer is preferably −0.07% or more as described in claim 15.

Thereby, generation | occurrence | production of the crack of a GaN electron transit layer can be prevented reliably.
The buffer layer may be a single layer of an AlN layer formed on the semiconductor substrate. In addition, as described in claim 17, it may have a superlattice structure in which a plurality of pairs of AlN layers and AlGaN layers are alternately stacked. Further, as described in claim 18, it may have a superlattice structure in which a plurality of pairs of AlGaN layers and GaN layers are alternately stacked.

The invention according to claim 19 is a nitride semiconductor comprising the nitride semiconductor element according to any one of claims 1 to 18 and a resin package formed so as to cover the nitride semiconductor element. It is a package.
According to this configuration, the nitride semiconductor element of the present invention is used, and the leakage current when the transistor operation is off can be reduced, so that a highly reliable package can be provided.

1 is a schematic overall view of a HEMT package according to an embodiment of the present invention. FIG. 2 is a perspective view showing the inside of the HEMT package shown in FIG. 1. FIG. 3 is an enlarged view of a portion surrounded by a broken line A in FIG. 2. It is a schematic cross section of the HEMT device concerning one embodiment of the present invention, and shows the section in the BB cut plane of Drawing 3. It is an image figure of the residual stress which arises in a nitride semiconductor layer. It is an illustration figure for demonstrating the structure of the processing apparatus for growing each layer which comprises a group III nitride semiconductor laminated structure. It is a figure for demonstrating the 1st modification of the buffer layer of FIG. It is a figure for demonstrating the 2nd modification of the buffer layer of FIG. It is a figure for demonstrating the 3rd modification of the buffer layer of FIG. It is a schematic cross section which shows the structure of the HEMT element of an Example. It is a graph for demonstrating the reduction effect of a leakage current and an edge dislocation density.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic overall view of a HEMT package according to an embodiment of the present invention. 2 is a perspective view showing the inside of the HEMT package shown in FIG. FIG. 3 is an enlarged view of a portion surrounded by a broken line A in FIG.

The HEMT package 1 as an example of the nitride semiconductor package of the present invention includes a terminal frame 2, a HEMT element 3 (chip), and a resin package 4.
The terminal frame 2 is formed in a metal plate shape. The terminal frame 2 has a quadrangular shape in plan view, and is separated from the base portion 5 that supports the HEMT package 1, the source terminal 6 that is integrally formed with the base portion 5, and the base portion 5. The drain terminal 7 and the gate terminal 8 are formed.

  The source terminal 6, the drain terminal 7 and the gate terminal 8 are each formed in a straight line shape in plan view having one end and the other end, and the source terminal 6, the drain terminal 7 and the gate terminal 8 are arranged in parallel with each other in this order. Of these terminals 6 to 8, only one end of the source terminal 6 integrated with the base portion 5 is connected to a corner portion of the base portion 5. Among the remaining terminals 7 to 8, the gate terminal 8 is arranged so that one end thereof faces the other corner of the base portion 5 adjacent to the corner to which the source terminal 6 is connected. 7 is arranged between the gate terminal 8 and the source terminal 6.

The HEMT element 3 is an example of the nitride semiconductor element of the present invention, and includes a drain pad 9, a source pad 10, and a gate pad 11. The drain pad 9, the source pad 10 and the gate pad 11 are formed in a metal plate shape and are spaced apart from each other.
The drain pad 9 integrally includes a bonding part 12D, an arm part 13D, and an electrode part 14D.

The bonding portion 12 </ b> D of the drain pad 9 has one end and the other end, and is formed in a straight line shape in plan view extending in a direction crossing the terminals 6 to 8 of the terminal frame 2. The bonding portion 12D is electrically connected to the drain terminal 7 using bonding wires 15D (three wires in FIG. 2).
A pair of arm portions 13D of the drain pad 9 are formed in a straight line shape in plan view extending in parallel to each other and extending in a direction away from the terminals 6 to 8 from one end and the other end of the bonding portion 12D. The drain pad 9 defines an element region 16 surrounded by a concave shape (U-shape) in plan view in which the free end (other end) side of the arm portion 13D is opened by the bonding portion 12D and the pair of arm portions 13D.

  The electrode part 14D of the drain pad 9 is provided in the element region 16, and is formed in a large number of stripes extending from each arm part 13D toward the other arm part 13D. A gap 17 having a predetermined width is provided between the tip of the electrode part 14D connected to one arm part 13D and the tip of the electrode part 14D connected to the other arm part 13D. The electrode portion 14D of the drain pad 9 is an example of the drain electrode of the present invention.

The source pad 10 integrally includes a bonding portion 18S, an arm portion 19S, and an electrode portion 20S.
The bonding portion 18S of the source pad 10 is formed in a straight line shape in plan view extending in parallel with the bonding portion 12D of the drain pad 9 at the open end of the element region 16. The bonding portion 18S is electrically connected to the base portion 5 using bonding wires 21S (two wires in FIG. 2). As a result, the bonding portion 18 </ b> S of the source pad 10 is electrically connected to the source terminal 6 integrated with the base portion 5.

One arm portion 19S of the source pad 10 is formed so that the gap 17 between the electrode portions 14D of the drain pad 9 extends in a direction crossing the electrode portion 14D of the drain pad 9.
A large number of electrode portions 20S of the source pad 10 are formed in stripes extending in both directions from the arm portion 19S toward the arm portions 13D of the drain pad 9. The electrode portion 20S is an example of the source electrode of the present invention, and one electrode portion 20S is provided between each electrode portion 14D of the drain pad 9.

The gate pad 11 integrally includes a bonding part 22G, a first arm part 23G, a second arm part 24G, and an electrode part 25G.
The bonding portion 22G of the gate pad 11 is formed in a square shape in plan view, and is disposed in the vicinity of the free end portion of one arm portion 13D of the drain pad 9. The bonding portion 22G is electrically connected to the gate terminal 8 using a bonding wire 26G (one wire in FIG. 2).

The first arm portion 23G of the gate pad 11 extends from the corner portion of the bonding portion 22G to the free end portion of the other arm portion 13D of the drain pad 9 on the side close to the element region 16 with respect to the bonding portion 18S of the source pad 10. The drain pad 9 is formed in a straight line shape in plan view extending parallel to the bonding portion 12D of the drain pad 9.
The second arm portion 24G of the gate pad 11 extends from the first arm portion 23G through the gap 17 between the electrode portion 14D of the drain pad 9 in a direction crossing the electrode portion 14D of the drain pad 9. One is formed on each side of 19S.

  A large number of electrode portions 25G of the gate pad 11 are formed in stripes extending in both directions from the second arm portions 24G toward the arm portions 13D of the drain pad 9. The electrode portion 25G is an example of the gate electrode of the present invention, and one electrode portion 25G is provided between each of the electrode portion 14D of the drain pad 9 and the electrode portion 20S of the source pad 10. Further, the interval GD between the electrode portion 25G and the electrode portion 14D is wider than the interval GS between the electrode portion 25G and the electrode portion 20S. That is, the electrode part 25G is arranged on the side closer to the electrode part 20S with respect to the intermediate position between the electrode part 14D and the electrode part 20S. Thus, when a positive voltage is applied to the drain-side electrode portion 14D and a voltage of 0 (zero) V or less is applied to the gate-side electrode portion 25G, a sufficient voltage drop is achieved between the drain and the gate. be able to. As a result, electric field concentration on the electrode portion 25G can be prevented.

  The resin package 4 has the outer shape of the HEMT package 1 and is formed in a substantially rectangular parallelepiped shape. The resin package 4 is made of, for example, a known mold resin such as an epoxy resin, and covers the base portion 5 of the terminal frame 2 and the bonding wires 15D, 21S, and 26G together with the HEMT element 3, and includes three terminals (source terminal 6, drain terminal). 7 and the gate terminal 8) are exposed so that the HEMT element 3 is sealed.

FIG. 4 is a schematic cross-sectional view of a HEMT device according to an embodiment of the present invention, showing a cross section taken along the line BB of FIG.
Next, the internal structure of the HEMT element will be described in detail with reference to FIG.
The HEMT element 3 includes a substrate 41 as a semiconductor substrate and a group III nitride semiconductor multilayer structure 42 formed on the substrate 41 by epitaxial growth (crystal growth).

In this embodiment, the substrate 41 is composed of an Si single crystal substrate (linear expansion coefficient α1 is, for example, 2.5 × 10 ^{−6 to} 3.5 × 10 ⁻⁶ (293K)). The substrate 41 is a just (111) plane Si substrate having an off angle of 0 ° with the (111) plane as the main surface 43.
The a-axis average lattice constant LC1 of the substrate 41 (interstitial distance between Si atoms bonded to atoms constituting the nitride semiconductor in the direction along the main surface 43 of the substrate 41) is, for example, 0.768 nm to 0.769 nm. . A group III nitride semiconductor multilayer structure 42 is formed by crystal growth on the main surface 43. The group III nitride semiconductor multilayer structure 42 is made of a group III nitride semiconductor having, for example, a c-plane ((0001) plane) as a crystal growth main surface.

  The lattice mismatch between each layer forming the group III nitride semiconductor multilayer structure 42 and the underlying layer is absorbed by lattice distortion of the layer in which the crystal is grown, and the continuity of the lattice at the interface with the underlying layer is maintained. It is. For example, when an InGaN layer and an AlGaN layer are grown from the c-plane ((0001) plane) of the GaN layer, the average lattice constant (a-axis average lattice constant) in the a-axis direction of InGaN in an unstrained state is GaN. Therefore, a compressive stress (compressive strain) in the a-axis direction is generated in the InGaN layer. On the other hand, since the a-axis average lattice constant of AlGaN in an unstrained state is smaller than the a-axis average lattice constant of GaN, tensile stress (tensile strain) in the a-axis direction is generated in the AlGaN layer.

The group III nitride semiconductor multilayer structure 42 is configured by laminating a buffer layer 44, a GaN electron transit layer 45, and an AlGaN electron supply layer 46 in this order from the substrate 41 side.
The buffer layer 44 is configured by laminating an AlN layer 47, a first AlGaN layer 48, and a second AlGaN layer 49. In this embodiment, the laminated structure of the first AlGaN layer 48 and the second AlGaN layer 49 is an example of the AlGaN laminated structure of the present invention. The second AlGaN layer 49 is an example of the reference AlGaN layer of the present invention, and the first AlGaN layer 48 is an example of the AlGaN layer disposed in contact with the surface of the reference AlGaN layer on the AlN layer side.

The thickness of the AlN layer 47 is 50 nm to 200 nm, for example, 120 nm. Moreover, the a-axis average lattice constant LC2 of the AlN layer 47 is, for example, 0.311 nm to 0.312 nm, and the linear expansion coefficient α2 is, for example, 4.1 × 10 ^{−6 to} 4.2 × 10 ⁻⁶ ( 293K).
In this embodiment, the first AlGaN layer 48 is configured as an undoped AlGaN layer to which impurities are not intentionally added. However, the first AlGaN layer 48 may contain a small amount of unintentional impurities. The thickness of the first AlGaN layer 48 is 100 nm to 500 nm, for example, 140 nm. The average Al composition of the first AlGaN layer 48 is 40 to 60% (for example, 50%). The a-axis average lattice constant LC3 of the first AlGaN layer 48 is, for example, 0.314 nm to 0.316 nm, and the linear expansion coefficient α3 is, for example, 4.6 × 10 ^{−6 to} 5.0 × 10 ^−6. (293K).

Further, the a-axis in-plane lattice constant LC3 ′ of the upper surface of the first AlGaN layer 48 (interface with the second AlGaN layer 49) is, for example, 0.312 nm to 0.314 nm.
In this embodiment, the second AlGaN layer 49 is configured as an undoped AlGaN layer to which impurities are not intentionally added. However, the second AlGaN layer 49 may contain a small amount of unintended impurities. The thickness of the second AlGaN layer 49 is 100 nm to 500 nm, for example, 140 nm. The average Al composition of the second AlGaN layer 49 is 10% or more smaller than that of the first AlGaN layer 48, specifically 10 to 30% (for example, 20%). The a-axis average lattice constant LC4 of the second AlGaN layer 49 is larger than the a-axis in-plane lattice constant LC3 ′ of the upper surface of the first AlGaN layer 48 (interface with the second AlGaN layer 49), and the a-axis average inherent in AlGaN. It is smaller than the lattice constant (0.316 nm to 0.318 nm), for example, 0.314 nm to 0.316 nm. The linear expansion coefficient α4 of the second AlGaN layer 49 is, for example, 5.0 × 10 ^{−6 to} 5.4 × 10 ⁻⁶ (293K).

In this embodiment, the GaN electron transit layer 45 is configured as an undoped GaN layer to which no impurity is intentionally added. However, the GaN electron transit layer 45 may contain a small amount of unintended impurities. The a-axis average lattice constant LC5 of the GaN electron transit layer 45 is, for example, 0.318 nm to 0.319 nm, and the linear expansion coefficient α5 is, for example, 5.5 × 10 ^{−6 to} 5.6 × 10 ⁻⁶ ( 293K).

  Further, the degree of distortion of the c-axis lattice constant of the GaN electron transit layer 45 is, for example, not less than −0.07% and not more than 0 (zero). The degree of distortion of the c-axis lattice constant can be obtained, for example, by measuring the c-axis lattice constant of the GaN electron transit layer 45 by X-ray diffraction measurement and comparing it with the c-axis lattice constant inherent to GaN. When the degree of distortion of the c-axis lattice constant of the GaN electron transit layer 45 is in the above-described range, the c-axis compressive stress applied to the GaN electron transit layer 45 is suppressed, and the generation of cracks can be prevented.

The c-axis and the a-axis are in a relationship orthogonal to each other. Therefore, as shown in FIG. 5, the compressive stress and tensile stress along these directions are applied in the other direction (for example, a-axis direction) when compressive stress is applied in one direction (for example, c-axis direction). There is a contradictory relationship such that a tensile stress is applied.
Therefore, as described above, the degree of distortion of the c-axis lattice constant of the GaN electron transit layer 45 is −0.07% or more and 0 (zero) or less, which means that the c-axis compressive stress applied to the GaN electron transit layer 45 is higher. It is suppressed and the occurrence of cracks can be prevented.

A BGaN portion 50 formed in a layer shape along the a-axis direction is formed in the middle of the GaN electron transit layer 45 in the thickness direction.
The BGaN portion 50 is a mixed crystal of BN (boron nitride) and GaN (gallium nitride), and has a wurtzite crystal structure. If the BGaN of the BGaN portion 50 is a wurtzite crystal structure, the crystal structure of the BGaN portion 50 and the GaN electron transit layer 45 can be made the same type (wurtzite crystal structure). That is, the BGaN portion 50 can function as a buffer layer that suppresses propagation of edge dislocations. As a result, a high quality device can be obtained.

The BGaN portion 50 having a wurtzite crystal structure specifically has a composition in which BGaN is represented by B _x Ga _1-x N (0.0 <x <0.02). It is preferable.
As the crystal structure of BN, hexagonal crystals (hBN) and rhombohedral crystals (rBN) of normal pressure stable phase, cubic zinc blende type (cBN) and hexagonal wurtzite type (cBN) of high temperature and high pressure stable phase ( Four crystal structures of wBN) are known.

If BGaN has a composition represented by B _x Ga _1-x N (0.0 <x <0.02), BN having a hexagonal wurtzite type (wBN) single crystal structure is favorably obtained. Obtainable. As a result, the BGaN portion 50 having a wurtzite crystal structure can be obtained favorably.
For example, if the crystal structure of BN is a cubic zinc blende type (cBN) single crystal structure, the crystal structure is inherited by GaN on the AlGaN electron supply layer 46 side with respect to the BGaN portion 50, and GaN is This is not preferable because the original wurtzite crystal structure cannot be maintained.

Further, the B composition x of BGaN in the BGaN portion 50 is preferably 0.0 <x <0.005. If the B composition x is in the above range, the flatness of the BGaN portion 50 can be maintained, and the quality (film quality) of the GaN electron transit layer 45 can be improved.
In addition, the layered BGaN portion 50 is not formed as a layer that forms a clear interface with GaN constituting the GaN electron transit layer 45, but in the GaN electron transit layer 45 rather than GaN. It is a portion where BN having a high density exists in a layered manner.

The thickness of the layered BGaN portion 50 is, for example, 5 nm or less, and preferably 2 nm to 5 nm. If the thickness of the BGaN portion 50 is in the above range, the flatness of the BGaN portion 50 can be maintained, and the quality (film quality) of the GaN electron transit layer 45 can be improved.
Further, the BGaN portion 50 is preferably formed on the substrate 41 side with respect to the central position in the thickness direction of the GaN electron transit layer 45. Specifically, the BGaN portion 50 is preferably formed at a height position of 100 nm to 300 nm (for example, 200 nm) from the lower end of the GaN electron transit layer 45.

In this embodiment, the AlGaN electron supply layer 46 is configured as an undoped AlGaN layer to which no impurity is intentionally added. However, the AlGaN electron supply layer 46 may contain a small amount of unintended impurities. The a-axis average lattice constant LC6 of the AlGaN electron supply layer 46 is, for example, 0.318 nm to 0.319 nm. The average Al composition of the AlGaN electron supply layer 46 is 20 to 30% (for example, 25%). The linear expansion coefficient α6 of the AlGaN electron supply layer 46 is, for example, 5.0 × 10 ^{−6 to} 5.2 × 10 ⁻⁶ (293K).

As described above, since the junction between the GaN electron transit layer 45 and the AlGaN electron supply layer 46 having different compositions is a heterojunction, the GaN electron transit layer 45 has a junction interface with the AlGaN electron supply layer 46 in the vicinity. Two-dimensional electron gas (2DEG) is generated. The two-dimensional electron gas is present in almost the entire region in the vicinity of the junction interface with the AlGaN electron supply layer 46 in the GaN electron transit layer 45, and the concentration thereof is, for example, 8 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm. ^-2 . In the HEMT element 3, the element operation is performed by passing a current between the source and the drain using the two-dimensional electron gas.

On the AlGaN electron supply layer 46, the electrode portion 25G of the gate pad 11, the electrode portion 20S of the source pad 10 and the electrode portion 14D of the drain pad 9 are spaced apart from each other so as to be in contact with the AlGaN electron supply layer 46. Is provided.
The electrode portion 25G (hereinafter, gate electrode 25G) of the gate pad 11 is made of an electrode material capable of forming a Schottky junction with the AlGaN electron supply layer 46, such as Ni / Au (nickel / gold alloy). be able to.

  The electrode part 20S of the source pad 10 (hereinafter referred to as source electrode 20S) and the electrode part 14D of the drain pad 9 (hereinafter referred to as drain electrode 14D) are both electrode materials capable of making ohmic contact with the AlGaN electron supply layer 46, For example, Ti / Al (titanium / aluminum alloy), Ti / Al / Ni / Au (titanium / aluminum / nickel / gold alloy), Ti / Al / Nb / Au (titanium / aluminum / niobium / gold alloy) Ti / Al / Mo / Au (alloy of titanium / aluminum / molybdenum / gold) or the like.

A back electrode 51 is formed on the back surface of the substrate 41. The back surface electrode 51 is connected to the base portion 5 of the terminal frame 2 to bring the potential of the substrate 41 to the ground (ground) potential. Note that the source electrode 20S may be set to the ground potential by setting the potential of the substrate 41 to the same potential as the source electrode 20S.
FIG. 6 is an illustrative view for explaining the configuration of a processing apparatus for growing each layer constituting the group III nitride semiconductor multilayer structure.

Next, with reference to FIG. 6, a method for producing a group III nitride semiconductor multilayer structure will be described in detail.
A susceptor 62 incorporating a heater 61 is disposed in the processing chamber 60. The susceptor 62 is coupled to a rotation shaft 63, and the rotation shaft 63 is rotated by a rotation drive mechanism 64 disposed outside the processing chamber 60. Thus, by holding the wafer 65 to be processed on the susceptor 62, the wafer 65 can be heated to a predetermined temperature in the processing chamber 60 and can be rotated. The wafer 65 is a Si single crystal wafer that constitutes the Si single crystal substrate 41 described above.

An exhaust pipe 66 is connected to the processing chamber 60. The exhaust pipe 66 is connected to exhaust equipment such as a rotary pump. Thereby, the pressure in the processing chamber 60 is set to 1/10 atm to normal pressure, and the atmosphere in the processing chamber 60 is always exhausted.
On the other hand, a raw material gas supply path 70 for supplying a raw material gas toward the surface of the wafer 65 held by the susceptor 62 is introduced into the processing chamber 60. The source gas supply path 70 includes a nitrogen source pipe 71 for supplying ammonia as a nitrogen source gas, a gallium source pipe 72 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. An aluminum raw material pipe 73 for supplying (TMAl), a boron raw material pipe 74 for supplying triethylboron (TEB) as a boron raw material gas, and ethylcyclopentadienylmagnesium (EtCp ₂ Mg) as a magnesium raw material gas are supplied. A magnesium raw material pipe 75, a silicon raw material pipe 76 for supplying silane (SiH ₄ ) as a silicon raw material gas, and a carrier gas pipe 77 for supplying a carrier gas are connected. Valves 81 to 87 are interposed in these raw material pipes 71 to 77, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.

  For example, a Si single crystal wafer having a (111) plane as a main surface is held on the susceptor 62 as a wafer 65. In this state, the valves 81 to 86 are closed, the carrier gas valve 87 is opened, and the carrier gas is supplied into the processing chamber 60. Furthermore, the heater 61 is energized, and the wafer temperature is raised to 1000 ° C. to 1100 ° C. (for example, 1050 ° C.). As a result, the group III nitride semiconductor can be grown without causing surface roughness.

After waiting until the wafer temperature reaches 1000 ° C. to 1100 ° C., the nitrogen material valve 81 and the aluminum material valve 83 are opened. As a result, ammonia and trimethylaluminum are supplied from the source gas supply path 70 together with the carrier gas. As a result, the AlN layer 47 is epitaxially grown on the surface of the wafer 65.
Next, the first AlGaN layer 48 is formed. That is, the nitrogen material valve 81, the gallium material valve 82, and the aluminum material valve 83 are opened, and the other valves 84 to 86 are closed. As a result, ammonia, trimethylgallium and trimethylaluminum are supplied toward the wafer 65, and the first AlGaN layer 48 made of AlGaN is formed. When the first AlGaN layer 48 is formed, the temperature of the wafer 65 is preferably 1000 ° C. to 1100 ° C. (for example, 1050 ° C.).

  Next, a second AlGaN layer 49 is formed. That is, the nitrogen material valve 81, the gallium material valve 82, and the aluminum material valve 83 are opened, and the other valves 84 to 86 are closed. As a result, ammonia, trimethylgallium and trimethylaluminum are supplied toward the wafer 65, and the second AlGaN layer 49 made of AlGaN is formed. When the second AlGaN layer 49 is formed, the temperature of the wafer 65 is preferably 1000 ° C. to 1100 ° C. (for example, 1050 ° C.).

  Next, the GaN electron transit layer 45 is formed. When the GaN electron transit layer 45 is formed, the nitrogen source valve 81 and the gallium source valve 82 are opened and ammonia and trimethyl gallium are supplied to the wafer 65 to grow the GaN layer. When a GaN layer having a predetermined thickness is grown on the second AlGaN layer 49, the boron material valve 84 is opened and the triethylboron is supplied to the wafer 65 while the valves 81 and 82 are opened. As a result, the BGaN portion 50 is formed in the middle of the GaN electron transit layer 45 in the thickness direction. After the formation of the BGaN portion 50 having a predetermined thickness, the boron source valve 84 is closed while the valves 81 and 82 are open, the supply of triethylboron is stopped, and the growth of the GaN layer is continued. Thereby, the GaN electron transit layer 45 in which the BGaN portion 50 is formed is formed. When the GaN electron transit layer 45 is formed, the temperature of the wafer 65 is preferably 1000 ° C. to 1100 ° C. (for example, 1050 ° C.), and when the BGaN portion 50 is formed, the temperature of the wafer 65 is, for example, The temperature is preferably 1000 ° C. to 1100 ° C. (for example, 1050 ° C.).

  Next, the AlGaN electron supply layer 46 is formed. That is, the nitrogen material valve 81, the gallium material valve 82, and the aluminum material valve 83 are opened, and the other valves 84 and 85 are closed. As a result, ammonia, trimethylgallium, and trimethylaluminum are supplied toward the wafer 65, and the AlGaN electron supply layer 46 is formed. When the AlGaN electron supply layer 46 is formed, the temperature of the wafer 65 is preferably 1000 ° C. to 1100 ° C. (for example, 1050 ° C.).

Thereafter, the wafer 65 is left at room temperature for 20 to 60 minutes and cooled. Thus, a group III nitride semiconductor multilayer structure 42 is formed.
As described above, according to this embodiment, the layered BGaN portion 50 is formed in the middle portion of the GaN electron transit layer 45. The BGaN of the BGaN portion 50 is a mixed crystal of BN (boron nitride) and GaN (gallium nitride).

  Since BN having high insulating properties is included as a mixed crystal with GaN in the middle of the GaN electron transit layer 45, the thickness direction AlGaN electron supply layer 46 with respect to the BGaN portion 50 in the GaN electron transit layer 45. The conductivity between the side and the substrate 41 side can be reduced. As a result, when the gap between the source electrode 20S and the drain electrode 14D is off, generation of a current path in the stacking direction (vertical direction) of the group III nitride semiconductor stacked structure 42 from the source electrode 20S to the substrate 41 is prevented. It can be prevented, or even if it occurs, the current flowing through the current path can be reduced. As a result, the leakage current when the HEMT element 3 is off can be reduced.

  On the other hand, the AlN layer 47, the first AlGaN layer 48, and / or the second AlGaN layer 49 of the buffer layer 44 is a nitride semiconductor having higher insulation than GaN. Therefore, increasing the series resistance of the nitride semiconductor layers 47 to 49 by increasing the thickness of the nitride semiconductor layers 47 to 49 may reduce the leakage current. However, if these nitride semiconductor layers 47 to 49 are too thick, cracks may occur in the wafer, which is not practical.

  Therefore, in this embodiment, by providing the BGaN portion 50 that can exist as a mixed crystal with GaN in the GaN electron transit layer 45, the leakage current can be reduced, and at the same time, the nitride semiconductor layers 47 to 49 The thickness can be limited to about 120 nm (AlN layer 47), 140 nm (first AlGaN layer 48), and 140 nm (second AlGaN layer 49), respectively. As a result, generation of cracks in the wafer can also be prevented.

  In addition, the BGaN portion 50 is sandwiched by the GaN layers from both sides in the thickness direction in the middle of the GaN electron transit layer 45, not in the interface with the buffer layer 44 (second AlGaN layer 49) in the GaN electron transit layer 45. Therefore, a ternary mixed crystal BGaN having a wurtzite crystal structure can be formed with high accuracy by boron atoms (B), gallium atoms (Ga) and nitrogen atoms (N). On the other hand, when the BGaN portion 50 is provided so as to form an interface with the second AlGaN layer 49 in the GaN electron transit layer 45, the AlGaN buffer layers 48 and 49 can be removed from the GaN due to imperfection of the BGaN crystal. The compressive stress transmitted to the electron transit layer 45 is weakened, which is not preferable. If the compressive stress is weak, cracks may occur.

Since the HEMT package 1 including the HEMT element 3 can reduce leakage current when the transistor operation of the HEMT element 3 is turned off, a highly reliable package can be provided.
In this embodiment, an AlN layer 47, a first AlGaN layer 48 (Al average composition 50%), and a second AlGaN layer 49 (Al average composition 20%) are laminated on the Si single crystal substrate 41 in this order. A buffer layer 44 is provided, and the GaN electron transit layer 45 is formed in contact with the main surface (c-plane) of the second AlGaN layer 49.

  As a result, the a-axis average lattice constant from the AlN layer 47 to the GaN electron transit layer 45 is changed to LC2 (0.311 nm), LC3 (0.314 nm) and LC4 (0.316 nm) and the a-axis average of the GaN electron transit layer. The value can be increased stepwise to a value close to the lattice constant LC5 (0.318 nm). Therefore, the difference (LC5-LC4) in the a-axis average lattice constant between the GaN electron transit layer 45 and the second AlGaN layer 49 in contact with the GaN electron transit layer 45 can be reduced. As a result, the thickness of the GaN electron transit layer 45 can be designed freely. Therefore, the breakdown voltage of the HEMT element 3 can be improved by designing the GaN electron transit layer 45 to be thick.

  Further, the compressive stress applied to the first AlGaN layer 48 due to the a-axis average lattice constant difference (LC3−LC2) between the AlN layer 47 and the first AlGaN layer 48 can be propagated to the second AlGaN layer 49. Thereby, the a-axis average lattice constant LC4 of the second AlGaN layer 49 is larger than the a-axis in-plane lattice constant LC3 ′ of the first AlGaN layer 48 in contact with the second AlGaN layer 49, and the a-axis average lattice inherent in the second AlGaN layer 49 It is smaller than a constant. That is, the a-axis compressive stress is applied to the second AlGaN layer 49 so as not to align with the a-axis in-plane lattice constant LC3 ′ of the first AlGaN layer 48. Then, this a-axis compressive stress can be applied to the GaN electron transit layer 45.

Therefore, during or after cooling after the formation of the group III nitride semiconductor multilayer structure 42, the tensile stress caused by the difference (α5-α1) in the linear expansion coefficient between the substrate 41 and the GaN electron transit layer 45 is caused by the GaN electron transit layer. Even if it occurs at 45, the tensile stress can be relaxed by the compressive stress applied from the second AlGaN layer 49 to the GaN electron transit layer 45.
As a result, as described above, the degree of distortion of the c-axis lattice constant of the GaN electron transit layer 45 can be set to −0.07% or more and 0 (zero) or less, that is, the GaN electron transit layer 45 has cracks. It can be held in a state in which a-axis tensile stress that does not occur is applied. Therefore, cracks in the GaN electron transit layer 45 and warping of the substrate 41 can be reduced.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form.
For example, the composition of BGaN is not limited to B _x Ga _1-x N (0.0 <x <0.02) as long as the leakage current of the HEMT element 3 can be reduced. Similarly, the thickness of the BGaN portion 50 may exceed 5 nm as long as the leakage current of the HEMT element 3 can be reduced.

The substrate 41 is replaced with a GaN substrate (for example, a GaN substrate having a c-plane as a main surface), a SiC substrate (for example, a SiC substrate having a c-plane as a main surface), or a sapphire substrate (for example, instead of a Si single crystal substrate). , A sapphire substrate having a c-plane as a main surface). When the substrate 41 is a GaN substrate, the buffer layer 44 can be omitted.
In addition, the AlGaN stacked structure of the buffer layer 44 does not need to be composed of two AlGaN layers 48 and 49 having different Al compositions. For example, the first AlGaN layer (average Al composition is 80%), a second AlGaN layer (average Al composition is 60%, for example), a third AlGaN layer (average Al composition is 40%, for example), and a fourth AlGaN layer (average Al composition is 20%, for example). It may be configured. Alternatively, three AlGaN layers having different Al compositions from each other, five AlGaN layers, and a larger number of AlGaN layers may be stacked.

  The buffer layer 44 may be composed of a single layer of the AlN layer 52 as shown in FIG. Moreover, as shown in FIG. 8, the AlN layer 53 and the AlGaN layer 54 may be composed of an AlN / AlGaN superlattice layer 55 in which a plurality of pairs are alternately stacked. Moreover, as shown in FIG. 9, the AlGaN layer 56 and the GaN layer 57 may be composed of an AlGaN / GaN superlattice layer 58 in which a plurality of pairs are alternately stacked.

  In addition, various design changes can be made within the scope of matters described in the claims.

Next, although this invention is demonstrated based on an Example and a comparative example, this invention is not limited by the following Example.
<Examples and Comparative Examples>
Examples and comparative examples were carried out in order to prove the effect of reducing the leakage current and edge dislocation density according to the present invention.
(1) Example First, an AlN layer (120 nm thickness) was epitaxially grown on the surface of a Si single crystal substrate having a (111) plane as a main surface. Next, a first AlGaN layer (average Al composition 50% 140 nm thickness) and a second AlGaN layer (average Al composition 20% 140 nm thickness) were epitaxially grown in order. Thereby, a buffer layer was formed.

Next, a GaN electron transit layer (thickness: 1000 nm) and an AlGaN electron supply layer were formed in this order on the second AlGaN layer, thereby producing the group III nitride semiconductor multilayer structure shown in FIG. During the growth of the GaN electron transit layer, a BGaN portion (B composition 0.5% 5 nm thickness) was formed at a position 200 nm from the surface of the GaN electron transit layer with the second AlGaN layer.
Thereafter, a source electrode and a drain electrode were formed on the AlGaN electron supply layer.

In addition, a group III nitride semiconductor multilayer structure provided with a BGaN portion having a thickness of 10 nm and a BGaN portion having a thickness of 15 nm was similarly produced.
(2) Comparative Example A group III nitride semiconductor multilayer structure was fabricated by the same method as in the example except that the BGaN portion was not formed (BGaN thickness was 0 nm).
<Evaluation>
(1) Measurement of Leakage Current First, etching was performed from the surface of the AlGaN electron supply layer to the middle part of the GaN electron transit layer (above the BGaN part) between the source electrode and the drain electrode. As a result, as shown in FIG. 10, a state where the two-dimensional electron gas was pinched off was generated, and a pseudo-off state was formed.

FIG. 11 shows a leakage current when a voltage (100 V) is applied between the source and the drain of the group III nitride semiconductor multilayer structure obtained in the example (BGaN thickness 5 nm only) and the comparative example.
As can be seen from FIG. 11, in the structure of the example in which the GaN electron transit layer is provided with the BGaN portion, the magnitude of the leakage current is reduced by about one digit compared to the structure of the comparative example (FIG. 11). (See black circle plot).
(2) Rocking curve measurement The X-ray rocking curve measurement by (1000) plane (omega) scan was performed with respect to the GaN electron transit layer of the group III nitride semiconductor laminated structure obtained by the Example and the comparative example. The full width at half maximum obtained by the measurement is shown in FIG.

  From FIG. 11, it was found that the half width (arcsec .: second) was reduced in the structure of the example in which the GaN electron transit layer was provided with the BGaN portion compared to the structure of the comparative example. Thereby, it was confirmed that the edge dislocation density of the GaN electron transit layer can be reduced (see the black triangular plot in FIG. 11).

DESCRIPTION OF SYMBOLS 1 HEMT package 3 HEMT element 4 Resin package 14D (drain pad) electrode part 20S (source pad) electrode part 25G (gate pad) electrode part 41 Substrate 43 (Substrate) main surface 44 Buffer layer 45 GaN electron transit layer 46 AlGaN electron supply layer 47 AlN layer 48 First AlGaN layer 49 Second AlGaN layer 50 BGaN portion 52 AlN layer 53 AlN layer 54 AlGaN layer 55 AlN / AlGaN superlattice layer 56 AlGaN layer 57 GaN layer 58 AlGaN / GaN superlattice layer

Claims (19)

A semiconductor substrate;
A GaN electron transit layer formed on the semiconductor substrate;
In the middle part of the GaN electron transit layer in the thickness direction, a BGaN part formed in a layer shape along a direction perpendicular to the thickness direction;
An AlGaN electron supply layer formed on the GaN electron transit layer;
On the AlGaN electron supply layer, a source electrode and a drain electrode formed with a space therebetween,
A nitride semiconductor device comprising a gate electrode formed between the source electrode and the drain electrode on the AlGaN electron supply layer.   The nitride semiconductor device according to claim 1, wherein the BGaN in the BGaN portion has a wurtzite crystal structure. 3. The nitride semiconductor device according to claim 1, wherein BGaN in the BGaN portion has a composition represented by B _x Ga _1-x N (0.0 <x <0.02).   The nitride semiconductor device according to claim 3, wherein the B composition x of BGaN is 0.0 <x <0.005.   The nitride semiconductor device according to claim 1, wherein the BGaN portion has a thickness of 5 nm or less.   The nitride semiconductor device according to any one of claims 1 to 5, wherein the BGaN portion is formed closer to the semiconductor substrate than a central position in the thickness direction of the GaN electron transit layer. The GaN electron transit layer has a thickness of 500 nm to 1500 nm;
The nitride semiconductor device according to claim 6, wherein the BGaN portion is formed at a height position of 100 nm to 300 nm from a lower end of the GaN electron transit layer.   The nitride semiconductor device according to claim 1, further comprising a buffer layer interposed between the GaN electron transit layer and the semiconductor substrate.   The nitride semiconductor device according to claim 8, wherein the semiconductor substrate is a Si substrate. The buffer layer includes an AlN layer formed on the semiconductor substrate, and an AlGaN stacked structure formed on the AlN layer and formed by stacking a plurality of AlGaN layers,
10. The nitride semiconductor device according to claim 9, wherein in the AlGaN laminated structure, an Al composition of a certain reference AlGaN layer is smaller than an Al composition of an AlGaN layer closer to the AlN layer than the reference AlGaN layer.   In the AlGaN laminated structure, the difference between the Al composition (%) of the reference AlGaN layer and the Al composition (%) of the AlGaN layer disposed in contact with the surface of the reference AlGaN layer on the AlN layer side is 10% or more. The nitride semiconductor device according to claim 10, wherein   12. The nitride semiconductor according to claim 10, wherein the AlGaN stacked structure is a structure in which a first AlGaN layer having an Al composition of 50% and a second AlGaN layer having an Al composition of 20% are stacked in order from the AlN layer. element. The plane orientation of the main surface of the buffer layer is c-plane,
In the AlGaN laminated structure, the a-axis average lattice constant of the reference AlGaN layer is larger than the a-axis in-plane lattice constant of the AlGaN layer arranged in contact with the surface of the reference AlGaN layer on the AlN layer side, The nitride semiconductor device according to any one of claims 10 to 12, which is smaller than an a-axis average lattice constant inherently possessed by the AlGaN layer.   The nitride semiconductor device according to claim 9, wherein the main surface of the Si substrate is a (111) surface.   The nitride semiconductor device according to claim 14, wherein a degree of distortion of the c-axis lattice constant of the GaN electron transit layer is −0.07% or more.   The nitride semiconductor device according to claim 8 or 9, wherein the buffer layer is formed of a single layer of an AlN layer formed on the semiconductor substrate.   The nitride semiconductor device according to claim 8 or 9, wherein the buffer layer has a superlattice structure in which a plurality of pairs of AlN layers and AlGaN layers are alternately stacked.   The nitride semiconductor device according to claim 8 or 9, wherein the buffer layer has a superlattice structure in which a plurality of pairs of AlGaN layers and GaN layers are alternately stacked. The nitride semiconductor device according to any one of claims 1 to 18, and
And a resin package formed to cover the nitride semiconductor element.

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