JP2013004718A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphene transistor using a graphene layer as a channel, which achieves low power consumption by reduction of off-leak.SOLUTION: A field-effect semiconductor device using a graphene layer as a channel, comprises: a channel region 45 composed of a graphene layer 40 formed on a substrate 10 and having a predetermined band gap; source/drain regions formed on both sides of the channel region 45, respectively, and each composed of the graphene layer 40 having a band gap smaller than that of the channel region 45; two gate electrodes 61, 62 formed on parts of the source/drain regions, which contact the channel region 45, respectively, and arranged in parallel with each other so as to cross the channel; and metal catalyst layers 21, 22 formed on contact parts of the source/drain regions, respectively.

Description

  Embodiments described herein relate generally to a field effect semiconductor device using a graphene layer as a channel and a method for manufacturing the same.

  In recent years, a graphene transistor using a graphene layer as a channel has been proposed (see, for example, Patent Document 1 and Non-Patent Document 1). This graphene transistor is attracting attention as a super high speed operation and ultra low power consumption by replacing it with a silicon device.

  However, since this type of graphene transistor has a small channel energy band gap, there is a problem that off-leakage current is large and power consumption is increased. Further, in graphene in a state where an energy band gap is generated, carrier mobility may decrease, which is a factor that hinders high-speed operation of the transistor. Further, in the graphene transistor of the prior art, when the electronic state of graphene is controlled to n-type or p-type by the back gate, a high resistance p / n junction may be formed between the top gate and the contact region. This causes a decrease in the drive current value of the transistor.

  In addition, an industrially manufacturable graphene layer is formed on the surface of a conductor such as a metal catalyst layer, but it is necessary to remove the metal catalyst layer in order to produce a graphene transistor. When the suspended graphene layer from which the metal catalyst layer is removed is used as a channel, it is very difficult to add a structure such as a top gate to the suspended graphene. In particular, when the suspended graphene layer has a very fine structure such as a graphene nanoribbon, it is easily broken during processing of a top gate or the like, and is further difficult to process.

JP 2009-164432 A

Physical Review Letters 98,206805 (2007), US Patent US2009 / 0140801 (Columbia University)

  The problem to be solved by the present invention is to provide a field effect semiconductor device capable of reducing power consumption by reducing off-leakage in a graphene transistor using a graphene layer as a channel.

  Another problem to be solved by the invention is to provide a semiconductor device manufacturing method capable of avoiding damage to the nanoribbon structure due to the top gate formation process in manufacturing the semiconductor device.

  A semiconductor device of one embodiment of the present invention includes a channel region formed on a substrate and including a graphene layer having a predetermined band gap, and graphene formed on both sides of the channel region, each having a smaller band gap than the channel region. A source / drain region composed of layers, two gate electrodes formed on a portion of the source / drain region in contact with the channel region and arranged in parallel to each other so as to cross the channel, and the source / drain And a metal catalyst layer formed on each contact portion of the region.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a metal catalyst layer in an island shape on a substrate; forming a graphene layer on the metal catalyst layer; and forming the graphene layer on the graphene layer. Forming two gate electrodes in parallel to each other; and the graphene layer on the graphene layer between the gate electrodes, having a stripe along the opposing direction of the gate electrode and outside the gate electrode Forming a protective film covering the layer, selectively etching the graphene layer using the protective film and the gate electrode as a mask, and etching the metal catalyst layer exposed by etching the graphene layer And a step of removing the metal catalyst layer under the graphene layer between the gate electrodes.

  According to the present invention, by applying voltages in opposite directions to the two gate electrodes formed on the graphene layer, the energy band gap existing between the gate electrodes becomes a potential barrier, and a high potential barrier can be obtained. . Accordingly, off-leakage can be reduced, and power consumption can be reduced.

  Moreover, since nanoribbon processing is performed after top gate processing, damage to the nanoribbon structure due to the top gate formation step can be avoided. Therefore, a transistor structure using a graphene layer formed on the surface of the metal catalyst as a channel can be realized.

The top view and sectional drawing for demonstrating schematic structure of the graphene transistor concerning 1st Embodiment. The top view and sectional drawing for demonstrating the manufacturing process of the graphene transistor concerning 1st Embodiment. The top view and sectional drawing for demonstrating the manufacturing process of the graphene transistor concerning 1st Embodiment. The top view and sectional drawing for demonstrating the manufacturing process of the graphene transistor concerning 1st Embodiment. The top view and sectional drawing for demonstrating the manufacturing process of the graphene transistor concerning 1st Embodiment. FIG. 3 is a schematic diagram for explaining a band structure in the transistor of the first embodiment. The top view and sectional drawing for demonstrating schematic structure of the graphene transistor concerning 2nd Embodiment. The top view and sectional drawing for demonstrating schematic structure of the graphene transistor concerning 3rd Embodiment. The schematic diagram for demonstrating the band structure in the transistor of 3rd Embodiment.

  Details of the embodiment will be described below with reference to the drawings.

(First embodiment)
1A and 1B are diagrams for explaining a schematic configuration of the graphene transistor according to the first embodiment, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. ) Is a cross-sectional view taken along the line BB ′ in FIG.

  On the insulating substrate 10, rectangular metal catalyst thin films 21, 22 are formed at a certain distance in the source / drain direction of a transistor to be described later. Here, the thin film 21 is the source side, and the thin film 22 is the drain side. Contacts 31 and 32 of, for example, gold are formed on the opposite sides of the opposing regions of the metal catalyst thin films 21 and 22, respectively. A graphene layer 40 having a film thickness of 1 to 10 is formed on the surfaces of the metal catalyst thin films 21 and 22 so as to straddle the thin films 21 and 22. Therefore, the graphene layer 40 has a suspended structure between the thin films 21 and 22. The insulating substrate 10 itself may be an insulator, or an insulating film such as a silicon oxide film or sapphire may be formed on a semiconductor or conductive substrate.

  On the graphene layer 40, two sets of gate stacks (top gates) are formed in parallel to each other in a direction to divide the source and drain. The gate stack on the source side is formed of a gate insulating film 51 such as aluminum oxide and a gate electrode 61 using a metal such as gold, and the gate stack on the drain side is formed of a gate insulating film 52 such as aluminum oxide and a gold The gate electrode 62 is made of a metal such as.

  The graphene layer 40 between the gate electrodes is narrowed by etching and processed into a ribbon shape. The width of the graphene nanoribbon 45 processed into a ribbon shape is set to 10 nm, for example.

  Next, the manufacturing method of the graphene transistor of this embodiment is demonstrated with reference to FIGS. 2 to 5, (a) is a plan view, (b) is a sectional view taken along line AA ′ in (a), and (c) is a sectional view taken along line BB ′ in (a). Show.

  First, as shown in FIGS. 2A and 2B, a thin film 20 such as copper, which is a catalyst for graphene growth, is deposited on the insulating substrate 10, and then, for example, RIE (reactive ion etching). ) Or the like, for example, an etching process is performed so that the thin film 20 remains only in a region having a desired shape such as a rectangle, and the mesa structure of the metal catalyst thin film 20 is formed. After the contacts 31 and 32 such as gold are formed on both ends of the metal catalyst thin film 20 having the rectangular mesa structure, a known method such as chemical vapor deposition is performed on the surface of the metal catalyst thin film 20. A graphene layer 40 having a thickness of 1 to 10 is formed. Specifically, for example, carbon is deposited on the surface of the metal catalyst thin film 20 using ethylene or acetylene gas.

  Note that graphene formed on a metal catalyst is much easier to make than graphene formed on an insulating layer, and is more industrially realistic. Further, the growth process of the graphene layer 40 may be performed before the formation process of the contacts 31 and 32, and may be performed before the mesa processing of the metal catalyst thin film 20.

  Next, as shown in FIGS. 3A and 3B, an insulating film such as aluminum oxide and a metal film such as gold are stacked, and then processed into a gate structure by RIE or the like, whereby two sets of gates are formed. Form a stack. That is, two sets of gate stacks (top gates) composed of the gate insulating films 51 and 52 and the gate electrodes 61 and 62 are formed in parallel in the direction of dividing the source and drain. At this time, the distance between the two gate electrodes is determined from the request for the performance of the element. That is, if the gate interval is too short, the tunnel current between the source and the drain becomes too large, so that the interval is preferably 1 nm or more. On the other hand, if the gate interval is too long, the resistance of the channel increases and the operation speed of the circuit decreases, so the gate interval is preferably 100 nm or less, preferably 20 nm or less.

Next, as shown in FIGS. 4A to 4C, the graphene layer 40 between the source-side contact 31 and the gate stacks 51 and 61, and between the drain-side contact 32 and the gate stacks 52 and 62. A protective film 70 that covers each of the graphene layers 40 is formed of, for example, SiO ₂ . Further, the protective film 70 has a thin line portion 75 covering a part of the graphene region exposed between the two gate electrodes.

  Next, as shown in FIGS. 5A to 5C, the portion of the graphene layer 40 that is not covered with the protective film 70 is removed by RIE, for example. As a result, the graphene nanoribbon 45 is formed only between the two gate regions. Here, the width of the graphene nanoribbon 45 is related to the energy band gap. That is, in order to obtain a sufficient band gap, the nanoribbon width is desirably 20 nm or less, and more desirably 10 nm or less.

  Note that a method for forming a band gap in the graphene layer 40 is not necessarily limited to processing the graphene layer 40 into a nanoribbon. For example, the graphene layer 40 may be chemically modified by doping oxygen, hydrogen, or the like, or minute holes having a radius of about 10 nm are formed in the graphene layer at a high density, and the graphene layer 40 is processed into a mesh shape. It is also possible to introduce dot defects.

  Subsequently, a step of dissolving and removing the metal catalyst thin film 20 with a chemical solution such as an acid is performed. At this time, when the metal catalyst thin film 20 between the two gates is exposed and immersed in the chemical solution, the chemical solution penetrates into the metal catalyst thin film 20 in the lower region of both gates, and the graphene between the two gate stacks. It similarly penetrates into the metal catalyst thin film 20 in the lower region of the nanoribbon 45. That is, the portion 25 that is removed by isotropic etching also includes the lower region of the two gate stacks and the metal catalyst thin film 20 below the graphene nanoribbon 45 around the gap portion between the two gate stacks. Span the territory. As a result, the metal catalyst thin film 20 is separated into the source side 21 and the drain side 22.

  Here, even if a part of the metal catalyst thin film 20 under the gate remains, there is no problem as long as the metal catalyst under the gate end on the nanoribbon side is sufficiently removed. In this embodiment, the case where the metal catalyst thin film 20 under the top gate region is completely removed is shown.

  Thereafter, by removing the protective film 70, the element structure of the present embodiment shown in FIG. 1 is completed. Note that the protective film 70 is not necessarily removed.

  Next, the operation of the transistor of this embodiment will be described. 6A and 6B are diagrams for explaining the operation of the transistor of the first embodiment. FIG. 6A is a diagram illustrating the arrangement of a graphene layer and a gate, and FIGS. 6B and 6C are graphenes having the structure of FIG. It is an energy band figure on the AA 'line containing a graphene nanoribbon of an element. Further, FIG. 6B shows the band structure in the off state, and FIG. 6C shows the band structure in the on state.

  Here, in the graphene region where no band gap is generated, there is a Dirac point 80 where the conduction band and the valence band are in contact with each other. On the other hand, in the region where the graphene nanoribbon 45 is formed, an energy band gap 81 exists between the conduction band and the valence band.

  First, the off state will be described with reference to FIG. By applying a positive bias to the drain, the Fermi energy 82 of electrons is lower in the drain region than in the source region (FIG. 6 (b) 83). At this time, by applying a negative bias to the gate electrode 61 on the source side, a Dirac point shift 84 of the graphene region under the gate occurs, and as a result, the graphene region becomes p-type. At the same time, by applying a positive bias to the gate electrode 62 on the drain side, a Dirac point shift 85 of the graphene region under the gate occurs, and as a result, the graphene region becomes n-type.

  By the above operation, a high energy barrier is formed at the source end of the graphene nanoribbon in the propagation of conduction electrons near the Fermi energy from the source side to the drain side, and at the same time, the same is true in the propagation of holes from the drain side to the source side. A high energy barrier is formed. Therefore, the leakage current due to thermal excitation in the off state is expected to be reduced by a potential barrier equal to or higher than the band gap energy value. In addition, by optimizing the length of the graphene nanoribbon, it is possible to set a sufficiently long interband tunneling distance (tunneling length) from the p-type source region to the n-type drain region. It is expected that off-leakage current due to current is suppressed.

  Next, the ON state will be described with reference to FIG. When the polarity of the voltage is reversed with respect to the source-side gate electrode 61 to which a negative bias is applied in the off state, the polarity of the Dirac point movement 84 in the graphene region under the source-side gate is reversed. As a result, the energy band gap generated by the graphene nanoribbon always exists on the lower energy side than the Fermi energy. This allows electrons to propagate through the graphene nanoribbon, thus turning on the transistor. Here, the energy band gap 81 of the graphene nanoribbon is always higher than the Fermi energy 82 even when a negative negative bias is applied to the drain-side gate electrode 62 instead of the source-side gate electrode 61. The transistor can be turned on. Furthermore, when the magnitude of the gate bias on at least one of the source side and the drain side is made larger than that in the off state, the tunnel length between the bands is shortened, so that the transistor can be turned on.

  Here, when the graphene transistor is in the ON state, electrons injected into the graphene nanoribbon region have a high speed in the wide graphene, and thus a high injection electron speed is expected. Furthermore, the ribbon length of the graphene nanoribbon can be significantly shortened compared to the prior art, and the influence of the mobility deterioration in the graphene nanoribbon on the operation speed of the circuit can be minimized. .

  By the above method, the transistor of this embodiment that operates at high speed and with low leakage current is manufactured with graphene on the metal catalyst layer. In particular, in the transistor of this embodiment, since the region where the band gap is generated is graphene having a suspended structure, higher charge mobility is expected. Furthermore, since the gate length of the top gate can be shortened, the capacitance between the top gate and the graphene layer is expected to be reduced.

  Further, even if the polarity of the operation bias voltage in the above embodiment is reversed, the transistor operation can be performed based on the same principle. That is, an off state can be obtained by a negative drain bias, a positive source side gate bias, and a negative drain side gate bias, and an on state can be obtained by making the source side gate bias negative or by making the drain side gate bias positive. . This means that the polarity of the transistor of the present embodiment can be freely changed between n-type and p-type, and thus an electrically reconfigurable circuit is realized.

  As described above, according to the present embodiment, since the two gates are formed so as to cross the graphene nanoribbon region 45 of the graphene layer 40, two gates can be obtained by applying a reverse voltage to these gates. The energy band gap existing between them becomes a potential barrier. Therefore, a reliable off state can be obtained by the high potential barrier, and power consumption can be reduced.

  In addition, the nanoribbon region having low mobility can be shortened as much as possible, and further, the operation speed of the transistor is improved because the charge injection speed into the nanoribbon portion is due to very high-speed electrons in the bulk graphene. Further, since the nanoribbon portion where the mobility is most deteriorated is in the suspended graphene state, the mobility of the charge is increased, so that the structure of this embodiment contributes to further increase in the operation speed of the transistor. In addition, the structure of this embodiment has an advantage that damage to the nanoribbon structure due to the top gate process can be avoided because nanoribbon processing is performed after top gate processing.

  Note that in the configuration of this embodiment, a back gate may be formed in order to give an energy offset to the graphene layer, or the graphene layer may be p-type or doped by doping electrons or holes by attaching impurities to the entire graphene layer. It may be n-type.

(Second Embodiment)
7A and 7B are diagrams for explaining a schematic configuration of the graphene transistor according to the second embodiment, in which FIG. 7A is a plan view, FIG. 7B is a cross-sectional view taken along line AA ′ in FIG. ) Is a cross-sectional view taken along the line BB ′ in FIG. In addition, the same code | symbol is attached | subjected to the same part as FIG. 1, and the detailed description is abbreviate | omitted.

  The difference between this embodiment and the first embodiment described above is that not all of the metal catalyst in the lower portion of the gate region is removed, but a part of the metal catalyst in the lower portion of the gate region is left. The basic configuration is the same as in the first embodiment, and the metal catalyst thin film under the gate region is removed on the graphene ribbon side and the source / drain electrode side remains.

  With such a configuration, the following advantages can be obtained as well as the same effects as those of the first embodiment described above. That is, since a part of the metal catalyst layer remains in the lower part of the gate region, the metal catalyst thin films 21 and 22 are in direct electrical contact with the graphene layer 40 controlled by the gate electrodes 61 and 62. For this reason, when the polarities are different between the inside and outside of the gate region, a high resistance state including a Dirac point at the boundary between them can be avoided, which contributes to an increase in driving current. At this time, an overlap between the gate region and the contact region occurs, which contributes to reduction of the element area.

(Third embodiment)
8A and 8B are diagrams for explaining a schematic configuration of the graphene transistor according to the third embodiment. FIG. 8A is a plan view, FIG. 8B is a cross-sectional view taken along the line AA ′ in FIG. ) Is a cross-sectional view taken along the line BB ′ in FIG. In addition, the same code | symbol is attached | subjected to the same part as FIG. 1, and the detailed description is abbreviate | omitted.

  The difference between this embodiment and the first embodiment is that the number of gates is one instead of two.

  In the present embodiment, one top gate including the gate insulating film 51 and the gate electrode 61 is formed for the graphene layer 40. The channel region constituted by the graphene layer 40 is defined by the following method. That is, the channel portion is exposed such that one end of the channel region is limited by using the gate as a mask and the other end is limited by a mask (not shown). Then, a process for forming the channel region as a semiconductor, that is, a step of forming a band gap in the graphene layer 40 is performed. Here, the processing in which the channel region becomes semiconducting is the same as the method described in the first embodiment, and may be performed by chemical modification or by introducing antidot defects.

  In the present embodiment, the entire graphene layer is doped p-type or n-type in order to improve the polarity of the voltage required for the gate operation to only one side. If electrons are doped by attaching a metal such as potassium to the entire graphene layer, the graphene layer becomes n-type. Similarly, if holes are doped by attaching a substance such as oxygen to the entire graphene layer, the graphene layer becomes p-type. Furthermore, the entire graphene layer is not necessarily made n-type or p-type by doping, but only one of the channel region and the source / drain region may be doped p-type or n-type.

  Further, instead of making the graphene layer n-type or p-type, for example, a back gate may be formed on the back side of the substrate to give a back gate bias. In a graphene element structure, by applying a back gate bias, an energy offset of a Dirac point with respect to Fermi energy is given, so that it can be made n-type or p-type over the entire graphene layer.

  By adopting such a structure, the area of the element can be reduced because the number of gates is less than that of the structure of the first embodiment, so that the manufacturing process can be simplified and the degree of integration can be reduced. Can increase. In addition, this allows only one of the positive and negative polarities of the voltage required for the gate operation, and therefore facilitates circuit design.

  9A and 9B are diagrams for explaining the operation of the transistor according to the third embodiment. FIG. 9A is a diagram illustrating the arrangement of the graphene layer and the gate, and FIG. 9B is a diagram illustrating the band structure in the ON state. c) is a diagram showing a band structure in an off state. Note that 90 to 95 in FIG. 9 correspond to 80 to 85 in FIG. 6.

  First, a case where the entire graphene layer becomes n-type due to a positive voltage back gate bias or the like will be described. At this time, since the Fermi energy is on the higher energy side than the band gap, the transistor is in an on state, and a current flows at a high charge injection rate. In this case, the drain bias is a positive voltage, and as shown in FIG. 9B, a Fermi energy shift 93 due to the drain voltage occurs. Here, by applying a negative voltage to the gate, a Dirac point shift 96 occurs as shown in FIG. As a result, the potential barrier becomes high at the source end of the channel, and hence the thermal excitation leakage current is suppressed. In addition, since the channel has a p-type polarity on the source side and an n-type polarity on the drain side and is partitioned by a band gap 91, the length of the semiconducting region is appropriately selected, so that the band-to-band tunneling can be achieved. Is sufficiently suppressed, and therefore, off-leakage current is suppressed.

  Next, the case where the entire graphene layer becomes p-type due to a negative voltage back gate bias or the like is the same as the case of the positive voltage back gate bias. That is, if no voltage is applied to the gate, the transistor is on, and current flows at a high charge injection rate. In this case, the drain bias is a negative voltage, and an off state of the transistor can be obtained by applying a positive voltage to the gate electrode.

  As described above, according to the present embodiment, although the number of gates is one, the transistor operation can be performed on the same principle as in the first embodiment, and the same effect as in the first embodiment can be obtained. Moreover, since the number of gates is one less than that of the structure of the first embodiment, there is an advantage that the manufacturing process can be simplified and the degree of integration can be increased.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, the number of graphene nanoribbons constituting the channel region is one, but the present invention is not limited to this, and a plurality of graphene nanoribbons may be used.

  The metal catalyst layer that is the base of the graphene layer is not necessarily limited to copper, and any graphene can be used as long as graphene is formed by chemical vapor deposition or the like, and iron, cobalt, nickel, or the like can be used. is there. The method of performing the process for generating the energy band gap on the graphene layer between the gate electrodes is not limited to processing the graphene layer into a ribbon shape, but may be performed by chemical modification or by introducing antidot defects.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 ... Insulating substrate 20, 21, 22 ... Metal catalyst layer 31 ... Contact layer (source)
32 ... Contact layer (drain)
40 ... Graphene layer 51 ... Gate insulating film (source side)
61 ... Gate electrode (source side)
52. Gate insulating film (drain side)
62 ... Gate electrode (drain side)
DESCRIPTION OF SYMBOLS 70 ... Protective film 25 ... Part removed by isotropic etching 45 ... Graphene nanoribbon 80 ... Dirac point 81 ... Energy band gap 82 ... Fermi energy 83 ... Transfer of Fermi energy by drain voltage 84 ... Dirac by electric field of source side gate Movement of point 85 ... Movement of Dirac point due to electric field of drain side gate

Claims (8)

A channel region formed of a graphene layer formed on a substrate and having a predetermined band gap;
A source / drain region formed on each side of the channel region and comprising a graphene layer having a smaller band gap than the channel region;
Two gate electrodes respectively formed on portions of the source / drain regions in contact with the channel region and arranged in parallel with each other so as to cross the channel;
Metal catalyst layers respectively formed on contact portions of the source / drain regions;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the graphene layer in the channel region is formed in a ribbon shape according to a necessary band gap.   The semiconductor device according to claim 1, wherein the graphene layer in the channel region is in a suspended state between the metal catalyst layers.   The semiconductor device according to claim 1, wherein the metal catalyst layer partially overlaps a lower portion of the gate electrode. Forming a metal catalyst layer in an island shape on the substrate;
Forming a graphene layer on the metal catalyst layer;
Forming two gate electrodes parallel to each other on the graphene layer;
Forming a protective film on the graphene layer between the gate electrodes, having a stripe along the facing direction of the gate electrode, and covering the graphene layer outside the gate electrode;
Selectively etching the graphene layer using the protective film and the gate electrode as a mask;
Etching the metal catalyst layer exposed by etching the graphene layer and etching the metal catalyst layer under the graphene layer between the gate electrodes;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the metal catalyst layer is etched by isotropic etching using a chemical solution.   7. The method of manufacturing a semiconductor device according to claim 6, wherein at least a part of the metal catalyst layer under the gate electrode is removed by an etching process of the metal catalyst layer. A channel region formed of a graphene layer formed on a substrate and having a predetermined band gap;
A source / drain region formed on each side of the channel region and comprising a graphene layer having a smaller band gap than the channel region;
A gate electrode disposed across the channel region on a portion of the source / drain region contacting the channel region;
Metal catalyst layers respectively formed on contact portions of the source / drain regions;
Comprising
One of the channel region and the source / drain region has a dopant.

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