CN102969360A - Group III-V semiconductor nanowire array field effect transistor - Google Patents
Group III-V semiconductor nanowire array field effect transistor Download PDFInfo
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- CN102969360A CN102969360A CN2012105454730A CN201210545473A CN102969360A CN 102969360 A CN102969360 A CN 102969360A CN 2012105454730 A CN2012105454730 A CN 2012105454730A CN 201210545473 A CN201210545473 A CN 201210545473A CN 102969360 A CN102969360 A CN 102969360A
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Abstract
The invention discloses a group III-V semiconductor nanowire array field effect transistor, which comprises a monocrystalline substrate layer, a group III-V semiconductor buffer layer formed on the monocrystalline substrate layer, a first ohmic contact layer formed on the group III-V semiconductor buffer layer, a first high-mobility semiconductor channel layer formed on the first ohmic contact layer, a second ohmic contact layer formed on the semiconductor channel layer, a second high-mobility semiconductor channel layer formed on the second ohmic contact layer, a third ohmic contact layer formed on the second high-mobility semiconductor channel layer, a group III-V semiconductor nanowire array formed by selectively etching the first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer in an active region in nano scale, an annular high K medium and work function metal layer formed on the group III-V semiconductor nanowire array, and a gate metal electrode formed on the high K medium and work function metal layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of III-V family conductor nano tube/linear array field-effect transistor.
Background technology
The relative silicon materials of III-V compound semiconductor materials have high carrier mobility, large advantages such as energy gap, and at aspects such as calorifics, optics and electromagnetism good characteristic are arranged.Day by day approach its physics limit in the silicon base CMOS technology after, the III-V compound semiconductor materials might become alternative channel material with its high electron mobility characteristic, is used for making cmos device.In addition, FinFET device and ring grid field effect transistor become the study hotspot of current device architecture with its more superior grid-control function.Because III-V family semiconductor device has many different physics and chemical property from silicon device, in III-V family semiconductor device, various different materials have different selective corrosion, and this is conducive to make the transistor of various different structures.Therefore, need to adopt new device architecture and new making flow process at III-V family semiconductor, to give full play to the material behavior of III-V family semi-conducting material, improve the DC characteristic of MOS device, to satisfy the requirement of high-performance III-V family semiconductor CMOS technology.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention provides a kind of III-V family conductor nano tube/linear array field-effect transistor, when realizing circular nano linear array structure and ring grid field effect transistor device, realize that low source omits living resistance, improve current driving ability and the grid-control function of III-V MOS device, satisfy the application demand of high-performance III-V CMOS technology on digital circuit.
(2) technical scheme
For achieving the above object, the invention provides a kind of III-V family conductor nano tube/linear array field-effect transistor, comprising: single crystalline substrate layer 101; III-V semiconductor buffer layer 102 in these single crystalline substrate layer 101 formation; The first ohmic contact layer 103 in these III-V semiconductor buffer layer 102 formation; The first high mobility semiconductor channel layer 104 in these first ohmic contact layer, 103 formation; The second ohmic contact layer 105 in these the first high mobility semiconductor channel layer 104 formation; The second high mobility semiconductor channel layer 106 in these second ohmic contact layer, 105 formation; The 3rd ohmic contact layer 107 in these the second high mobility semiconductor channel layer 106 formation; Utilize dry method or wet etching to etch the nanoscale active area, utilize selective corrosion and be dry-etched in this nanoscale active area selective corrosion and fall the III-V family conductor nano tube/linear array that the first ohmic contact layer, the second ohmic contact layer and the 3rd ohmic contact layer form; The annular high K dielectric and the workfunction layers 108 that form at this III-V conductor nano tube/linear array; And the grid metal electrode 109 that forms in this high K dielectric and workfunction layers 108.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1, this III-V provided by the invention family conductor nano tube/linear array field-effect transistor all is the structure of ohmic contact layer owing to adopted two-layer up and down at channel layer, omits living resistance so can realize low source; Owing to adopt the selective corrosion characteristic of multilayer III-V semiconductor layer, so can realize the making of Multilayered Nanowires; Because adopt the ALD technology to realize the deposition of ring-shaped gate medium and grid metal at nano wire, thus can realize encircling gate device, thus improve the grid-control ability of device.
2, this III-V provided by the invention family conductor nano tube/linear array field-effect transistor, omit living resistance owing to realized low source, the current driving ability of III-V family semiconductor MOS device and stronger grid-control function have been improved, so satisfied the application demand of high-performance III-V CMOS technology on digital circuit.
Description of drawings
Fig. 1 is the schematic diagram of III-V provided by the invention family semiconductor nanowires field-effect transistor;
Fig. 2 is the schematic diagram according to the III-V family semiconductor nanowires field-effect transistor of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This III-V provided by the invention family semiconductor nanowires field-effect transistor utilizes the selective corrosion characteristic of multilayer III-V semiconductor layer, has realized the making of nano wire; Utilize the ALD technology to realize the deposition of ring-shaped gate medium and grid metal at nano wire; Thereby improve the grid-control ability of device; Reduce the source by channel layer two-layer ohmic contact layer up and down and omit living resistance, improve device drive current, and then improve the DC performance of device.
As shown in Figure 1, Fig. 1 shows the schematic diagram of III-V provided by the invention family semiconductor nanowires field-effect transistor, and this nano-wire field effect transistor comprises: single crystalline substrate layer 101; III-V semiconductor buffer layer 102 in these single crystalline substrate layer 101 formation; The first ohmic contact layer 103 in these III-V semiconductor buffer layer 102 formation; The first high mobility semiconductor channel layer 104 in these first ohmic contact layer, 103 formation; The second ohmic contact layer 105 in these the first high mobility semiconductor channel layer 104 formation; The second high mobility semiconductor channel layer 106 in these second ohmic contact layer, 105 formation; The 3rd ohmic contact layer 107 in these the second high mobility semiconductor channel layer 106 formation; Utilize dry method or wet etching to etch the nanoscale active area, utilize selective corrosion and be dry-etched in this nanoscale active area selective corrosion and fall the III-V family conductor nano tube/linear array that the first ohmic contact layer, the second ohmic contact layer and the 3rd ohmic contact layer form; The annular high K dielectric and the workfunction layers 108 that form at this III-V conductor nano tube/linear array; And the grid metal electrode 109 that forms in this high K dielectric and workfunction layers 108.
Wherein, described single crystalline substrate layer 101 is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
Described III-V semiconductor buffer layer 102 adopts III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises any compound in the group that is made of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and aluminium arsenide AlAs, and the multicomponent alloy that a plurality of compounds form in this group.
Described the first ohmic contact layer 103 and the second ohmic contact layer 105 adopt III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.It is characterized in that realizing low ohmic contact resistance, and and the good selective corrosion of composite channel layer realization.
Described the first high mobility semiconductor channel layer 104 and the second high mobility semiconductor channel layer 106 adopt III-V family layer material, this III-V family layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the composite channel layer that is combined by multiple III-V family's semiconductor and alloy thin layer; It is characterized in that it has high electronics or hole mobility, and can realize good selective corrosion with ohmic contact layer.
The 3rd ohmic contact layer 107 at described top adopts II-V family's layer material or semi-metallic, this III-V family layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer; This semi-metallic comprises the alloy of III-V family semi-conducting material and metal, perhaps the alloy-layer of II-VI family semiconductor, IV family semiconductor and metal.
The dielectric constant k of the high K dielectric in described annular high K dielectric and the workfunction layers 108 is higher than SiO greater than 20
2Dielectric constant k=3.9, the ability that has scaled down with the equivalent oxide thickness that guarantees this annular high K dielectric and workfunction layers 108, the material that this annular high K dielectric and workfunction layers 108 adopt comprises oxide, nitride or nitrogen oxide, and any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.This layer adopts technique for atomic layer deposition to make, and realizes the fully covering to nano-wire array.
Described grid metal electrode 109 comprises and sticks metal level and contact metal layer, wherein sticks metal level and is used for regulating device threshold and in workfunction layers good adhesion is arranged, and contact metal layer is low resistivity metal, such as gold, and aluminium etc.
Fig. 2 is the schematic diagram according to the InP of embodiment of the invention base InP/InAsP/InP nano-wire array field-effect transistor, and the manufacturing process of this InP base InP/InAsP/InP nano-wire array field-effect transistor comprises: at first adopt grow successively on InP (100) substrate 201 In of 100 nanometers of molecular beam epitaxial method (MBE)
0.52Al
0.48The one In of As bottom barrier layer 202,30 nanometers
0.7Ga
0.3The 2nd In of the one InP/InAsP/InP channel layer 204,30 nanometers of As ohmic contact layer 203,20 nanometers
0.7Ga
0.3The 3rd In of the 2nd InP/InAsP/InP channel layer 206,30 nanometers of As ohmic contact layer 205,20 nanometers
0.7Ga
0.3As ohmic contact layer 207; After utilizing photoetching and corrosion technology to produce active area, define grid groove structure, utilize the selective corrosion characteristic of InGaAs and InP material, utilize H at the grid slot part
3PO
4: H
2O
2Be that corrosive liquid erodes an In
0.7Ga
0.3As ohmic contact layer 203, the 2nd In
0.7Ga
0.3As ohmic contact layer 205 and the 3rd In
0.7Ga
0.3As ohmic contact layer 207 is produced nano thread structure, and then substrate is transferred to the AlON of continued growth 1 nanometer in the reaction chamber of plasma enhanced atomic equipment (PE-ALD)
xThe La of Interface Control/3 nanometers
2O
3The TiN work function layer 208 of gate dielectric layer/5 nanometers forms W metal electrode 209 at this high K dielectric and workfunction layers 208 at last.This high mobility III-V family semiconductor MOS interfacial structure by implementing that the present invention realizes satisfies the requirement of high-performance CMOS technology fully.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. an III-V family conductor nano tube/linear array field-effect transistor is characterized in that, comprising:
Single crystalline substrate layer (101);
III-V semiconductor buffer layer (102) in this single crystalline substrate layer (101) formation;
The first ohmic contact layer (103) in this III-V semiconductor buffer layer (102) formation;
The first high mobility semiconductor channel layer (104) in this first ohmic contact layer (103) formation;
The second ohmic contact layer (105) in this first high mobility semiconductor channel layer (104) formation;
The second high mobility semiconductor channel layer (106) in this second ohmic contact layer (105) formation;
The 3rd ohmic contact layer (107) in this second high mobility semiconductor channel layer (106) formation;
Utilize dry method or wet etching to etch the nanoscale active area, utilize selective corrosion and be dry-etched in this nanoscale active area selective corrosion and fall the III-V family conductor nano tube/linear array that the first ohmic contact layer, the second ohmic contact layer and the 3rd ohmic contact layer form;
The annular high K dielectric and the workfunction layers (108) that form at this III-V conductor nano tube/linear array; And
Grid metal electrode (109) in this high K dielectric and workfunction layers (108) formation.
2. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that described single crystalline substrate layer (101) is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
3. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that, described III-V family's semiconductor buffer layer (102) adopts III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises any compound in the group that is made of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and aluminium arsenide AlAs, and the multicomponent alloy that a plurality of compounds form in this group.
4. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that, described the first ohmic contact layer (103) and the second ohmic contact layer (105) adopt III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
5. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that, described the first high mobility semiconductor channel layer (104) and the second high mobility semiconductor channel layer (106) adopt III-V family layer material, this III-V family layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the composite channel layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
6. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that, described the 3rd ohmic contact layer (107) adopts II-V family's layer material or semi-metallic, this III-V family layer material comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer; This semi-metallic comprises the alloy of III-V family semi-conducting material and metal, perhaps the alloy-layer of II-VI family semiconductor, IV family semiconductor and metal.
7. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor is characterized in that the dielectric constant k of the high K dielectric in described annular high K dielectric and the workfunction layers (108) is higher than SiO greater than 20
2Dielectric constant k=3.9, the ability that has scaled down with the equivalent oxide thickness that guarantees this annular high K dielectric and workfunction layers (108), the material that this annular high K dielectric and workfunction layers (108) adopt comprises oxide, nitride or nitrogen oxide, and any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.
8. III-V according to claim 1 family conductor nano tube/linear array field-effect transistor, it is characterized in that, described grid metal electrode (109) comprises and sticks metal level and contact metal layer, wherein stick metal level and be used for regulating device threshold and in workfunction layers good adhesion arranged, contact metal layer is low resistance metal.
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| CN104282559A (en) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor |
| CN105019027A (en) * | 2014-04-23 | 2015-11-04 | 长春理工大学 | Method for preparing GaSb nanowire on GaSb substrate without catalysis by use of molecular beam epitaxy (MBE) |
| CN105870062A (en) * | 2016-06-17 | 2016-08-17 | 中国科学院微电子研究所 | High-quality nanowire CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device, manufacture method thereof and electronic equipment comprising high-quality nanowire CMOS device |
| CN106548944A (en) * | 2015-09-18 | 2017-03-29 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor device |
| CN109989101A (en) * | 2019-04-04 | 2019-07-09 | 西京学院 | A kind of indium antimonide nanowire preparation method |
| CN110648916A (en) * | 2018-06-27 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN111243960A (en) * | 2020-01-20 | 2020-06-05 | 中国科学院上海微系统与信息技术研究所 | Preparation method of semiconductor nanowire and field effect transistor |
| CN113540284A (en) * | 2020-04-17 | 2021-10-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | Aluminum nitride nanosheet array and manufacturing method thereof |
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| CN104282559A (en) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor |
| CN105019027A (en) * | 2014-04-23 | 2015-11-04 | 长春理工大学 | Method for preparing GaSb nanowire on GaSb substrate without catalysis by use of molecular beam epitaxy (MBE) |
| CN105019027B (en) * | 2014-04-23 | 2019-04-30 | 长春理工大学 | The method for preparing GaSb nano wire without catalysis on GaSb substrate with molecular beam epitaxy (MBE) |
| CN106548944A (en) * | 2015-09-18 | 2017-03-29 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor device |
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| CN111243960A (en) * | 2020-01-20 | 2020-06-05 | 中国科学院上海微系统与信息技术研究所 | Preparation method of semiconductor nanowire and field effect transistor |
| CN113540284A (en) * | 2020-04-17 | 2021-10-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | Aluminum nitride nanosheet array and manufacturing method thereof |
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Application publication date: 20130313 |