CN102107852A - Semiconductor nano-structure, manufacturing method and application thereof - Google Patents
Semiconductor nano-structure, manufacturing method and application thereof Download PDFInfo
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- CN102107852A CN102107852A CN2009103121609A CN200910312160A CN102107852A CN 102107852 A CN102107852 A CN 102107852A CN 2009103121609 A CN2009103121609 A CN 2009103121609A CN 200910312160 A CN200910312160 A CN 200910312160A CN 102107852 A CN102107852 A CN 102107852A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 208
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
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- 239000013078 crystal Substances 0.000 claims abstract description 59
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- 229910002601 GaN Inorganic materials 0.000 claims description 7
- 229910005540 GaP Inorganic materials 0.000 claims description 7
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- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 7
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Abstract
The invention relates to a semiconductor nano-structure, a manufacturing method and the application thereof, and belongs to the technical field of semiconductor material preparation. The semiconductor nano-structure comprises a single crystal silicon substrate, a dielectric thin film, a first buffer layer, a semiconductor seed crystal material, a second buffer layer and a semiconductor nano functional area, wherein, the dielectric thin film is formed on the single crystal silicon substrate; a graphical window is formed on the single crystal silicon substrate; the first buffer layer is formed on the single crystal silicon substrate in the graphical window; the semiconductor seed crystal material is formed on the first buffer layer; and the second buffer layer and the semiconductor nano functional area are formed on the dielectric thin film. When the semiconductor nano-structure integrally grows on the silicon substrate, the carrier mobility, the geometrical characteristic and a heterostructure of the semiconductor nano-structure can all satisfy the requirement of a high-performance CMOS (complementary metal oxide semiconductor) technology and the requirement for silicon-based optoelectronic integration.
Description
Technical field
The present invention relates to semiconductor applications, relate in particular to a kind of nanometer semiconductor structure and manufacture method and application thereof.
Background technology
In the past in four more than ten years, the silicon base CMOS technology improves performance by down feature sizes, yet when semiconductor technology evolves behind nanoscale, the silicon integrated circuit technology is approached its technological limit day by day, and the performance that adopts new material and new construction to promote CMOS has become an important directions of continuity Moore's Law.
Aspect new material, adopting the high mobility channel material is the effective ways that improve the transistor saturation drive current, shorten the grid delay time, and can prolong the service life of integrated circuit production line.The room temperature electron mobility of III-V family semi-conducting material approximately is 6-60 a times of silicon, has very excellent electron transport performance; And the III-V family semiconductor that has direct band gap is fit to make photoelectric device very much.For the semi-conductive good characteristic of industrial advantage and III-V family in conjunction with si-substrate integrated circuit, integrated growth III-V family semi-conducting material will be that the integrated ideal of high-performance III-V family semiconductor CMOS technology and silicon based opto-electronics is selected on silicon substrate.Yet, there are lattice constant mismatch, coefficient of thermal expansion mismatch and crystal structure mismatch between silicon substrate and the III-V family semi-conducting material, be difficult to the III-V family semiconductor epitaxial layers of growing high-quality on silicon substrate.Lattice constant mismatch will be introduced a large amount of dislocations and defective in the hetero-epitaxy process; Thermal expansion coefficient difference will cause thermal mismatching, produce thermal stress in the temperature-fall period behind high growth temperature, thereby the defect concentration of epitaxial loayer is increased even crack; The crystal structure mismatch often causes reverse farmland problem.The work of heteroepitaxial growth III-V family semi-conducting material mainly launches around solving these three kinds of mismatch problems on silicon substrate.Method at present relatively more commonly used is to utilize epitaxy technology certain flexible intermediate layer of growing, and the defective that lattice mismatch is produced is confined in the flexible layer, and then the extension graded buffer layer, thereby obtains high-quality III-V family semiconductor epitaxial layers.The III-V family semiconductor lamella that this method needs thicker flexible layer of general several micron and cushion to obtain fabricating low-defect-density, thus extension cost height caused, and also incompatible with the traditional cmos planar technology.Semi-conducting material is a kind of new technology that developed recently gets up in patterned silicon substrate surface heteroepitaxial growth III-V family, limit dislocation by the depth-width ratio (54.7 ° of h/w＞tan) of selecting figure medium window and expand to the semi-conductive upper surface of III-V family, yet as shown in Figure 1, Fig. 1 is prior art III-V family semi-conducting material 104 dislocation expansion and the structural representation that stops during selective area epitaxial growth on having (100) silicon substrate 101 of patterned media 102, its surface always is not parallel to the surface of substrate when selective area epitaxial growth, and near the dislocation 105 [001] crystal orientation that produces because of surface undulation during crystal growth can not effectively be eliminated.In case these dislocations expand to the active area of device, will significantly reduce the yield rate of mobility of charge carrier rate and integrated circuit.
Aspect new device structure, adopt on-plane surface multiple-grid electrode structure can effectively suppress transistorized short channel effect.When being contracted to 20 nanometers along with transistorized grid length, the channel thickness of conventional planar MOS device requires to be reduced to 6 nanometers (grid long 1/3rd) and improves the subthreshold value characteristic of device and the on-off ratio of electric current, yet, adopt the existing integrated circuits manufacturing process to realize that the following ultra-thin raceway groove of 10 nanometers is very difficult.Though adopt the device architecture of novel bigrid (FinFET) or three grids (Tri-Gate) channel thickness can be increased to about 2 times of single gated device, the Fin type structure of these devices is very difficult to make.For example, for the bigrid MOS device (FinFET) that a grid length is 16 nanometers, the width of Fin is 10 nanometers only, and requires depth-width ratio greater than 5 geometric properties, and this has challenge concerning existing photoetching technique and plasma etching technology.And, as shown in Figure 2, Fig. 2 is the structural representation of the semiconductor FinFET of prior art III-V family element manufacturing on the lattice mismatch cushion, the raceway groove 205 of the traditional semiconductor FinFET of III-V family device all is positioned at the top of hetero-epitaxy cushion 206, in the high-temperature process of follow-up semiconductor technology, dislocation extends to channel region easily, and transistor performance is degenerated.
Summary of the invention
The present invention is directed to dislocation that prior art III-V family semi-conducting material produces during selective area epitaxial growth and can expand to the active area of device on the patterned silicon substrate, and significantly reduce the yield rate of mobility of charge carrier rate and integrated circuit, and by the device of its manufacturing in the high-temperature process of follow-up semiconductor technology, dislocation extends to channel region easily, make the deficiency of device performance degeneration, a kind of semiconductor III-V family's nanometer semiconductor structure and manufacture method and application thereof are provided.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of nanometer semiconductor structure comprises monocrystalline substrate, dielectric film, first cushion, semiconductor seed material layer, second cushion and semiconductor nano functional areas; Described dielectric film is formed on the described monocrystalline substrate; Have graphical window on the described monocrystalline substrate, described first cushion is formed on the monocrystalline substrate in the described graphical window, and described semiconductor seed material layer is formed on described first cushion; Described second cushion and semiconductor nano functional areas are formed on the described dielectric film.
Further, described semiconductor seed crystal material, second cushion and semiconductor sacrificial layer are commaterial, and comprise following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
Further, described dielectric film layer comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.
Further, the thickness of described dielectric film is greater than 1.41 times of the graphical window width on the described monocrystalline substrate.
Further, the lattice paprmeter of described first cushion is between described monocrystalline silicon and semiconductor seed crystal material, and it comprises following any one material: SiGe alloy, Ge semiconductor, III-V family semiconductor and their multicomponent alloy.
Further, described nanometer semiconductor structure, it is characterized in that, described semiconductor nano functional areas comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy perhaps comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above as follows: a kind of manufacture method of nanometer semiconductor structure may further comprise the steps:
Step 10: on monocrystalline substrate, form the dielectric film layer;
Step 20:, on monocrystalline substrate, form graphical window by the patterned media thin layer;
Step 30: form first cushion in the graphical window on described monocrystalline substrate;
Step 40: growing semiconductor seed crystal material on described first cushion, and form epitaxial lateral overgrowth outgrowth district;
Step 50: the described epitaxial lateral overgrowth outgrowth of etching district, thus form the semiconductor seed crystal material side direction crystal face vertical with described dielectric film laminar surface;
Step 60: epitaxial growth second cushion on described semiconductor seed crystal material side direction crystal face;
Step 70: selective epitaxial semiconductor nano functional areas and semiconductor sacrificial layer successively on described second cushion;
Step 80: the top of the described semiconductor seed crystal material of planarization, semiconductor nano functional areas and semiconductor sacrificial layer keeps the epitaxial lateral overgrowth part perpendicular to dielectric film;
Step 90: the described semiconductor seed crystal material of wet method selective corrosion, second cushion and semiconductor sacrificial layer form nanometer semiconductor structure on dielectric film.
Further, the chemical attack characteristic of described semiconductor nano functional areas and semiconductor seed crystal material, second cushion, semiconductor sacrificial layer are all inequality, by wet method selective corrosion method semiconductor seed crystal material, second cushion and semiconductor sacrificial layer are removed, and do not damaged the semiconductor nano functional areas.
Further, the method for selective epitaxial comprises described in described step 30, step 40, step 60 and the step 70: metal organic chemical vapor deposition, high vacuum chemical vapour deposition and other chemical vapour deposition techniques.
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above as follows: a kind of device of being made by nanometer semiconductor structure, described nanometer semiconductor structure is applied to the functional part of following device: field-effect transistor, bipolar transistor, resonance tunnel-through diode, Schottky diode, light emitting devices, photo-detector, fiber waveguide, optical modulator, optical coupler and optical switch.
The invention has the beneficial effects as follows: nanometer semiconductor structure of the present invention during integrated growth, makes its carrier mobility, geometric properties and heterojunction structure can both satisfy high-performance CMOS technology and the integrated requirement of silicon based opto-electronics on silicon substrate.
Description of drawings
Fig. 1 is the dislocation expansion and the structural representation that stops during selective area epitaxial growth on the patterned silicon substrate of prior art III-V family semi-conducting material;
Fig. 2 is the structural representation of the semiconductor FinFET of prior art III-V family element manufacturing on the lattice mismatch cushion;
The schematic flow sheet of the manufacture method of the nanometer semiconductor structure that Fig. 3 provides for the embodiment of the invention;
The structural representation of step 20 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 4 provides for the embodiment of the invention;
The structural representation of step 40 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 5 provides for the embodiment of the invention;
The structural representation of step 50 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 6 provides for the embodiment of the invention;
The structural representation of step 70 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 7 provides for the embodiment of the invention;
The structural representation of step 80 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 8 provides for the embodiment of the invention;
The structural representation of step 90 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 9 provides for the embodiment of the invention;
The nanometer semiconductor structure that Figure 10 provides for the embodiment of the invention is applied to the structural representation of FinFET device;
The nanometer semiconductor structure that Figure 11 provides for the embodiment of the invention is applied to the structural representation of RTD device.
The specific embodiment
Below in conjunction with accompanying drawing principle of the present invention and feature are described, institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
The schematic flow sheet of the manufacture method of the nanometer semiconductor structure that Fig. 3 provides for the embodiment of the invention.As shown in Figure 3, manufacture method may further comprise the steps:
Step 10: on monocrystalline substrate 401, form dielectric film layer 402.
The crystalline orientation of monocrystalline substrate can be (100), and crystal plane direction can be＜100 〉.The dielectric film layer comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.At present embodiment, the dielectric film layer is the silicon nitride of high growth temperature.
Step 20:, on monocrystalline substrate 401, form graphical window 403 by patterned media thin layer 402.
The structural representation of step 20 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 4 provides for the embodiment of the invention.As shown in Figure 4, can adopt dry etching technology on monocrystalline substrate 401, to form graphical window, the thickness of dielectric film 402 so just can be limited in misfit dislocation in the graphical window 403 greater than 1.41 times of graphical window 403 width on the monocrystalline substrate 401.
After this step is finished, carry out next procedure again before, adopt and to form the V-type groove in the graphical window 403 of anisotropic wet technology on monocrystalline substrate 401.
Step 30: selective epitaxial first cushion in the graphical window 403 on monocrystalline substrate 401.
The lattice paprmeter of first cushion is between monocrystalline silicon 401 and semiconductor seed crystal material 405, and it comprises following any one material: SiGe alloy, Ge semiconductor, III-V family semiconductor and their multicomponent alloy.
Step 40: selective epitaxial semiconductor seed crystal material 405 on first cushion, and form the living long district 404 of epitaxial lateral overgrowth.
The method of the selective epitaxial of semiconductor seed crystal material 405 comprises: metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapour deposition (UHVCVD) and other chemical vapour deposition techniques (CVD).Semiconductor seed crystal material 405 is proceeded the epitaxial lateral overgrowth outgrowth after filling up graphical window, thereby forms epitaxial lateral overgrowth outgrowth district 404.The top of semiconductor seed crystal material requires to exceed the upper surface of dielectric film layer 402.Because the dislocation that produces in misfit dislocation that monocrystalline substrate produces and the epitaxial process all is limited in the graphical window 403 and the upper area of window, thereby the dislocation density in epitaxial lateral overgrowth outgrowth district 404 is extremely low, even does not have any dislocation.
The structural representation of step 40 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 5 provides for the embodiment of the invention.As shown in Figure 5, semiconductor seed crystal material 405 comprises following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
Step 50: etching epitaxial lateral overgrowth outgrowth district 404, thus form the lateral semiconductor crystal face 406 vertical with the dielectric film laminar surface.
The structural representation of step 50 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 6 provides for the embodiment of the invention.As shown in Figure 6, the surface light at semiconductor seed crystal material 405 carves needed figure.The method of etching can adopt dry etching, also can adopt wet etching.After forming the lateral semiconductor crystal face 406 vertical, adopt wet chemical process that its side direction crystal face 406 is carried out polishing etch with the dielectric film laminar surface.
Step 60: epitaxial growth second cushion 407 on lateral semiconductor crystal face 406.
Step 70: the selective epitaxial first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 successively on second cushion 407.
The structural representation of step 70 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 7 provides for the embodiment of the invention.As shown in Figure 7, in the time of can at least one semiconductor nano functional areas of extension, the material of semiconductor nano functional areas can be germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.When at least two semiconductor nano functional areas of extension, the material of each semiconductor nano functional areas can be identical, also can be inequality.When semiconductor nano functional areas of extension, the semiconductor nano functional areas can also comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.In the present embodiment, the first semiconductor nano functional areas 408 and the second semiconductor nano functional areas 410 comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.Semiconductor sacrificial layer 409 is a commaterial with semiconductor seed crystal material 405, and the function of semiconductor sacrificial layer 409 is to isolate each semiconductor III-V family semiconductor nano functional areas.The semiconductor nano functional areas can be that the high mobility channel material is made the high-performance CMOS device, also can be hetero-junctions or quantum well structure is made opto-electronic device.The thickness of the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 is accurately controlled by growth time.
Step 80: the top of planarization semiconductor seed crystal material 405, the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 keeps the epitaxial lateral overgrowth part perpendicular to dielectric film layer 402.
The method of planarization comprises chemical mechanical polishing method, can realize the planarization on surface, and this planarized surface has determined the thickness of the first semiconductor nano functional areas 408 and the second semiconductor nano functional areas 410 to the distance of the upper surface of dielectric film layer 402.
The structural representation of step 80 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 8 provides for the embodiment of the invention.As shown in Figure 8,
Step 90: wet method selective corrosion semiconductor seed crystal material 405, second cushion 407 and semiconductor sacrificial layer 409 form nanometer semiconductor structure on the dielectric film layer.
The structural representation of step 90 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 9 provides for the embodiment of the invention.As shown in Figure 9, because the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 have different chemical attack characteristics with semiconductor seed crystal material 405, second cushion 407, semiconductor sacrificial layer 409, so semiconductor seed crystal material 405, second cushion 407 and semiconductor sacrificial layer 409 can optionally be removed by chemical etching technology, the corrosion selectivity requires greater than 5.
Semiconductor nano functional areas, second cushion, semiconductor sacrificial layer and semiconductor seed crystal material are the lattice matching relationship, perhaps there is certain lattice mismatch, the lattice mismatch of the lattice mismatch of the lattice mismatch of semiconductor nano functional areas and semiconductor seed crystal material, second cushion and semiconductor seed crystal material, semiconductor sacrificial layer and semiconductor seed crystal material all is lower than ± and 5%.
The manufacture method of nanometer semiconductor structure of the present invention adopts the wrong filtration method of two steps, i.e. the technology that combines with selective epitaxial of graph substrate, the semiconductor seed crystal material of integrated growth utmost point low-dislocation-density on monocrystalline substrate; Utilize advanced epitaxy technology can accurately control the characteristics of semiconductor film layer thickness then, selective epitaxial semiconductor nano functional areas on the side direction crystal face of semiconductor seed crystal material; Use flatening process and semiconductor sacrificial layer technology to form nanometer semiconductor structure then.Be that the present invention utilizes graph substrate constituency epitaxy technology to be terminated in by the dislocation that lattice mismatch causes on the side wall of graphical window, use constituency epitaxial lateral overgrowth technology further to filter dislocation simultaneously, form utmost point low-dislocation-density (＜10
3Cm
-2) the lateral semiconductor crystal face, by in conjunction with epitaxial lateral overgrowth means, flatening process and sacrificial layer technology, the final nanometer semiconductor structure of on silicon substrate, realizing utmost point low-dislocation-density, high mobility, high integration, thus satisfy high-performance semiconductor electronic device and the heterogeneous integrated material requirements of silicon based opto-electronics.
The nanometer semiconductor structure that Figure 10 provides for the embodiment of the invention is applied to the structural representation of FinFET device.As shown in figure 10, the manufacturing process of FinFET device is: at first adopt the SiNx medium 502 of low-pressure chemical vapor deposition method (LPCVD) in Si (100) 501 surperficial high growth temperature one deck 200 nanometers, litho pattern also uses RIE etching SiNx to form the wide window of 100 nanometers, adopts alkaline solution to corrode the V-type groove in window; Put into mocvd growth chamber constituency extension InP seed crystal material (selecting GaAs first cushion) after RCA cleans, outgrowth realizes the epitaxial lateral overgrowth outgrowth then; Litho pattern also adopts RIE etching epitaxial lateral overgrowth outgrowth district to form vertical side direction crystal face, carries out polishing etch then; Put into mocvd growth chamber after thoroughly cleaning and carry out the constituency extension, successively extension 100 nanometer InP second cushion, 20 nanometer N type In
0.7Ga
0.3As raceway groove 503,100 nanometer InP sacrifice layers, 20 nanometer P type GaAs
0.3Sb
0.7Raceway groove 504 and 100 nanometer InP sacrifice layers; Use cmp method (CMP) planarized surface, the height of control channel material is about 120 nanometers, uses hydrochloric acid solution selective corrosion InP sacrifice layer then, forms the In that is symmetrically distributed
0.7Ga
0.3As and GaAs
0.3Sb
0.7Channel array; Adopt conventional CMOS manufacturing process to finish ALD LaAl0 at last
3Gate medium 506, TaN/W grid metal 505, medium side wall, source are leaked and are injected and metallization process.Compare with traditional silicon CMOS technology, silica-based high mobility III-V family its speed of semiconductor CMOS technology that adopts that the present invention makes improves more than 2 times, power consumption reduces an order of magnitude, is that the ideal of back 15 nanometers (post-15nm) CMOS technology is selected.
The nanometer semiconductor structure that Figure 11 provides for the embodiment of the invention is applied to the structural representation of RTD device.As shown in figure 11, the manufacturing process of RTD device is: at first adopt the SiNx medium 602 of low-pressure chemical vapor deposition method (LPCVD) in Si (100) 601 surperficial high growth temperature one deck 200 nanometers, litho pattern also uses RIE etching SiNx to form the wide window of 100 nanometers, adopts alkaline solution to corrode the V-type groove in window; Put into mocvd growth chamber selective epitaxial InP seed crystal material (selecting GaAs first cushion) after RCA cleans, outgrowth realizes epitaxial lateral overgrowth then; Litho pattern also adopts RIE etching epitaxial lateral overgrowth outgrowth district to form vertical side direction crystal face, carries out polishing etch then; Put into mocvd growth chamber after thoroughly cleaning and carry out the constituency extension, successively extension InP second cushion, semiconductor nano functional areas 603 (being AlAs/InGaAs/AlAs double potential barrier RTD heterojunction structure in this example), InGaAs ohmic contact layer 604 and InP sacrifice layer; Use cmp method (CMP) planarized surface, use hydrochloric acid solution selective corrosion InP sacrifice layer then, form the RTD epitaxial structure of horizontal direction; Adopt conventional semiconductor technology to make Ohmic contact 605, mesa etch, dielectric passivation layer 606 at last.By implementing the present invention, can on silicon substrate, realize high performance AlAs/InGaAs/AlAs double potential barrier RTD, by in conjunction with RTD and CMOS technology, will provide a new technology platform for high integration MULTI-VALUED LOGIC CIRCUIT, ultrahigh-speed and low-power-consumption circuit.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a nanometer semiconductor structure is characterized in that, comprises monocrystalline substrate, dielectric film, first cushion, semiconductor seed crystal material, second cushion and semiconductor nano functional areas; Described dielectric film is formed on the described monocrystalline substrate; Have graphical window on the described monocrystalline substrate, described first cushion is formed on the monocrystalline substrate in the described graphical window, and described semiconductor seed material layer is formed on described first cushion; Described second cushion and semiconductor nano functional areas are formed on the described dielectric film.
2. nanometer semiconductor structure according to claim 1, it is characterized in that, described semiconductor seed crystal material, second cushion and semiconductor sacrificial layer are commaterial, and comprise following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
3. nanometer semiconductor structure according to claim 1 is characterized in that, described dielectric film layer comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.
4. nanometer semiconductor structure according to claim 1 is characterized in that, the thickness of described dielectric film is greater than 1.41 times of the graphical window width on the described monocrystalline substrate.
5. nanometer semiconductor structure according to claim 1, it is characterized in that, the lattice paprmeter of described first cushion is between described monocrystalline silicon and semiconductor seed crystal material, and it comprises following any one material: SiGe alloy, Ge semiconductor, III-V family semiconductor and their multicomponent alloy.
6. nanometer semiconductor structure according to claim 1, it is characterized in that, described semiconductor nano functional areas comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy perhaps comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.
7. the manufacture method of a nanometer semiconductor structure is characterized in that, described manufacture method may further comprise the steps:
Step 10: on monocrystalline substrate, form the dielectric film layer;
Step 20:, on monocrystalline substrate, form graphical window by the patterned media thin layer;
Step 30: selective epitaxial first cushion in the graphical window on described monocrystalline substrate;
Step 40: selective epitaxial semiconductor seed crystal material on described first cushion, and form epitaxial lateral overgrowth outgrowth district
Step 50: the described epitaxial lateral overgrowth outgrowth of etching district, thus form the semiconductor seed crystal material side direction crystal face vertical with described dielectric film laminar surface;
Step 60: selective epitaxial second cushion on described semiconductor seed crystal material side direction crystal face;
Step 70: selective epitaxial semiconductor nano functional areas and semiconductor sacrificial layer successively on described second cushion;
Step 80: the top of the described semiconductor seed crystal material of planarization, semiconductor nano functional areas and semiconductor sacrificial layer keeps the epitaxial lateral overgrowth part perpendicular to the dielectric film surface;
Step 90: the described semiconductor seed crystal material of wet method selective corrosion, second cushion and semiconductor sacrificial layer form nanometer semiconductor structure on dielectric film.
8. the manufacture method of nanometer semiconductor structure according to claim 7, it is characterized in that, the chemical attack characteristic of described semiconductor nano functional areas and semiconductor seed crystal material, second cushion, semiconductor sacrificial layer are all inequality, by wet method selective corrosion method semiconductor seed crystal material, second cushion and semiconductor sacrificial layer are removed, and do not damaged the semiconductor nano functional areas.
9. the manufacture method of nanometer semiconductor structure according to claim 7, it is characterized in that the method for selective epitaxial comprises described in described step 30, step 40, step 60 and the step 70: metal organic chemical vapor deposition and high vacuum chemical vapour deposition.
10. device of making by nanometer semiconductor structure, it is characterized in that described nanometer semiconductor structure is applied to the functional part of following device: field-effect transistor, bipolar transistor, resonance tunnel-through diode, Schottky diode, light emitting devices, photo-detector, fiber waveguide, optical modulator, optical coupler and optical switch.
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