CN103022135A - III-V group semiconductor nano-wire field effect transistor device and manufacturing method thereof - Google Patents
III-V group semiconductor nano-wire field effect transistor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an III-V group semiconductor nano-wire transistor device which comprises a single crystal substrate layer, an III-V group semiconductor buffer layer, a bottom ohmic contact layer, an III-V group semiconductor composite channel layer, a top ohmic contact layer, a nano-wire structure, an annular high K gate dielectric layer, a work function metal layer, gate metal electrodes and source drain electrodes. The III-V group semiconductor buffer layer is formed on the single crystal substrate layer, the bottom ohmic contact layer is formed on the III-V group semiconductor buffer layer, the III-V group semiconductor composite channel layer is formed on the bottom ohmic contact layer, the top ohmic contact layer and the nano-wire structure are formed on the III-V group semiconductor composite channel layer, the annular high K gate dielectric layer and the work function metal layer are formed on the nano-wire structure, the gate metal electrodes are formed on the high K gate dielectric layer and the work function metal layer, and the source drain electrodes are formed on the top ohmic contact layer. The invention further discloses a method for manufacturing the nano-wire field effect transistor device. Low source drain parasitic resistance is realized by the nano-wire field effect transistor device, the current drive capacity and stronger gate control functions of the III-V group MOS (metal oxide semiconductor) device are improved, and the application requirement of high-performance III-V CMOS (complementary metal oxide semiconductor) technology on a digital circuit is met.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of III-V family semiconductor nanowires FET device and preparation method thereof.
Background technology
The relative silicon materials of III-V compound semiconductor materials have high carrier mobility, large advantages such as energy gap, and at aspects such as calorifics, optics and electromagnetism good characteristic are arranged.Day by day approach its physics limit in the silicon base CMOS technology after, the III-V compound semiconductor materials might become alternative channel material with its high electron mobility characteristic, is used for making cmos device.In addition, FinFET device and ring grid field effect transistor become the study hotspot of current device architecture with its more superior grid-control function.Because III-V family semiconductor device has many different physics and chemical property from silicon device, in III-V family semiconductor device, various different materials have different selective corrosion, and this is conducive to make the transistor of various different structures.Therefore, need to adopt new device architecture and new making flow process at III-V family semiconductor, to give full play to the material behavior of III-V family semi-conducting material, improve the DC characteristic of MOS device, to satisfy the requirement of high-performance III-V family semiconductor CMOS technology.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention provides a kind of III-V family semiconductor nanowires FET device and preparation method thereof, omit living resistance to realize low source, can realize simultaneously circular nano line structure and ring grid field effect transistor device, improve the current driving ability of III-V family semiconductor MOS device and stronger grid-control function, satisfy the application demand of high-performance III-V CMOS technology on digital circuit.
(2) technical scheme
For achieving the above object, the invention provides a kind of III-V family semiconductor nanowire transistor device, comprising: single crystalline substrate layer 101; III-V family semiconductor buffer layer 102 in these single crystalline substrate layer 101 formation; Bottom ohmic contact layer 103 in these III-V family semiconductor buffer layer 102 formation; III-V family semiconductor composite channel layer 104 in these bottom ohmic contact layer 103 formation; Top ohmic contact layer 105 and nano thread structure in these III-V family semiconductor composite channel layer 104 formation; The annular high-K gate dielectric layer and the workfunction layers 106 that form at this nano thread structure; Grid metal electrode 107 in this high K dielectric layer and workfunction layers 106 formation; And the source-drain electrode 108 that forms at this top ohmic contact layer 105.
In the such scheme, described single crystalline substrate layer 101 is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
In the such scheme, described III-V semiconductor buffer layer 102 adopts III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises any compound in the group that is made of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and aluminium arsenide AlAs, and the multicomponent alloy that a plurality of compounds form in this group.
In the such scheme, described bottom ohmic contact layer 103 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
In the such scheme, described III-V family semiconductor composite channel layer 104 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the composite channel layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
In the such scheme, described top ohmic contact layer 105 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
In the such scheme, the dielectric constant k of the high K dielectric in described annular high-K gate dielectric layer and the workfunction layers 106 is higher than SiO greater than 20
2Dielectric constant k=3.9, the ability that has scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer 106, the material that this high-K gate dielectric layer 106 adopts comprises oxide, nitride or nitrogen oxide, and any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.
In the such scheme, the workfunction layers in described annular high-K gate dielectric layer and the workfunction layers 106, work function is adjustable, is used for regulating the threshold voltage of device, and the material that this work function once adopted comprises nitride and metal.
In the such scheme, described grid metal electrode 107 comprises workfunction layers and contact metal layer, and wherein workfunction layers is used for regulating device threshold, and contact metal layer is low resistance metal.
In the such scheme, it is single-layer metal or multiple layer metal that metal electrode 108 is leaked in described source, at alloy or not in the situation of alloy, forms good ohmic contact with ohmic contact layer.
For achieving the above object, the present invention also provides the method for a kind of III-V of making family semiconductor nanowires FET device, comprising: step 1: select a single crystalline substrate layer 101; Step 2: form III-V family semiconductor buffer layer 102 at this single crystalline substrate layer 101; Step 3: form bottom ohmic contact layer 103 at III-V family semiconductor layer 102; Step 4: form III-V family semiconductor composite channel layer 104 at ohmic contact layer 103; Step 5: form top ohmic contact layer 105 at III-V family semiconductor composite channel layer 104; Step 6: the epitaxial wafer after forming top ohmic contact layer 105 adopts the method for etching to be formed with the source region; Step 7: form grid groove figure at active area, and adopt wet etching to go out the nano wire transistor arrangement; Step 8: on the nano-wire transistor structure, form annular high-K gate dielectric and gate work function metal level 106; Step 9: on high-K gate dielectric and gate work function metal electrode 106, form grid metal electrode 107; Step 10: this workfunction layers and high K dielectric layer take grid metal electrode 107 as mask etching, expose ohmic contact layer 105; Step 11: metal electrode 108 is leaked in the formation source on the ohmic contact layer 105 that exposes.
In the such scheme, described at single crystalline substrate layer 101 formation III-V family semiconductor buffer layer 102, be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
In the such scheme, described at III-V family semiconductor buffer layer 102 formation bottom ohmic contact layers 103, be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
In the such scheme, described at bottom ohmic contact layer 103 formation III-V family semiconductor composite channel layers 104, be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
In the such scheme, described at III-V family semiconductor composite channel layer 104 formation top ohmic contact layer 105, be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
In the such scheme, described epitaxial wafer after forming top ohmic contact layer 105 adopts the method for etching to be formed with the source region, is to adopt dry etching, wet etching, and perhaps the method that combines with wet etching of dry etching realizes.
In the such scheme, described employing wet etching goes out the nano wire transistor arrangement, is to adopt dry etching, wet etching, and perhaps the method that combines with wet etching of dry etching realizes.
In the such scheme, described high-K gate dielectric layer and workfunction layers 106 in nano-wire transistor structure formation annular are to adopt ald or molecular beam epitaxy to realize.
In the such scheme, the described grid metal electrode 107 that forms on high-K gate dielectric and gate work function metal electrode 106 is to adopt optical lithography or electron beam exposure, electron beam evaporation and dry etching technology to realize.
In the such scheme, described take grid metal electrode 107 as mask etching this high-K gate dielectric and workfunction layers 106, adopt dry etching and wet etching to realize.
In the such scheme, described on the ohmic contact layer 105 that exposes the formation source leak metal electrode 108, be to adopt the method for optical lithography, electron beam evaporation and lift-off technology to realize.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1, this III-V provided by the invention family semiconductor nanowires FET device and preparation method thereof, owing to utilize the selective corrosion characteristic (such as the selective corrosion of InGaAs and InP) of multilayer III-V semiconductor layer, and the nanoscale active area that etches, so can realize the making of nano wire; Because the present invention adopts the ALD technology in the deposition of nano wire realization ring-shaped gate medium and grid metal, so can realize the annular transistor device; Because the raceway groove of device is all at nanoscale, and employing ring-shaped gate medium and grid metal, so can improve the grid-control ability of device; Because this device material structure adopts at channel layer two-layer ohmic contact layer up and down, omits living resistance so can reduce the source, improves device drive current, and then improve the DC performance of device.
2, this III-V provided by the invention family semiconductor nanowires FET device and preparation method thereof, omit living resistance owing to can realize low source, and improved the current driving ability of III-V family semiconductor MOS device, realized stronger grid-control function by the annular gate device structure, so can satisfy the application demand of high-performance III-V CMOS technology on digital circuit.
Description of drawings
Fig. 1 is the structural representation according to the III-V family semiconductor nanowires FET device of the embodiment of the invention;
Fig. 2 is the method flow diagram of making III-V family semiconductor nanowires FET device according to the embodiment of the invention;
Fig. 3-1 makes the process chart of III-V family semiconductor nanowires FET device to Fig. 3-the 10th according to the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This III-V provided by the invention family semiconductor nanowires FET device and preparation method thereof is the selective corrosion characteristic of utilizing multilayer III-V semiconductor layer, realizes the making of nano wire; Utilize the ALD technology to realize the deposition of ring-shaped gate medium and grid metal at nano wire; Thereby improve the grid-control ability of device; Reduce the source by channel layer two-layer ohmic contact layer up and down and omit living resistance, improve device drive current, and then improve the DC performance of device.
As shown in Figure 1, Fig. 1 shows the structural representation according to the III-V family semiconductor nanowires FET device of the embodiment of the invention, and this nano-wire field effect transistor structure comprises: single crystalline substrate layer 101; III-V family semiconductor buffer layer 102 in these single crystalline substrate layer 101 formation; Bottom ohmic contact layer 103 in these III-V family semiconductor buffer layer 102 formation; III-V family semiconductor composite channel layer 104 in these bottom ohmic contact layer 103 formation; Top ohmic contact layer 105 and nano thread structure in these III-V family semiconductor composite channel layer 104 formation; The annular high-K gate dielectric layer and the workfunction layers 106 that form at this nano thread structure; Grid metal electrode 107 in this high K dielectric layer and workfunction layers 106 formation; And the source-drain electrode 108 that forms at this top ohmic contact layer 105.
Described single crystalline substrate layer 101 is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
Described III-V semiconductor buffer layer 102 adopts III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises any compound in the group that is made of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and aluminium arsenide AlAs, and the multicomponent alloy that a plurality of compounds form in this group.
Described bottom ohmic contact layer 103 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
Described III-V family semiconductor composite channel layer 104 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the composite channel layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
Described top ohmic contact layer 105 comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
The dielectric constant k of the high K dielectric in described annular high-K gate dielectric layer and the workfunction layers 106 is higher than SiO greater than 20
2Dielectric constant k=3.9, the ability that has scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer 106, the material that this high-K gate dielectric layer 106 adopts comprises oxide, nitride or nitrogen oxide, and any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.
Workfunction layers in described annular high-K gate dielectric layer and the workfunction layers 106, its work function is adjustable, is used for regulating the threshold voltage of device, the material that this work function layer adopts comprises nitride TaN, the conductive materials such as TiN also can adopt the tungsten W of metal such as ALD, aluminium Al etc.
Described grid metal electrode 107 comprises workfunction layers and contact metal layer, and wherein workfunction layers be used for to be regulated device threshold, metal nickel for example, platinum Pt etc.; Contact metal layer is low resistance metal, such as aluminium Al, and tungsten W, copper Cu etc., its resistivity is less than 1 * 10
-8Ω m.
It is single-layer metal (such as tungsten W) or multiple layer metal (such as Ti/Pt/Au, NiGeAu etc.) that metal electrode 108 is leaked in described source, at alloy or not in the situation of alloy, forms good ohmic contact with ohmic contact layer.
Based on the schematic diagram of III-V family semiconductor nanowires field-effect transistor shown in Figure 1, Fig. 2 shows the method flow diagram according to the making III-V family semiconductor nanowires field-effect transistor of the embodiment of the invention, and the method comprises:
Step 1: select a single crystalline substrate layer 101;
Step 2: form III-V semiconductor buffer layer 102 at this single crystalline substrate layer 101;
Step 3: form bottom ohmic contact layer 103 at III-V semiconductor layer 102;
Step 4: high mobility channel layer 104 on ohmic contact layer 103;
Step 5: the top ohmic contact layer 105 that forms on the high mobility channel layer 104;
Step 6: the epitaxial wafer after forming top ohmic contact layer 105 adopts the method for etching to be formed with the source region;
Step 7: form grid groove figure at active area, and adopt wet etching to go out the nano wire transistor arrangement;
Step 8: on the nano-wire transistor structure, form annular high-K gate dielectric and gate work function metal level 106;
Step 9: on high-K gate dielectric and gate work function metal electrode 106, form grid metal electrode 107;
Step 10: this workfunction layers and high K dielectric layer take grid metal electrode 107 as mask etching, expose ohmic contact layer 105;
Step 11: metal electrode 108 is leaked in the formation source on the ohmic contact layer 105 that exposes.
Wherein, step 2 all adopts the method epitaxial growth of molecular beam epitaxy or MOCVD to obtain to step 5; Epitaxial wafer in the step 6 after forming top ohmic contact layer 105 adopts the method for etching to be formed with the source region, and lithographic method can be dry etching, wet etching, perhaps both methods of combining; Adopting wet etching to go out the nano wire transistor arrangement at active area in the step 7, is the selective corrosion characteristic of utilizing ohmic contact layer and high mobility channel layer, adopts the method for wet etching to obtain; Forming annular high-K gate dielectric and gate work function metal level 106 in the step 8 on the nano-wire transistor structure, is to adopt ald or molecular beam epitaxy to realize; Forming grid metal electrode 107 in the step 9 on high-K gate dielectric and gate work function metal electrode 106 is to adopt optical lithography or electron beam exposure, electron beam evaporation and dry etching technology to realize; In the step 10 take grid metal electrode 107 as mask etching this workfunction layers and high K dielectric layer, expose ohmic contact layer 105, mainly adopt dry etching, realize such as methods such as reactive ion etching, ICP; In the step 11 on the ohmic contact layer 105 that exposes the formation source leak metal electrode 108, be to adopt optical lithography or electron beam exposure, electron beam evaporation, the method for peeling off realize.
Based on nano-wire field effect transistor structure illustrated in figures 1 and 2 and preparation method thereof, Fig. 3-1 shows process chart according to the making III-V nano-wire field effect transistor of the embodiment of the invention to Fig. 3-9, specifically comprises:
Shown in Fig. 3-1, select a monocrystalline InP substrate 301, adopt the method heteroepitaxial growth InAlAs semiconductor layer 302 of molecular beam epitaxy in this single crystalline substrate 301;
Shown in Fig. 3-2, adopt the highly doped InGaAs bottom ohmic contact layer 303 of method heteroepitaxial growth of molecular beam epitaxy at InAlAs semiconductor buffer layer 302;
Shown in Fig. 3-3, adopt the method heteroepitaxial growth InP/InAsP/InP high mobility composite channel layer 304 of molecular beam epitaxy at highly doped InGaAs ohmic contact layer 303;
As shown in Figure 3-4, adopt the highly doped InGaAs top layer ohmic contact layer 305 of method heteroepitaxial growth of molecular beam epitaxy at InP/InAsP/InP high mobility composite channel layer 304;
Shown in Fig. 3-5, use photoetching process definition active area, adopt dry etching, be etched with source region epitaxial material in addition, etch into following 50 nanometers of InAlAs resilient coating to 300 nanometers;
Shown in Fig. 3-6, use photoetching process to define the grid groove at active area, adopt the method for wet etching, thereby top InGaAs ohmic contact layer and bottom InGaAs ohmic contact layer form InP/InAsP/InP high mobility composite channel layer at the grid slot part nano thread structure is fallen in selective corrosion;
Shown in Fig. 3-7, on the nano-wire transistor structure, adopt the method for ald to form annular high-K gate dielectric and gate work function metal level 306 at the nano wire of InP/InAsP/InP high mobility composite channel layer;
Shown in Fig. 3-8, on high-K gate dielectric and gate work function metal electrode 306, form grid metal electrode 307;
Shown in Fig. 3-9, this workfunction layers and high K dielectric layer expose ohmic contact layer 305 take grid metal electrode 307 as mask etching;
Shown in Fig. 3-10, metal electrode 308 is leaked in the formation source on the ohmic contact layer 305 that exposes.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (21)
1. an III-V family semiconductor nanowire transistor device is characterized in that, comprising:
Single crystalline substrate layer (101);
III-V family semiconductor buffer layer (102) in this single crystalline substrate layer (101) formation;
Bottom ohmic contact layer (103) in this III-V family semiconductor buffer layer (102) formation;
III-V family semiconductor composite channel layer (104) in this bottom ohmic contact layer (103) formation;
Top ohmic contact layer (105) and nano thread structure in this III-V family semiconductor composite channel layer (104) formation;
The annular high-K gate dielectric layer and the workfunction layers (106) that form at this nano thread structure;
Grid metal electrode (107) in this high K dielectric layer and workfunction layers (106) formation; And
Source-drain electrode (108) in this top ohmic contact layer (105) formation.
2. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that described single crystalline substrate layer (101) is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
3. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, described III-V semiconductor buffer layer (102) adopts III-V family semiconductor film layer material, this III-V family semiconductor film layer material comprises any compound in the group that is made of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and aluminium arsenide AlAs, and the multicomponent alloy that a plurality of compounds form in this group.
4. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, described bottom ohmic contact layer (103) comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
5. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, described III-V family's semiconductor composite channel layer (104) comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the composite channel layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
6. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, described top ohmic contact layer (105) comprises the semi-conductive multicomponent alloy of a kind of III-V family's semiconductor or multiple III-V family, perhaps comprises the high doping semiconductor thin layer that is combined by multiple III-V family's semiconductor and alloy thin layer.
7. III-V according to claim 1 family semiconductor nanowire transistor device is characterized in that the dielectric constant k of the high K dielectric in described annular high-K gate dielectric layer and the workfunction layers (106) is higher than SiO greater than 20
2Dielectric constant k=3.9, the ability that has scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer (106), the material that this high-K gate dielectric layer (106) adopts comprises oxide, nitride or nitrogen oxide, and any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.
8. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, workfunction layers in described annular high-K gate dielectric layer and the workfunction layers (106), work function is adjustable, be used for regulating the threshold voltage of device, the material that this work function once adopted comprises nitride and metal.
9. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, described grid metal electrode (107) comprises workfunction layers and contact metal layer, and wherein workfunction layers is used for regulating device threshold, and contact metal layer is low resistance metal.
10. III-V according to claim 1 family semiconductor nanowire transistor device, it is characterized in that, it is single-layer metal or multiple layer metal that metal electrode (108) is leaked in described source, at alloy or not in the situation of alloy, forms good ohmic contact with ohmic contact layer.
11. the method for a making III-V claimed in claim 1 family semiconductor nanowires FET device is characterized in that, comprising:
Step 1: select a single crystalline substrate layer (101);
Step 2: form III-V family's semiconductor buffer layer (102) at this single crystalline substrate layer (101);
Step 3: form bottom ohmic contact layer (103) at III-V family semiconductor layer (102);
Step 4: form III-V family's semiconductor composite channel layer (104) at ohmic contact layer (103);
Step 5: form top ohmic contact layer (105) at III-V family semiconductor composite channel layer (104);
Step 6: the epitaxial wafer after forming top ohmic contact layer (105) adopts the method for etching to be formed with the source region;
Step 7: form grid groove figure at active area, and adopt wet etching to go out the nano wire transistor arrangement;
Step 8: on the nano-wire transistor structure, form annular high-K gate dielectric and gate work function metal level (106);
Step 9: on high-K gate dielectric and gate work function metal electrode (106), form grid metal electrodes (107);
Step 10: take grid metal electrode (107) as this workfunction layers of mask etching and high K dielectric layer, expose ohmic contact layer (105);
Step 11: leak metal electrode (108) in the upper formation source of the ohmic contact layer that exposes (105).
12. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described at single crystalline substrate layer (101) formation III-V family's semiconductor buffer layer (102), be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
13. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described at III-V family semiconductor buffer layer (102) formation bottom ohmic contact layer (103), be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
14. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described at bottom ohmic contact layer (103) formation III-V family's semiconductor composite channel layer (104), be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
15. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described at III-V family semiconductor composite channel layer (104) formation top ohmic contact layer (105), be to adopt molecular beam epitaxy or the epitaxially grown method of MOCVD to realize.
16. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described epitaxial wafer after forming top ohmic contact layer (105) adopts the method for etching to be formed with the source region, be to adopt dry etching, wet etching, perhaps the method that combines with wet etching of dry etching realizes.
17. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described employing wet etching goes out the nano wire transistor arrangement, be to adopt dry etching, wet etching, perhaps the method that combines with wet etching of dry etching realizes.
18. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described high-K gate dielectric layer and workfunction layers (106) in nano-wire transistor structure formation annular are to adopt ald or molecular beam epitaxy to realize.
19. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, the described grid metal electrodes (107) that form on high-K gate dielectric and gate work function metal electrode (106) are to adopt optical lithography or electron beam exposure, electron beam evaporation and dry etching technology to realize.
20. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, described take grid metal electrode (107) as this high-K gate dielectric of mask etching with workfunction layers (106), adopt dry etching and wet etching to realize.
21. method of making III-V family semiconductor nanowires FET device according to claim 11, it is characterized in that, metal electrode (108) is leaked in the upper formation source of described ohmic contact layer (105) exposing, and is to adopt the method for optical lithography, electron beam evaporation and lift-off technology to realize.
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