201230327 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種非平面鍺量子井裝置。 【先前技術】 在磊晶生長半導體異質結構中且通常爲ΠΙ-ν族或矽-鍺/鍺（SiGe/Ge )材料體系中形成之量子井電晶體裝置 ，由於低有效質量而提供了電晶體通道中之非常高的載子 遷移率（carrier mobility )，且由於 D e 11 a 型慘雜（d e 11 a doping)而提供了較低的雜質散射（impurity scattering) 。此外，這些裝置提供了非常高的驅動電流性能。然而， 因爲係在磊晶生長的異質結構中形成量子井電晶體，所以 所形成的結構包含數個垂直的磊晶層，而只容許形成平面 類型的量子井裝置》 【發明內容】 本發明揭示了形成非平面鍺量子井結構之技術。尤其 可以IV族或III-V族半導體材料實施該量子井結構，且該量 子井結構包含一鍺鰭結構。在一例子中，提供了一種非平 面量子井裝置，該量子井裝置包含一量子井結構，該量子 井結構具有一基材（例如，矽上覆矽鍺（SiGe)或砷化鎵 (GaAs )緩衝層）、一IV族或III-V族材料阻障層（例如 ，矽鍺（SiGe )、砷化鎵（GaAs )、或砷化鋁鎵（ AlGaAs )、一摻雜層（例如’被Delta型摻雜/調變摻雜 -5- 201230327 的層）、以及一未被摻雜的鍺量子井層。在該量子井結構 中形成一未被摻雜的鍺鰭結構，且在該鰭結構之上沈積一 上阻障層。可在該鰭結構上沈積一閘極金屬。可在該鰭結 構的各別末端上形成汲極/源極區。 【實施方式】 本發明揭示了形成非平面鍺量子井結構之技術。尤其 可以IV族或III-V族半導體材料實施該量子井結構，且該量 子井結構包含一鍺鰭結構，因而有效地提供了一種混合式 結構。可將該技術用來諸如改善調變摻雜/ Delta型摻雜的 非平面裝置中之短通道效應以及閘極長度（Lg)可擴展性 (scalability)。實現了基於鰭的裝置之靜電效益，且同 時保留了調變摻雜/ Delta型摻雜裝置的高遷移率效益。 槪述 如前文所述，在磊晶生長半導體異質結構中且通常爲 ΠΙ-V族材料體系中形成之量子井電晶體裝置由於低有效質 量而提供了電晶體通道中之非常高的載子遷移率，且由於 Delta型摻雜而提供了較低的雜質散射。這些傳統的裝置提 供了非常高的驅動電流性能。通常以平面架構製造此類量 子井體系。 可將諸如鰭式場效電晶體（FinFET )結構（例如，雙 閘極、三閘極、或環繞閘（surround gate )結構）等的非 平面電晶體架構用來改善靜電及短通道效應，且因而能夠 -6- 201230327 有閘極長度（Lg )可擴展性。然而，此種非平面架構通常 被認爲與在晶晶生長異質結構中形成之高品質且高遷移率 之摻雜量子井電晶體不相容。 因此’根據本發明的一實施例，提供了 一種調變摻雜 非平面鍺量子井電晶體裝置。可自諸如鍺、矽鍺（SiGe) 、矽、及/或砷化鎵（GaAs )、砷化鋁（AlAs )等的半導 體異質結構形成該裝置。以IV族或III-V族材料製造的任何 數目之磊晶生長異質結構可被配置成具有一基於鍺鰭之通 道。該裝置可包含諸如在一較大能帶間隙（band gap )的 材料中之Delta型摻雜，該Delta型摻雜以調變摻雜之方式 摻雜了一較低能帶間隙的材料。在該較大能帶間隙材料及 Delta型摻雜之後，以磊晶方式生長該較低能帶間隙的材料 。可在該異質結構中產生圖案，也將該異質結構蝕刻成一 或多個窄鰭，且那些鰭中之Delta型摻雜/調變摻雜的較低 能帶間隙材料構成了該裝置的主動區本體。 例如，可以與製造其中包括淺溝槽隔離（Shallow Trench Isolation ;簡稱STI )'閘極堆疊、源極/汲極區 、及接觸點形成之傳統基於矽的非平面裝置時使用的方式 類似之方式執行製造該裝置之流程。然而，與裝置的主動 區本體中含有高摻雜程度的傳統非平面裝置對照之下，鍺 鰭結構的主動區本體不包含摻雜劑（這是因爲以調變摻雜 / Delta型摻雜之方式摻雜該裝置），因而由於較佳的庫侖 散射（Coulomb scattering)而提供給對載子遷移率之顯著 增強。 201230327 該非平面不摻雜之基於鍺鰭的裝置通常呈現比在半導 體異質結構中形成的傳統調變摻雜平面量子井裝置較佳之 其中包括顯著的閘極長度（Lg)及臨界電壓（Vt)可擴展 性之改進的裝置靜電特性。根據本發明之揭示，將可易於 了解其他的優點。例如，根據本發明的一實施例而配置的 —III_V族/鍺混合式體系之一優點在於：可將（阻障層中 之）III-V族材料與（鰭結構中之）鍺間之蝕刻選擇性用於 淺溝槽隔離（STI )製程，在該製程中，只對鍺/ III-V族 界面進行STI蝕刻。 因此，考慮一所需的鍺量子井結構時，可根據本發明 的一實施例而形成一鰭結構（以及閘極、源極/汲極區、 及接點等的結構）。因而根據一實施例，一調變摻雜非平 面鍺量子井電晶體裝置之形成通常可包括在形成鍺鰭結構 之前的下方量子井結構（或該量子井結構之任何部分）之 生長》—替代II施例假定：係預先形成該量子井結構，然 後在該量子井結構中形成該鍺鰭結構。 量子井結構 第1圖是於製造根據本發明的一實施例的一非平面鍺 量子井裝置時可被使用的一例示鍺量子井生長結構之一橫 斷面側視圖。該量子井生長結構可以是諸如具有一覆蓋層 (capping layer)之一傳統的矽鍺/鍺或砷化鎵/鍺量子 井結構。然而’如前文所述’請注意：如根據本發明的揭 示而將可了解的’可以被配Η成具有各種1V族或11 族材 201230327 料、摻雜層、及緩衝層之任何數目的量子井生長結構，實 施根據本發明的一實施例而形成的一調變摻雜/ Delta型摻 雜非平面鍺量子井電晶體裝置。在申請專利範圍中述及的 本發明將不限於任何特定的量子井生長構型。 如第1圖所示，該量子井生長結構包含一基材，在該 基材之上形成了一些成核（nucl eat ion )及緩衝層。該結 構進一步包含一 IV族或III-V族材料阻障層，而在該阻障層 之上形成了一摻雜層，且在該摻雜層之上形成了 一間隔層 ’且在該間隔層之上形成了鍺量子井層。在該鍺量子井層 上提供了一覆蓋層。下文中將依次說明這些例示層中之每 一層。其他實施例可包含較少的層（例如，較少的緩衝層 及/或沒有覆蓋層）、或較多的層（例如，在量子井層之 下之額外的間隔層及/或摻雜層）、或不同的層（例如， 以不同的半導體材料、配方、及/或摻雜劑形成的層）。 可使用已確立的半導體製程（例如，金屬有機化學氣相沈 積、分子束磊晶、微影、或其他此類適當的製程）而以任 何適當的層厚度及其他所需的層參數實施該等層，且該等 層可以是漸變的（graded )(例如，線性或步階之方式） ’以便改善具有不同晶格的材料的鄰近層間之晶格常數匹 配。一般而言’該等特定層及結構的尺寸將取決於諸如所 需裝置性能、工廠能力、及所用半導體材料等的因素。 可以典型的方式實施該基材，且本發明可使用任何數 目的適當基材類型及材料（例如，p型、η型、中性型、矽 、鍺、高或低電阻係數、偏移切割（0ff-cut )或非偏移切 -9 - 201230327 割、基體（bulk )、或絕緣層上覆矽（silicon-on-insulator) 等 的類型 及材料 ） 。 在一實 施例中 ，該 基材是 一基體矽基材。在另一實施例中，該基材是一基體鍺基材 。其他實施例可使用諸如絕緣層上覆矽（SOI )、或絕緣 層上覆鍺（Germanium On Insulator;簡稱 GeOI)、或絕 緣層上覆砂鍺（SiGe On Insulator;簡稱SiGeOI)等的絕 緣層上覆半導體結構。 在該基材上形成成核及緩衝層，且亦可以典型的方式 實施該等成核及緩衝層。在一特定實施例中，係由矽鍺（ SiGe )(例如，60%的鍺）或砷化鎵（GaAs )製成該成核 及緩衝層，且該成核及緩衝層具有大約0.5至2.0微米之總 體厚度（例如，厚度大約爲25奈米至50奈米之成核層、以 及厚度大約爲0.3微米至1.9微米之緩衝層）。如所習知的 ，可將該成核及緩衝層用來以諸如砷化鎵（GaAs )材料等 的III-V族材料之雙原子層（atomic bi-layer)塡滿最低基 材平台。可將該成核層用來產生一反相無晶域（anaphase domain-free ) 虛擬極 性基材 （ virtual polar substrate)，且可將該緩衝層用來提供位錯過濾緩衝結構 (dislocation filtering buffer)，而該位錯過濾緩衝結構 可提供量子井結構之壓縮應變（compressive strain) ’且 /或可提供對該基材與該阻障層間之晶格失配（lattice mismatch)的控制。該等緩衝層亦可包含漸變緩衝層，且 亦可以傳統的方式實施該漸變緩衝層。如所習知的’藉由 形成該漸變緩衝層，位錯可沿著其間較爲對角線的平面滑 -10 - 201230327 動，因而有效地控制了該基材與該IV族/ 11 族材料阻障 層（及/或任何中間層）間之晶格失配。將可了解的’可 將此類漸變層用於該量子井結構或堆疊之其他位置。請注 意，可以在沒有該成核及/或緩衝層的情形下實施可受益 於本發明的實施例之其他量子井結構。例如’可以在沒有 漸變緩衝層的情形下實施具有以晶格常數充分類似的材料 實施的基材及阻障層之實施例。 在該實施例中，在該成核及緩衝層上形成該IV族/ III-V族阻障層，且亦可以傳統的方式實施該IV族/ III-V 族阻障層。在一特定實施例中，係以Si ,-xGex (其中X是在 諸如60的4〇至80之範圍內）、或砷化鎵（GaAs)、或A1,· xGax As (其中X是在諸如70的50至90之範圍內）實施該阻 障層，且該阻障層具有在4奈米至120奈米的範圍內（例如 ，1〇〇奈米±20奈米）之厚度。一般而言，係由具有比形成 上方量子井層的材料的能帶間隙高的一能帶間隙之一材料 形成該阻障層’且該阻障層有足以提供電晶體通道中之電 荷載子的一位能障（potential barrier)之厚度。如將可了 解的，該阻障層的實際構造及厚度將取決於諸如基材及量 子井層材料及/或厚度等的因素。如根據本發明的揭示而 將可了解的’本發明中可使用許多此類阻障材料及結構。 在該例示量子井生長結構中，在該阻障層上（或內） 形成該摻雜層’且亦可以傳統的方式實施該摻雜層。一般 而言，可以該摻雜層摻雜該阻障層，以便將載子供應到該 量子井層。可以諸如Delta型摻雜（或調變摻雜）之方式摻 -11 - 201230327 雜該摻雜層。對於利用一矽鍺（S i G e )材料阻障層之一n 型裝置而言，可使用諸如硼及/或碲雜質而實施該摻雜， 且對於P型裝置而言，可使用諸如鈹（Be)及/或碳而實 施該摻雜。該摻雜層之厚度將取決於諸如摻雜的類型及所 用的材料等的因素。例如，在一實施例中，該摻雜層是具 有大約3埃至15埃間之厚度之一硼Delta型摻雜3丨4()〇^0層 。在另一實施例中，該摻雜層是具有大約15埃至60埃間之 厚度之一鈹（Be)調變摻雜砷化鎵（GaAs)層。可根據諸 如適用於鍺量子井層的通道之片載子濃度（sheet carrier concentration )而選擇摻雜。如根據本發明的揭示而將可 了解的，可以具有任何類型的一或多個適用摻雜層之量子 井結構實施本發明之一實施例。 在該摻雜層上（或之上）形成該間隔層，且亦可以傳 統的方式實施該間隔層。在一特定實施例中，係以 Sii.xGex (其中X是在諸如60的40至80之範圍內）、或砷化 鎵（GaAs)、或Ah.xGaxAs (其中X是在諸如70的50至90 之範圍內）實施該間隔層，且該間隔層具有在0.2奈米至 70奈米的範圍內（例如，5奈米）之厚度。一般而言，該 間隔層可被配置成將壓縮應變提供給該量子井層，這是因 爲該量子井層被用來作爲一半導體通道。請注意，可以在 沒有該間隔層的情形下實施可受益於本發明的實施例之其 他量子井結構。 亦可以傳統的方式實施該量子井層。一般而言，係以 具有大約20埃至5 00埃的例示厚度之未被摻雜的鍺實施該 -12- 201230327 量子井層。將可了解的，本發明中可使用許多其他的量子 井層結構。更一般性而言’該量子井層具有比1▽族/111^ 族阻障層的能帶間隙小的一能帶間隙’且該量子井層是未 被摻雜的，而且該量子井層具有足以針對記憶單元或邏輯 電路的電晶體等的特定應用而提供適當的通道傳導性之厚 度。該阻障層、一上阻障層、或以上兩阻障層可對該量子 井層施加應變。 在形成了通常包含該基材至前文所述的該量子井層之 該裝置堆疊之後，可在該量子井層之上形成一覆蓋層。在 一特定實施例中，係以矽鍺（SiGe)或矽實施該覆蓋層， 且該覆蓋層具有2至10奈米（例如，6奈米）的範圍內之一 厚度。將可了解的，可將其他適當的覆蓋層材料用來保護 該下方鍺量子井層。 基於鍺鰭的調變摻雜量子井裝置 第2至8圖以橫斷面圖及透視圖示出根據本發明的一實 施例而配置的一基於鍺鰭的量子井結構之形成。將可了解 的，可在第1圖所示之該裝置堆疊上或任何數目之具有一 未被摻雜的鍺通道的其他調變摻雜/ Delta型摻雜量子井生 長結構上形成該基於鰭的結構。請注意，可將諸如平坦化 (例如，化學機械硏磨（Chemical Mechanical Polishing :簡稱CMP ))及後續的清洗製程等的中間製程包含在整 個形成製程中’但是可能並未明確地說明此類製程。 第2圖示出根據本發明的一實施例而自第1圖所示之該 -13- 201230327 量子井生長結構去除該覆蓋層。在一此類實施例中， 蓋層是矽鍺（SiGe )(例如’ 60%的鍺）或矽。無論 ，可以諸如蝕刻法（溼式及/或乾式蝕刻去除該覆蓋 而露出下方之鍺量子井層。 第3圖示出在第2圖所示之該量子井生長結構上沈 硬質罩幕且在該硬質罩幕中產生圖案。可使用標準微 執行用於淺溝槽隔離（STI )形成之圖案產生，其中 準微影法包含下列步驟：沈積硬質罩幕材料（例如， 化矽、氮化矽、及/或其他適當的硬質罩幕材料；在 質罩幕中將暫時地保留用於保護下方鰭結構（在本例 爲鍺通道）的一部分上之光阻上產生圖案；蝕刻而去 硬質罩幕的沒有罩幕（沒有光阻）之部分（例如，使 式蝕刻、或其他適當的硬質罩幕去除製程；然後剝離 生圖案之光阻。在第3圖所示之實施例中，所形成的 質罩幕是在該裝置堆疊的中心，且被形成在一位置， 在其他實施例中，該硬質罩幕可能根據特定的主動裝 偏移到該堆疊的一側，且/或被設置在該堆疊上的多 置。 第4圖示出用來形成第3圆所示的該量子井生長結 的一鍺鰭結構之一淺溝槽隔離（STI )蝕刻，且第5圖 根據本發明的一實施例而在該鍺鰭結構周圍沈積且平 介電材料。可使用其中包括蝕刻的標準微影法去除該 中沒有被該硬質罩幕保護的~些部分（例如，溼式或 蝕刻）’且而沈積一介電材料（例如，二氧化矽或其 該覆 如何 層， 積一 影法 該標 二氧 該硬 子中 除該 用乾 該產 該硬 但是 置而 個位 構上 示出 坦化 堆疊 乾式 他適 -14 - 201230327 當的介電材料）’而執行上述之介電材料沈積及平坦化。 可改變該STI蝕刻的深度’但是在某些實施例中，該深度 是在該鍺量子井層底部之下〇埃至5000埃之範圍內。在該 實施例中，該蝕刻深度幾乎到了該材料阻障層的底部。一 般而言’該蝕刻應到足以可讓該量子井通道（與鄰近元件 部分或其他潛在干擾源）電氣上被隔離之深度。在形成了 該s TI且沈積了介電材料之後，可硏磨/平坦化（例如， 使用化學機械硏磨（CMP))該被沈積的介電材料。請注 意，可保留該硬質罩幕.，以便保護該鍺通道。 第6圖不出根據本發明的一實施例而使第5圖所示的該 量子井生長結構的該STI介電材料凹下之蝕刻。亦可使用 其中包括蝕刻的標準微影法去除該介電材料（例如，使用 溼式蝕刻，但是亦可使用乾式蝕刻），而執行使上述之 S TI介電材料凹下之蝕刻。可改變該凹下蝕刻之深度，但 是該深度通常是在該鍺量子井層（通道）的底部與該摻雜 層上面之間。如圖所示，在該實施例中，該凹下蝕刻深度 是到了該鍺量子井層（通道）的底部。請注意，該硬質罩 幕仍然留在適當的位置，以便保護該鍺鰭結構（或通道） 〇 第7圖示出根據本發明的一實施例而在第6圖所示的該 量子井生長結構上形成閘極。第8圖的透視圖所示之形成 的結構實際上是被配置成一鰭式場效電晶體（FinFET)裝 置（因而爲非平面）之一鍺量子井結構。如所習知的，鰭 式場效電晶體（FinFET)是一種在一薄半導體材料帶（通 201230327 常被稱爲鰭）周圍建構之電晶體。該FinFET裝置包含標準 場效電晶體（FET )之節點，該等節點包括一閘極、一閘 極介電層（通常爲高k値）、一源極區、以及一汲極區（ 第8圖中只大致示出一源極/汲極區）。該裝置之導電通 道位於該閘極介電層之下的鰭之外側上。具體而言，電流 沿著該鰭的兩側壁（垂直於基材表面的面）且沿著該鰭的 頂部（平行於基材表面的面）而流動。因爲此類結構的導 電通道實質上沿著該鰭的三個不同的外平面區而分佈，所 以此種鰭式場效電晶體（FinFET)設計有時被稱爲三閘極 FinFET。也有諸如被稱爲雙閘極FinFET之其他類型的 FinFET構型，其中導電通道主要只沿著該鰭的兩個側壁（ 且不沿著該鰭的頂部）而分佈。 如第7圖所示’該硬質罩幕被去除（例如，使用溼式 或乾式蝕刻），且在該鍺通道之上沈積一上阻障層，其中 該鍺通道根據該摻雜層是未被摻雜的。該上阻障層可以是 諸如一被沈積的矽/矽鍺層。該上阻障層之厚度可以是諸 如10埃至100埃（例如’ 50埃）。一般而言，可由具有比 形成下方量子井通道的鍺材料的能帶間隙高的一能帶間隙 之任何適當的材料形成該上阻障層，且該上阻障層有足以 提供電晶體通道中之電荷載子的一位能障之厚度。在該上 阻障層上沈積的該高k値閘極介電層可以是具有在1〇埃至 5〇埃的範圍內（例如’ 2〇埃）的厚度之—薄膜，且可以諸 如二氧化飴（hafnium oxide )、氧化鋁（alumina )、五 氧化一鉬（tantalum pentaoxide) '氧化锆（zirconium -16- 201230327 oxide)、銘酸鋼（lanthanum aluminate)、銳酸 ( gadolinium scandate)、給砂氧化物（hafnium silicon oxide)、氧化鑭（lanthanum oxide)、鑭鋁氧化物（ lanthanum aluminum oxide )、錐砂氧化物（zirconium silicon oxide )、氧化钽（tantalum oxide )、氧化鈦（ titanium oxide )、鋇總欽氧化物（barium strontium titanium oxide )、鋇欽氧化物（barium titanium oxide) 、總欽氧化物（strontium titanium oxide )、氧化 f乙（ yttrium oxide )、氧化 |呂（aluminum oxide)、鈴钪钽氧 化物（lead scandium tantalum oxide)、或鈮酸辞給（ lead zinc niobate)等的具有大於諸如二氧化砂的介電常 數的一·介電常數之其他此類材料實施該高k値閘極介電層 。在該高k値閘極介電層之上沈積的閘極金屬可以是諸如 鎳、金、鈾、鋁、鈦、鈀、鈦鎳合金、或其他適當的閘極 金屬或合金。可針對FinFET結構而以傳統方式形成源極/ 汲極區，且該源極/汲極區可被配置成具有與該閘極相同 的金屬、或另一適當的接觸金屬。如根據本發明之揭示而 將可了解的，可使用標準FinFET製程實施該上阻障層、高 k値閘極介電層、閘極金屬、及源極/汲極區。 因此，本發明提供之技術係在非平面架構之環境中採 用了通常被用於製造平面量子井堆疊之調變摻雜技術，以 便提供一種具有未被摻雜的鍺通道之FinFET裝置。可使用 諸如矽鍺（SiGe )、砷化鎵（GaAs )、或砷化鋁鎵（ AlGaAs )等的一些適當之〖V族/ III-V族材料。可將如圖 -17- 201230327 所示的所形成之積體電路裝置用來作爲可被安裝在諸如中 央處理單元、記憶體陣列、晶片上快取記憶體、或邏輯閘 等的數種微電子裝置中之任何微電子裝置之一電晶體。同 樣地，許多系統層級的應用可採用本發明所述之積體電路 方法 第9圖示出根據本發明的一實施例而形成基於鍺鰭的 調變摻雜/ Delta型摻雜量子井結構之一方法。可視需要而 配置該量子井結構，且該量子井結構通常包含一堆疊，該 堆疊包含一基材、一IV族/ ΙΠ-V族阻障層、一（調變摻雜 / Delta型摻雜的）摻雜層、以及一量子井層。 該方法包含：在步驟901中，去除該量子井結構的一 覆蓋層（在有該覆蓋層之情形下），以便露出下方之鍺量 子井結構。可使用諸如溼式或乾式蝕刻而去除該覆蓋層。 該方法繼續在步驟903中於一硬質罩幕中產生圖案，而執 行淺溝槽隔離（STI)之圖案產生。該產生圖案步驟可包 括諸如：沈積硬質罩幕材料；在該硬質罩幕中將在STI蝕 刻期間暫時保護該裝置的下方鰭結構之一部分上的光阻中 產生圖案；蝕刻而去除該硬質罩幕的沒有罩幕（沒有光阻 )之部分（例如，使用乾式蝕刻或其他適當的硬質罩幕去 除製程）：以及然後剝離該產生圖案之光阻，以便提供一 產生圖案的STI硬質罩幕。 該方法繼續在步驟905中將一 STI蝕刻到鍺量子井結構 201230327 ，因而形成了一鶴結構。在一例子中，如前文所述，可使 用一或多次乾式及/或溼式鈾刻而執行該溝槽形成。該方 法繼續在步驟907中將介電材料沈積到該STI，且將該介電 材料平坦化。該方法繼續在步驟909中使該STI材料凹下（ 例如，凹下到該鍺量子井層的底部且在該摻雜層之前）。 可以諸如一溼式蝕刻實施該蝕刻。 該方法繼續在步驟911中在該鰭結構之上沈積一上阻 障層及一或有的高k値聞極介電層。如前文所述，可以具 有比形成下方量子井通道的鍺材料的能帶間隙高的一能帶 .間隙之任何適當的材料（例如，矽/矽鍺）形成該上阻障 層，且該上阻障層有足以將一位能障提供給電晶體通道中 之電荷載子之厚度。該高k値閘極介電層可以是諸如具有 可充分隔離該金屬閘極的適當的厚度以及大於諸如二氧化 矽的介電常數的一介電常數之一薄膜。本發明亦可使用其 他適當的閘極介電層（例如，非高k値介電層），且在該 上阻障層獨立地提供充分的隔離之某些實施例中，可以不 需要閘極介電層。該方法繼續在步驟913中在該上阻障層 之上以及形成裝置通道的該被隔離之鍺鰭結構上沈積閘極 金屬’且繼續在步驟9 1 5中於該鰭結構（通道）的各別端 上形成汲極及源極區。可使用標準製程（沈積、遮罩、蝕 刻、平坦化等的製程）實施該閘極金屬及源極/汲極區。 因此’提供了被配置成具有一未被摻雜的鍺通道之一 非平面調變摻雜/ Delta型摻雜量子井結構。可將該結構用 來作爲諸如適用於許多應用（例如，處理器、記億體等的 -19- 201230327 應用）之一FinFET裝置（例如，雙閘極或三 〇 根據本發明之揭示將可了解許多實施例 ，本發明之一實施例提供了一種形成非平面 方法。該方法包含下列步驟：接收具有一基 ΠΙ-ν族材料阻障層、一摻雜層、以及一未被 井層之一量子井結構。該方法進—步包含下 性地蝕刻該量子井結構，而形成一鍺鰭結構 之上沈積一上阻障層：以及在該鰭結構上沈 在一特定例子.中，選擇性地蝕刻該量子井結 含下列步驟：在該量子井結構上的一硬質罩 ，以便執行淺溝槽隔離（STI)圖案產生；步 該量子井結構；將介電材料沈積到該STI ; 材料平坦化。在一此類例子中，使該STI中 下到該鍺量子井層之底部。該方法可包含下 鰭結構的各別末端上形成汲極及源極區。該 列步驟：去除該量子井結構之一覆蓋層，以 子并結構。在另一特定例子中，在該鰭結構 上阻障層之後，且在該鰭結構上沈積閘極金 法進一步包含下列步驟：在該上阻障層之J; 閘極介電層。該量子井結構可以是諸如一磊 結構。該摻雜層可包含諸如Delta型摻雜，用 雜的鍺量子井層進行調變摻雜。在另一特定 該摻雜層之後，以磊晶方式生長該未被摻雜 閘極 FinFET ) 及結構。例如 量子井結構之 材、一 IV族或 摻雜的鍺量子 列步驟：選擇 :在該鰭結構 積閘極金屬。 構之該步驟包 幕中產生圖案 导一STI蝕刻到 以及將該介電 之介電材料凹 列步驟：在該 方法可包含下 便露出該鍺量 之上沈積了 一 屬之前，該方 :沈積一高k値 晶生長的異質 以對該未被慘 例子中，可在 的鍺量子井層 -20- 201230327 本發明之另一實施例提供了一種非平面量子井裝置。 該裝置包含一量子井結構，該量子井結構具有一基材、一 IV族或III-V族材料阻障層、—摻雜層、以及—未被摻雜的 錯量子井層。該裝置進—步包含在該量子井結構中形成之 一未被摻雜的鍺鰭結構、在該鰭結構之上沈積之—上阻障 層、以及在該鰭結構上沈積之閘極金屬。該裝置可包含諸 如在淺溝槽隔離（STI)中接近該鰭結構之凹下的介電材 料。在一此類例子中，使該STI中之該介電材料凹下到該 錯量子井層之底部。該裝置可包含在該鰭結構的各別末端 上形成之汲極及源極區。該裝置可包含被沈積在該上阻障 層與閘極金屬間之一高k値閘極介電層。在一例子中，該 非平面量子井結構包含一鰭式場效電晶體（FinFET)裝置 。在另一例子中，係以矽鍺、砷化鎵、或砷化鋁鎵實施該 IV族或III-V族材料阻障層，且該基材包含矽上覆矽鍺或砷 化鎵緩衝層。在另一例子中，該量子并結構是一磊晶生長 的異質結構。在另一例子中，該摻雜層包含Delta型摻雜， 用以對該未被摻雜的鍺量子井層進行調變摻雜。在另一例 子中，在該摻雜層之後（或在該阻障層上或內），以磊晶 方式生長該未被摻雜的鍺量子井層。 本發明之另一實施例提供了一種非平面量子井裝置。 在該例子中，該裝置包含一量子井結構，該量子井結構具 有一基材、一 IV族或III-V族材料阻障層、一摻雜層、以及 一未被摻雜的鍺量子井層。該量子井結構是一磊晶生長之 -21 - 201230327 異質結構，其中在該摻雜層之後，以磊晶方式生長該未被 摻雜的鍺量子井層，且該摻雜層對該未被摻雜的鍺量子井 層進行調變摻雜。該裝置進一步包含在該量子井結構中形 成之一未被摻雜的鍺鰭結構、在該鰭結構之上沈積之一上 阻障層、以及在該鰭結構上沈積之-閘極金屬。此外，該 裝置包含在該鰭結構的各別末端上形成之汲極及源極區、 以及被沈積在該上阻障層與閘極金屬間之一高k値閘極介 電層。 已爲了例示及說明之目的而提供了前文中對本發明的 實施例之說明。該說明將不具有耗盡性，也並非將本發明 限制於所揭示之確切形式。根據本發明揭示的許多修改及 變化都是可能的。本發明之範圍將不受該詳細說明之限制 ，而是只受限於本發明最後的申請專利範圍》 【圖式簡單說明】 第1圖是於製造根據本發明的一實施例的一非平面鍺 量子井裝置時可被使用的一例示鍺量子井生長結構之一橫 斷面側視圖。 第2圖示出根據本發明的一實施例而自第1圖所示之該 量子井生長結構去除覆蓋層。 第3圖示出根據本發明的一實施例而在第2圖所示之該 量子井生長結構上沈積一硬質罩幕且在該硬質罩幕中產生 圖案。 第4圖示出根據本發明的一實施例而用來形成第3圖所 -22- 201230327 示的該量子井生長結構上的一鍺鰭結構之一淺溝槽隔離（ S TI )蝕刻。 第5圖示出根據本發明的一實施例而在第4圖所示的_ 量子井生長結構的該鍺鰭結構周圍沈積且平坦化介電材料 〇 第6圖示出根據本發明的一實施例而使第5圖所示的該 量子井生長結構的該STI介電材料凹下之蝕刻。 第7圖示出根據本發明的一實施例而在第6圖所示的該 量子井生長結構的該鍺鰭結構上之閘極形成。 第8圖是根據本發明的一實施例而配置的第7圖所示裝 置之一透視圖。 第9圖示出根據本發明的一實施例而形成基於鍺鰭的 調變摻雜量子井結構之一方法。 -23-201230327 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a non-planar germanium quantum well device. [Prior Art] A quantum well transistor device formed in an epitaxially grown semiconductor heterostructure and typically formed in a ΠΙ-ν family or a 矽-锗/锗 (SiGe/Ge) material system, providing a transistor due to low effective mass Very high carrier mobility in the channel and lower impurity scattering due to De 11 a doping. In addition, these devices provide very high drive current performance. However, since a quantum well transistor is formed in a heterostructure grown by epitaxial growth, the formed structure includes a plurality of vertical epitaxial layers, and only a planar type quantum well device is allowed to be formed. [Invention] The present invention discloses The technique of forming a non-planar germanium quantum well structure. The quantum well structure can be implemented, in particular, from a Group IV or III-V semiconductor material, and the quantum well structure comprises a skeletal structure. In one example, a non-planar quantum well device is provided, the quantum well device comprising a quantum well structure having a substrate (eg, germanium overlying germanium (SiGe) or gallium arsenide (GaAs) a buffer layer), a Group IV or III-V material barrier layer (eg, germanium (SiGe), gallium arsenide (GaAs), or aluminum gallium arsenide (AlGaAs), a doped layer (eg 'by Delta' a layer of doping/modulation doping-5-201230327, and an undoped germanium quantum well layer. An undoped skeletal structure is formed in the quantum well structure, and the fin structure is formed An upper barrier layer is deposited thereon. A gate metal can be deposited on the fin structure. A drain/source region can be formed on each end of the fin structure. [Embodiment] The present invention discloses forming a non-planar surface. The technique of the quantum well structure. The quantum well structure can be implemented, in particular, with a Group IV or III-V semiconductor material, and the quantum well structure comprises a fin structure, thereby effectively providing a hybrid structure. Non-planar devices such as improved modulation doping / Delta doping The short channel effect and gate length (Lg) scalability achieves the electrostatic benefits of the fin-based device while preserving the high mobility benefits of the modulated doping/delta type doping device. As mentioned above, quantum well crystal devices formed in epitaxially grown semiconductor heterostructures and typically in bismuth-V material systems provide very high carrier mobility in the transistor channel due to low effective mass, And because of the Delta-type doping, it provides lower impurity scattering. These conventional devices provide very high drive current performance. These quantum well systems are typically fabricated in a planar architecture. FinFETs such as FinFETs can be used. Non-planar transistor architectures such as dual gate, triple gate, or surround gate structures are used to improve static and short channel effects, and thus can have a gate length of -6-201230327 (Lg Scalability. However, such non-planar architectures are generally considered to be incompatible with high quality and high mobility doped quantum well transistors formed in crystal growth heterostructures. Therefore, in accordance with an embodiment of the present invention, a modulated doped non-planar germanium quantum well transistor device is provided, such as germanium, germanium (SiGe), germanium, and/or gallium arsenide (GaAs). A semiconductor heterostructure of aluminum arsenide (AlAs) or the like forms the device. Any number of epitaxially grown heterostructures fabricated from Group IV or III-V materials can be configured to have a fin-based channel. A Delta-type doping, such as in a material having a larger band gap, is doped with a lower band gap material in a modulated doping manner. After the larger band gap material and the delta type doping, the lower band gap material is grown in an epitaxial manner. A pattern can be created in the heterostructure, the heterostructure is also etched into one or more narrow fins, and the delta-type doped/modulated doped lower energy band gap material in those fins constitutes the active region of the device. Ontology. For example, it can be used in a manner similar to that used to fabricate conventional yttrium-based non-planar devices that include shallow trench isolation (STI) 'gate stacks, source/drain regions, and contact points. Perform the process of manufacturing the device. However, in contrast to conventional non-planar devices with a high degree of doping in the active region body of the device, the active region body of the skeletal structure does not contain dopants (this is due to modulation doping / Delta doping The device is doped in a manner) and thus provides a significant increase in carrier mobility due to better Coulomb scattering. 201230327 The non-planar undoped stencil-based device generally exhibits a better gate length (Lg) and a threshold voltage (Vt) than conventional modulated doped planar quantum well devices formed in a semiconductor heterostructure. Scalability improved device electrostatic properties. Other advantages will be readily apparent from the disclosure of the present invention. For example, one of the -III_V family/锗 hybrid systems configured in accordance with an embodiment of the present invention has the advantage that etching between the III-V material (in the barrier layer) and the (fin in the fin structure) can be performed. Selectively used in shallow trench isolation (STI) processes where STI etching is performed only on the 锗/III-V family interface. Thus, in view of a desired germanium quantum well structure, a fin structure (and structures of gates, source/drain regions, and contacts, etc.) can be formed in accordance with an embodiment of the present invention. Thus, in accordance with an embodiment, the formation of a modulated doped non-planar germanium quantum well transistor device can generally include the growth of a lower quantum well structure (or any portion of the quantum well structure) prior to formation of the skeg structure. The II embodiment assumes that the quantum well structure is preformed and then the skeletal structure is formed in the quantum well structure. Quantum Well Structure Figure 1 is a cross-sectional side view of an exemplary quantum well growth structure that can be used in the fabrication of a non-planar germanium quantum well device in accordance with an embodiment of the present invention. The quantum well growth structure can be, for example, a conventional germanium/ruthenium or gallium arsenide/germanium quantum well structure having a capping layer. However, 'as noted above', please note that any number of quantums that can be configured as having various 1V or 11 family materials 201230327, doped layers, and buffer layers, as will be appreciated in accordance with the teachings of the present invention. The well growth structure implements a modulated doped/delta type doped non-planar germanium quantum well transistor device formed in accordance with an embodiment of the present invention. The invention as described in the patent application will not be limited to any particular quantum well growth configuration. As shown in Figure 1, the quantum well growth structure comprises a substrate on which a plurality of nucl eat ions and buffer layers are formed. The structure further includes a barrier layer of a group IV or III-V material, and a doped layer is formed over the barrier layer, and a spacer layer is formed over the doped layer and at the interval A germanium quantum well layer is formed on the layer. A cover layer is provided on the tantalum well layer. Each of these exemplary layers will be described in turn below. Other embodiments may include fewer layers (eg, fewer buffer layers and/or no cover layers), or more layers (eg, additional spacer layers and/or doped layers below the quantum well layer) ), or a different layer (eg, a layer formed of a different semiconductor material, formulation, and/or dopant). Such established semiconductor processes (eg, metal organic chemical vapor deposition, molecular beam epitaxy, lithography, or other such suitable process) can be implemented with any suitable layer thickness and other desired layer parameters. The layers, and the layers may be graded (eg, linear or stepwise) to improve lattice constant matching between adjacent layers of materials having different crystal lattices. In general, the dimensions of such particular layers and structures will depend on factors such as desired device performance, plant capabilities, and semiconductor materials used. The substrate can be implemented in a typical manner, and any number of suitable substrate types and materials can be used in the present invention (eg, p-type, n-type, neutral, tantalum, niobium, high or low resistivity, offset cut ( 0ff-cut) or non-offset cut -9 - 201230327 Type, material, etc. for cutting, bulk, or silicon-on-insulator. In one embodiment, the substrate is a substrate tantalum substrate. In another embodiment, the substrate is a matrix substrate. Other embodiments may use an insulating layer such as an insulating layer overlying germanium (SOI), or a germanium on insulator (GeOI), or a SiGe On Insulator (SiGeOI). Cover the semiconductor structure. Nucleation and buffer layers are formed on the substrate, and the nucleation and buffer layers can also be carried out in a typical manner. In a particular embodiment, the nucleation and buffer layer is made of germanium (SiGe) (eg, 60% germanium) or gallium arsenide (GaAs), and the nucleation and buffer layer has about 0.5 to 2.0. The overall thickness of the micron (e.g., a nucleation layer having a thickness of about 25 nm to 50 nm, and a buffer layer having a thickness of about 0.3 to 1.9 μm). As is conventional, the nucleation and buffer layer can be used to fill the lowest substrate platform with an atomic bi-layer of a Group III-V material such as a gallium arsenide (GaAs) material. The nucleation layer can be used to generate an anaphase domain-free virtual polar substrate, and the buffer layer can be used to provide a dislocation filtering buffer. And the dislocation filter buffer structure can provide a compressive strain of the quantum well structure and/or can provide control of the lattice mismatch between the substrate and the barrier layer. The buffer layers may also comprise a graded buffer layer and the graded buffer layer may also be implemented in a conventional manner. As is known by the formation of the graded buffer layer, the dislocations can be moved along the more diagonal plane between them - 10, 201230327, thus effectively controlling the substrate and the Group IV / 11 material. Lattice mismatch between the barrier layer (and/or any intermediate layer). Such a graded layer can be used for other locations of the quantum well structure or stack. It is noted that other quantum well structures that may benefit from embodiments of the present invention may be implemented without the nucleation and/or buffer layer. For example, an embodiment having a substrate and a barrier layer which are sufficiently similar in lattice constant can be implemented without a graded buffer layer. In this embodiment, the Group IV/III-V barrier layer is formed on the nucleation and buffer layer, and the Group IV/III-V barrier layer can also be implemented in a conventional manner. In a particular embodiment, is Si, -xGex (where X is in the range of 4 to 80 such as 60), or gallium arsenide (GaAs), or A1, xGax As (where X is in, for example The barrier layer is implemented in the range of 50 to 90 of 70, and the barrier layer has a thickness in the range of 4 nm to 120 nm (for example, 1 〇〇 nanometer ± 20 nm). Generally, the barrier layer is formed from a material having a band gap higher than the energy band gap of the material forming the upper quantum well layer, and the barrier layer is sufficient to provide the charge carriers in the transistor channel. The thickness of a potential barrier. As will be appreciated, the actual construction and thickness of the barrier layer will depend on factors such as substrate and quantum well material and/or thickness. Many such barrier materials and structures can be used in the present invention as will be appreciated in light of the present disclosure. In the illustrated quantum well growth structure, the doped layer is formed on (or within) the barrier layer and the doped layer can also be implemented in a conventional manner. In general, the barrier layer can be doped with the doped layer to supply carriers to the quantum well layer. The doped layer may be doped with -11 - 201230327, such as a delta type doping (or modulation doping). For an n-type device utilizing a barrier layer of a (S i G e ) material, the doping may be performed using impurities such as boron and/or germanium, and for a P-type device, such as germanium may be used. This doping is carried out with (Be) and/or carbon. The thickness of the doped layer will depend on factors such as the type of doping and the materials used. For example, in one embodiment, the doped layer is one of boron thicknesses of about 3 Å to about 15 Å. In another embodiment, the doped layer is a beryllium (Be) modulated doped gallium arsenide (GaAs) layer having a thickness between about 15 angstroms and 60 angstroms. Doping can be selected based on the sheet carrier concentration of the channels, such as those applicable to the quantum well layer. An embodiment of the invention may be implemented in a quantum well structure that may be of any type of one or more suitable doped layers, as will be appreciated in light of the present disclosure. The spacer layer is formed on (or over) the doped layer, and the spacer layer can also be implemented in a conventional manner. In a particular embodiment, is Sii.xGex (where X is in the range of 40 to 80 such as 60), or gallium arsenide (GaAs), or Ah.xGaxAs (where X is 50 to such as 70 The spacer layer is implemented in the range of 90, and the spacer layer has a thickness in the range of 0.2 nm to 70 nm (for example, 5 nm). In general, the spacer layer can be configured to provide compressive strain to the quantum well layer because the quantum well layer is used as a semiconductor channel. It is noted that other quantum well structures that may benefit from embodiments of the present invention may be implemented without the spacer layer. The quantum well layer can also be implemented in a conventional manner. In general, the -12-201230327 quantum well layer is implemented with an undoped germanium having an exemplary thickness of about 20 angstroms to 500 angstroms. As will be appreciated, many other quantum well layers can be used in the present invention. More generally, the quantum well layer has a band gap smaller than the energy band gap of the 1 //111 族 barrier layer and the quantum well layer is undoped, and the quantum well layer A thickness sufficient to provide adequate channel conductivity for a particular application of a memory cell or logic transistor or the like. The barrier layer, an upper barrier layer, or both barrier layers can apply strain to the quantum well layer. A blanket layer can be formed over the quantum well layer after forming a stack of the device that typically includes the substrate to the quantum well layer described above. In a particular embodiment, the cover layer is implemented with germanium (SiGe) or germanium, and the cover layer has a thickness in the range of 2 to 10 nanometers (e.g., 6 nanometers). It will be appreciated that other suitable overlay materials can be used to protect the underlying germanium well layer. Trump-Based Modulated Doping Quantum Well Apparatus Figures 2 through 8 illustrate, in cross-sectional and perspective views, the formation of a fin-based quantum well structure configured in accordance with an embodiment of the present invention. It will be appreciated that the fin-based growth structure can be formed on the stack of devices shown in FIG. 1 or any other number of modulated doped/delta type doped quantum well growth structures having an undoped germanium channel. Structure. Please note that intermediate processes such as planarization (eg, Chemical Mechanical Polishing (CMP)) and subsequent cleaning processes may be included throughout the fabrication process' but may not explicitly state such processes . Figure 2 illustrates the removal of the cover layer from the -13-201230327 quantum well growth structure shown in Figure 1 in accordance with an embodiment of the present invention. In one such embodiment, the cap layer is tantalum (SiGe) (e.g., < 60% tantalum) or tantalum. Either, the etching may be performed by etching (wet and/or dry etching to expose the underlying quantum well layer. Figure 3 shows the hard mask on the quantum well growth structure shown in Fig. 2 and A pattern is created in the hard mask. Pattern generation for shallow trench isolation (STI) formation can be performed using standard micro-lithography, which includes the following steps: depositing a hard mask material (eg, germanium, tantalum nitride) And/or other suitable hard mask material; a pattern is temporarily retained in the mask to protect the photoresist on a portion of the underlying fin structure (in this case, the channel); etching to remove the hard mask The portion of the curtain that has no mask (no photoresist) (eg, etched, or other suitable hard mask removal process; then the photoresist of the green pattern is stripped. In the embodiment shown in FIG. 3, formed The hood is at the center of the stack of devices and is formed in a position that, in other embodiments, may be offset to one side of the stack according to a particular active fit and/or On the stack Figure 4 shows a shallow trench isolation (STI) etch of a fin structure used to form the quantum well growth junction shown in the third circle, and Figure 5 is in accordance with an embodiment of the present invention. Depositing and planarizing a dielectric material around the skeletal structure. The portion of the refractory-containing lithography may be used to remove portions (eg, wet or etched) that are not protected by the hard mask and deposit a a dielectric material (for example, cerium oxide or a layer thereof), which is a method of averaging the hard oxidized material. The dielectric material can be deposited and planarized as described above. The depth of the STI etch can be varied. 'But in some embodiments, the depth is at the bottom of the 锗 quantum well layer. Below the range of 〇 5,000 Å. In this embodiment, the etch depth is almost at the bottom of the barrier layer of the material. Generally, the etch should be sufficient to allow the quantum well channel (with adjacent component parts) Or other potential sources of interference) The depth of the gas is isolated. After the s TI is formed and the dielectric material is deposited, the deposited dielectric material can be honed/planarized (eg, using chemical mechanical honing (CMP)). The hard mask can be retained to protect the crucible channel. Figure 6 illustrates the etching of the STI dielectric material of the quantum well growth structure shown in Figure 5 in accordance with an embodiment of the present invention. The dielectric material may also be removed using standard lithography including etching (eg, using wet etching, but dry etching may also be used), and etching to recess the above-described S TI dielectric material may be performed. Depth the depth of the etch, but the depth is typically between the bottom of the germanium quantum well layer (via) and the top of the doped layer. As shown, in this embodiment, the recess etch depth is The bottom of the quantum well layer (channel). Please note that the hard mask remains in place to protect the skeletal structure (or channel). FIG. 7 illustrates the quantum well growth structure shown in FIG. 6 in accordance with an embodiment of the present invention. A gate is formed on it. The structure shown in the perspective view of Fig. 8 is actually a quantum well structure configured as a fin field effect transistor (FinFET) device (and thus non-planar). As is known, a fin field effect transistor (FinFET) is a transistor constructed around a thin strip of semiconductor material (often referred to as fins in 201230327). The FinFET device includes a node of a standard field effect transistor (FET), the node including a gate, a gate dielectric layer (typically high k値), a source region, and a drain region (8th) Only one source/drain region is shown in the figure. The conductive path of the device is on the outside of the fin below the gate dielectric layer. Specifically, current flows along both sidewalls of the fin (the surface perpendicular to the surface of the substrate) and along the top of the fin (the surface parallel to the surface of the substrate). Because the conductive channels of such structures are distributed substantially along three different outer planar regions of the fin, such fin field effect transistor (FinFET) designs are sometimes referred to as triple gate FinFETs. There are other types of FinFET configurations, such as those known as double gate FinFETs, in which the conductive vias are primarily distributed only along the two sidewalls of the fin (and not along the top of the fin). As shown in FIG. 7 'the hard mask is removed (for example, using wet or dry etching), and an upper barrier layer is deposited over the germanium channel, wherein the germanium channel is not according to the doped layer Doped. The upper barrier layer can be, for example, a deposited ruthenium/ruthenium layer. The upper barrier layer may have a thickness of, for example, 10 angstroms to 100 angstroms (e.g., < 50 angstroms). In general, the upper barrier layer can be formed of any suitable material having a band gap that is higher than the band gap of the germanium material forming the underlying quantum well channel, and the upper barrier layer is sufficient to provide a transistor channel The thickness of one of the charge carriers. The high-k gate dielectric layer deposited on the upper barrier layer may be a film having a thickness in the range of 1 至 to 5 Å (for example, 2 Å Å), and may be, for example, dioxide Hafnium oxide, alumina, tantalum pentaoxide 'zirconium -16- 201230327 oxide, lanthanum aluminate, gadolinium scandate, sand oxidation Hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, oxidation, oxidized Lead scandium tantalum oxide, or lead zinc niobate, etc., having a dielectric constant greater than a dielectric constant such as silica sand The material implements the high-k gate dielectric layer. The gate metal deposited over the high-k gate dielectric layer can be, for example, nickel, gold, uranium, aluminum, titanium, palladium, titanium-nickel alloy, or other suitable gate metal or alloy. The source/drain regions can be formed in a conventional manner for the FinFET structure, and the source/drain regions can be configured to have the same metal as the gate, or another suitable contact metal. As will be appreciated in light of the teachings of the present invention, the upper barrier layer, the high k gate dielectric layer, the gate metal, and the source/drain regions can be implemented using standard FinFET processes. Accordingly, the present invention provides a technique for utilizing a modulation doping technique commonly used in the fabrication of planar quantum well stacks in a non-planar architecture environment to provide a FinFET device having an undoped germanium channel. Some suitable Group V/III-V materials such as germanium (SiGe), gallium arsenide (GaAs), or aluminum gallium arsenide (AlGaAs) may be used. The integrated circuit device formed as shown in FIG. 17-201230327 can be used as several kinds of microelectronics that can be mounted on, for example, a central processing unit, a memory array, a cache memory on a wafer, or a logic gate. A transistor of any of the microelectronic devices in the device. Similarly, many system level applications may employ the integrated circuit method of the present invention. FIG. 9 illustrates the formation of a falcon-based modulation doping/delta type doped quantum well structure according to an embodiment of the present invention. A method. The quantum well structure can be configured as needed, and the quantum well structure generally comprises a stack comprising a substrate, a group IV/ΙΠ-V barrier layer, and a (modulation doped/delta type doped a doped layer, and a quantum well layer. The method includes, in step 901, removing a cover layer of the quantum well structure (in the presence of the cover layer) to expose the underlying quantum well structure. The cover layer can be removed using, for example, wet or dry etching. The method continues with patterning in a hard mask in step 903 to perform pattern creation of shallow trench isolation (STI). The patterning step can include, for example, depositing a hard mask material in which a pattern is created in the photoresist on a portion of the underlying fin structure that temporarily protects the device during STI etching; etching to remove the hard mask There is no portion of the mask (no photoresist) (for example, using a dry etch or other suitable hard mask removal process): and then stripping the resulting pattern of photoresist to provide a patterned STI hard mask. The method continues by etching an STI to the germanium quantum well structure 201230327 in step 905, thereby forming a crane structure. In one example, the trench formation can be performed using one or more dry and/or wet uranium engravings as previously described. The method continues by depositing a dielectric material to the STI in step 907 and planarizing the dielectric material. The method continues by recessing the STI material in step 909 (eg, recessing to the bottom of the germanium quantum well layer and before the doped layer). The etching can be performed such as a wet etching. The method continues by depositing an upper barrier layer and a contiguous high k smear dielectric layer over the fin structure in step 911. As described above, the upper barrier layer may be formed by any suitable material (eg, 矽/矽锗) having a higher energy band gap than the energy band gap of the germanium material forming the lower quantum well channel, and the upper barrier layer The barrier layer has a thickness sufficient to provide a barrier to the charge carriers in the transistor channel. The high-k gate dielectric layer can be, for example, a film having a suitable thickness sufficient to isolate the metal gate and a dielectric constant greater than a dielectric constant such as cerium oxide. Other suitable gate dielectric layers (e.g., non-high-k値 dielectric layers) may also be used in the present invention, and in some embodiments where the upper barrier layer provides sufficient isolation independently, gates may not be needed Dielectric layer. The method continues by depositing a gate metal on the upper barrier layer and on the isolated skilital structure forming the device channel in step 913 and continuing in step 915 for each of the fin structures (channels) The bungee and source regions are formed on the other end. The gate metal and source/drain regions can be implemented using standard processes (deposition, masking, etching, planarization, etc.). Thus, a non-planar modulation doped/delta type doped quantum well structure configured to have an undoped germanium channel is provided. The structure can be used as one of FinFET devices such as dual gates or triacs, for example, for use in many applications (eg, processor, cc. In many embodiments, an embodiment of the present invention provides a method of forming a non-planar surface, the method comprising the steps of: receiving a barrier layer having a base germanium-ν material, a doped layer, and one of the unwelld layers Quantum well structure. The method further comprises etching the quantum well structure in an underlying manner to form an upper barrier layer on the surface of the fin structure: and depositing the fin structure in a specific example. Etching the quantum well junction comprises the steps of: forming a hard mask on the quantum well structure to perform shallow trench isolation (STI) pattern generation; stepping the quantum well structure; depositing a dielectric material onto the STI; In one such example, the STI is lowered to the bottom of the germanium quantum well layer. The method can include forming a drain and a source region on respective ends of the lower fin structure. The column step: removing the quantum well One of the cladding layers is a sub-layer and a structure. In another specific example, depositing a gate gold on the fin structure and depositing a gate gold on the fin structure further includes the step of: forming an upper barrier layer J; a gate dielectric layer. The quantum well structure may be, for example, a Lei structure. The doped layer may comprise, for example, a delta-type doping, which is doped with a heterojunction quantum well layer. After doping the layer, the undoped gate FinFET and structure are grown in an epitaxial manner. For example, a quantum well structure, a Group IV or doped 锗 quantum column step: Select: build a gate metal in the fin structure. Forming a step in the step of forming a pattern of STI etching and recessing the dielectric dielectric material: before the method can include exposing the enthalpy to deposit a genus, the side: deposition A high-k twin growth heterogeneity provides a non-planar quantum well device in accordance with another embodiment of the present invention in the unobtrusive example of the 锗 quantum well layer -20-201230327. The apparatus includes a quantum well structure having a substrate, a Group IV or III-V material barrier layer, a doped layer, and an undoped quantum well layer. The apparatus further includes an undoped skeletal structure formed in the quantum well structure, an upper barrier layer deposited over the fin structure, and a gate metal deposited on the fin structure. The device can include a dielectric material that approximates the recess of the fin structure, such as in shallow trench isolation (STI). In one such example, the dielectric material in the STI is recessed to the bottom of the fault quantum well layer. The device can include a drain and a source region formed on respective ends of the fin structure. The device can include a high-k gate dielectric layer deposited between the upper barrier layer and the gate metal. In one example, the non-planar quantum well structure comprises a fin field effect transistor (FinFET) device. In another example, the Group IV or III-V material barrier layer is implemented with germanium, gallium arsenide, or aluminum gallium arsenide, and the substrate comprises a germanium-on-layer or gallium arsenide buffer layer. . In another example, the quantum structure is an epitaxially grown heterostructure. In another example, the doped layer comprises a delta-type doping for modulation doping of the undoped germanium quantum well layer. In another example, the undoped germanium quantum well layer is grown epitaxially after the doped layer (or on or within the barrier layer). Another embodiment of the present invention provides a non-planar quantum well device. In this example, the apparatus includes a quantum well structure having a substrate, a Group IV or III-V material barrier layer, a doped layer, and an undoped germanium quantum well Floor. The quantum well structure is an epitaxially grown 21 - 201230327 heterostructure, wherein after the doped layer, the undoped germanium quantum well layer is grown in an epitaxial manner, and the doped layer is not The doped yttrium quantum well layer is modulated and doped. The apparatus further includes forming an undoped skeletal structure in the quantum well structure, depositing an upper barrier layer over the fin structure, and depositing a gate metal on the fin structure. In addition, the device includes a drain and a source region formed on respective ends of the fin structure, and a high-k gate dielectric layer deposited between the upper barrier layer and the gate metal. The foregoing description of the embodiments of the invention has been provided for purposes of illustration and description. This description is not exhaustive and is not intended to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the invention. The scope of the present invention is not limited by the detailed description, but is only limited by the scope of the final application of the present invention. [FIG. 1] FIG. 1 is a non-planar in accordance with an embodiment of the present invention. A cross-sectional side view of one of the growth structures of the quantum wells that can be used in the case of a quantum well device. Figure 2 illustrates the removal of the cover layer from the quantum well growth structure illustrated in Figure 1 in accordance with an embodiment of the present invention. Figure 3 illustrates the deposition of a hard mask on the quantum well growth structure shown in Figure 2 and the creation of a pattern in the hard mask, in accordance with an embodiment of the present invention. Figure 4 illustrates a shallow trench isolation (STI) etch of a skeletal structure on the quantum well growth structure shown in Figure 3, from -22 to 201230327, in accordance with an embodiment of the present invention. 5 is a view showing deposition and planarization of a dielectric material around the skeletal structure of the _ quantum well growth structure shown in FIG. 4 according to an embodiment of the present invention. FIG. 6 is a view showing an implementation according to the present invention. For example, the STI dielectric material of the quantum well growth structure shown in FIG. 5 is recessed and etched. Figure 7 illustrates the formation of a gate on the skeletal structure of the quantum well growth structure shown in Figure 6 in accordance with an embodiment of the present invention. Figure 8 is a perspective view of a device shown in Figure 7 configured in accordance with an embodiment of the present invention. Figure 9 illustrates one method of forming a falcon-based modulated doped quantum well structure in accordance with an embodiment of the present invention. -twenty three-