CN114122112A - Groove type power device and manufacturing method thereof - Google Patents
Groove type power device and manufacturing method thereof Download PDFInfo
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- CN114122112A CN114122112A CN202210093654.8A CN202210093654A CN114122112A CN 114122112 A CN114122112 A CN 114122112A CN 202210093654 A CN202210093654 A CN 202210093654A CN 114122112 A CN114122112 A CN 114122112A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims description 35
- 239000002019 doping agent Substances 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 23
- 238000001259 photo etching Methods 0.000 abstract 1
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- 229910052785 arsenic Inorganic materials 0.000 description 3
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- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000007796 conventional method Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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Abstract
The application belongs to the technical field of semiconductors, and particularly relates to a trench type power device and a manufacturing method thereof, wherein the trench type power device comprises: the semiconductor device comprises a semiconductor substrate, an epitaxial layer, a channel layer, a first groove structure, a second groove structure and an active region adjacent to the second groove structure, wherein the first groove structure comprises a first groove, a first insulating layer covering the inner wall of the first groove and a first polycrystalline material layer positioned in the first groove, the first polycrystalline material layer comprises at least one P-type doping layer and at least one N-type doping layer to form at least one diode structure, the directions of the P-type doping layer and the N-type doping layer are parallel to the opening direction of the first groove, so that a diode is integrated in the first groove and the device structure in the second groove are formed simultaneously, an additional photoetching plate or an additional process step is not needed, and the production cost of a power device is reduced.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a trench type power device and a manufacturing method thereof.
Background
With the development of semiconductor technology, power devices require integrated diodes in many cases. Common power devices such as Super Junction (SJ) MOSFETs, Split-Gate-Trench (SGT) MOSFETs, etc. include a diode at the drain and source, which can protect the device. But this protection is lacking between the gate and source, and between the gate and drain of the power device. The anti-Static capability of the power device mainly depends on the capacitance of the gate, the larger the gate capacitance is, the stronger the ESD (Electro-Static discharge) protection capability is, but as the area of the power device becomes smaller and smaller, the smaller the gate capacitance is, the power device is required to integrate an additional ESD protection circuit to improve the anti-Static protection capability of the device. The ESD protection circuit of a power device is typically a pair of diodes interconnected in parallel with their anodes between the gate and source.
Compared with a planar power device, the trench power device has the advantages that the grid electrode of the trench power device is arranged in the trench, so that the Junction Field-Effect Transistor (JFET) Effect can be completely eliminated, and the channel density of the power device is improved. In the conventional technical scheme, a trench power device is integrated with an ESD protection circuit in a manner shown in fig. 1, for example, an N-type trench MOSFET is used, and the structure of the trench power device includes a heavily doped N-type substrate 1, an N-type epitaxial layer on the N-type substrate 1, a P-type channel 2 formed by ion implantation, an oxide layer 3 in the trench, a polysilicon gate 4, an oxide layer 5, a deposited intrinsic polysilicon layer 6, and an N-type source region 7 formed by heavily doped source implantation.
Therefore, the prior art at least has the problems of complex process steps and high manufacturing cost for manufacturing the trench type power device of the integrated diode.
Disclosure of Invention
In view of this, embodiments of the present application provide a trench type power device and a manufacturing method thereof, and aim to solve the problems of complex process steps and high manufacturing cost when manufacturing a trench type power device of an integrated diode.
A first aspect of an embodiment of the present application provides a trench type power device, including at least:
a semiconductor substrate;
the epitaxial layer is positioned on the semiconductor substrate, and the epitaxial layer and the semiconductor substrate are both doped with first conductive type doping ions;
a channel layer on the epitaxial layer, wherein the channel layer is doped with second conductive type dopant ions;
a first trench structure in the channel layer;
the first groove structure comprises a first groove, a first insulating layer covering the inner wall of the first groove and a first polycrystalline material layer positioned in the first groove; the first insulating layer is used for isolating the first polycrystalline material layer from the epitaxial layer, the first polycrystalline material layer comprises at least one P-type doping layer and at least one N-type doping layer, and the directions of the P-type doping layer and the N-type doping layer are parallel to the opening direction of the first groove;
a second trench structure in the channel layer;
the second groove structure comprises a second groove, a second insulating layer covering the inner wall of the second groove and a second polycrystalline material layer positioned in the second groove; the second insulating layer is used for isolating the second polycrystalline material layer from the epitaxial layer, and the second polycrystalline material layer is doped with second conductive type doped ions;
and the active region is arranged on the channel layer and is adjacent to the second groove structure.
In one embodiment, the depth of the first trench is greater than the thickness of the channel layer, and the depth of the second trench is greater than the thickness of the channel layer.
In one embodiment, the width of the first trench is the same as the width of the second trench.
In one embodiment, the at least one P-type doped layer and the at least one N-type doped layer comprise a plurality of P-type doped layers and N-type doped layers alternately arranged.
In one embodiment, the plurality of alternately arranged P-type doped layers and N-type doped layers includes: the first P-type doped layer, the first N-type doped layer, the second P-type doped layer, the second N-type doped layer and the third P-type doped layer are sequentially arranged.
In one embodiment, the trench power device further includes:
a first diode electrode;
the first contact hole is in contact with the first P-type doped layer and used for leading out the first diode electrode;
a second diode electrode;
and the second contact hole is in contact with the third P-type doped layer and is used for leading out the second diode electrode.
A second aspect of an embodiment of the present application provides a method for manufacturing a trench type power device, including:
forming an epitaxial layer on a semiconductor substrate; the epitaxial layer and the semiconductor substrate are both doped with first conductive type doping ions;
forming a channel layer on the epitaxial layer; wherein the channel layer is doped with second conductive type dopant ions;
forming a first trench structure and a second trench structure on the channel layer; the first groove structure comprises a first groove, a first insulating layer covering the inner wall of the first groove, and a first polycrystalline material layer positioned in the first groove; the first insulating layer is used for isolating the first polycrystalline material layer from the epitaxial layer, the first polycrystalline material layer comprises at least one P-type doping layer and at least one N-type doping layer, the directions of the P-type doping layer and the N-type doping layer are parallel to the opening direction of the first groove, the second groove structure comprises a second groove, a second insulating layer covering the inner wall of the second groove, and a second polycrystalline material layer located in the second groove; the second insulating layer is used for isolating the second polycrystalline material layer from the epitaxial layer, and the second polycrystalline material layer is doped with second conductive type doped ions;
an active region is formed on the channel layer adjacent to the second trench structure.
In one embodiment, the forming a first trench structure and a second trench structure on the channel layer includes:
forming the first trench and the second trench on the channel layer;
forming the first insulating layer and the second insulating layer in the first trench and the second trench, respectively;
filling polycrystalline materials in the first groove and the second groove, forming a first polycrystalline material layer in the first groove and a second polycrystalline material layer in the second groove respectively;
an N-type doped region is defined on the first polycrystalline material layer by adopting a first mask, an N-doped region is defined on the active region, and a first P-type doped layer, a first N-type doped layer, a second P-type doped layer, a second N-type doped layer and a third P-type doped layer which are sequentially arranged are formed on the first polycrystalline material layer by injecting N-type doped ions.
In one embodiment, the filling of the first trench and the second trench with a polycrystalline material includes:
filling intrinsic polysilicon in the first trench and the second trench;
and implanting ions of a second conductive type into the intrinsic polycrystalline silicon, and respectively forming a first polycrystalline material layer in the first groove and a second polycrystalline material layer in the second groove.
In one embodiment, after the step of forming an active region on the channel layer adjacent to the second trench structure, the method further includes:
forming a first contact hole and a second contact hole on the first polycrystalline material layer; the first contact hole is in contact with the first P-type doped layer, and the second contact hole is in contact with the third P-type doped layer.
As described above, the trench power device and the manufacturing method thereof of the present application have the following beneficial effects: the diode is arranged in the groove structure, so that the manufacturing complexity and the manufacturing cost are reduced, meanwhile, the power device is compact in structure and superior in performance, and the problems of complex process steps and high manufacturing cost in the process of manufacturing the groove type power device of the integrated diode are solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic structural diagram of a trench type power device integrated diode in the prior art;
fig. 2 is a schematic structural diagram of a trench power device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a first trench structure according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart illustrating a method for manufacturing a trench power device according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating an epitaxial layer formed on a semiconductor substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of forming a first trench structure and a second trench structure according to an embodiment of the present disclosure;
fig. 7 is a flowchart illustrating a method for manufacturing a trench power device according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a first trench structure according to an embodiment of the present disclosure;
FIG. 9 is a flowchart of a method of forming a first layer of polycrystalline material and a second layer of polycrystalline material according to one embodiment of the present disclosure;
fig. 10 is a flowchart illustrating a method for manufacturing a trench type power device according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
The power device needs to integrate a diode in many occasions, the integrated diode can be used as a temperature sensor and can also be used for ESD protection, the anti-static capacity of the power device mainly depends on the capacitance of a grid, the larger the grid capacitance is, the stronger the ESD protection capacity is, but as the area of the power device is smaller and smaller, the grid capacitance is smaller and smaller, and at the moment, the power device is required to integrate an additional ESD protection circuit to improve the anti-static protection capacity of the device. The ESD protection circuit of the power device is usually a pair of diodes with their anodes connected in parallel between the gate and the source, and the structure of the power device integrated diode ESD protection circuit is shown in fig. 1, and by providing a diode D1 and a diode D2, it can be ensured that the leakage current of the gate in the forward direction or the reverse direction is within an acceptable range, and it is usually required to ensure that the leakage current is less than 10 μ a, even 1 μ a under the condition of the highest gate voltage that allows operation. In practical circuits, the diodes D1 and D2 are usually formed by connecting several pairs of diodes in series, respectively, because the withstand voltage of a single diode is usually not high, and the number of diodes in series depends on the highest operating voltage that the gate can tolerate. For 12V devices, two pairs of diodes are connected in series, and for 20V devices, three or four pairs of diodes are connected in series.
Compared with a planar power device, the grid electrode of the groove type power device is arranged in the groove, so that the JFET effect can be completely eliminated, and the channel density of the power device is improved. In the conventional technical scheme, a trench power device is integrated with an ESD protection circuit in a manner shown in fig. 1, for example, an N-type trench MOSFET is used, and the structure of the trench power device includes a heavily doped N-type substrate 1, an N-type epitaxial layer on the N-type substrate 1, a P-type channel 2 formed by ion implantation, an oxide layer 3 in the trench, a polysilicon gate 4, an oxide layer 5, a deposited intrinsic polysilicon layer 6, and an N-type source region 7 formed by heavily doped source implantation.
In order to solve the above problems, a first aspect of the present invention provides a trench type power device of an integrated diode, and referring to fig. 2, fig. 2 is a schematic structural diagram in an XZ plane direction, and includes a semiconductor substrate 100, an epitaxial layer 100 ' on the semiconductor substrate 100, wherein the epitaxial layer 100 ' and the semiconductor substrate 100 are both doped with first conductive type dopant ions, and a channel layer 200 on the epitaxial layer 100 ', wherein the channel layer 200 is doped with second conductive type dopant ions, and the first trench structure 300 in the channel layer 200; the first trench structure 300 includes a first trench 310, a first insulating layer 320 covering an inner wall of the first trench 310, and a first polycrystalline material layer 330 located in the first trench 310; the first insulating layer 320 is used to isolate the first polycrystalline material layer 330 from the epitaxial layer 100', the first polycrystalline material layer 330 includes at least one P-type doped layer and at least one N-type doped layer, the adjacent P-type doped layers and N-type doped layers form PN junctions, and if there are more PN junctions, multiple PN junctions are formed. A second trench structure 400 in which the directions of the P-type doped layer and the N-type doped layer are parallel to the opening direction of the first trench 310 and are located in the channel layer 200; the second trench structure 400 includes a second trench 410, a second insulating layer 420 covering an inner wall of the second trench, a second polycrystalline material layer 430 located in the second trench 410, wherein the second insulating layer 420 is used to isolate the second polycrystalline material layer 430 from the epitaxial layer 100', the second polycrystalline material layer 430 is doped with second conductive type dopant ions, and an active region disposed on the channel layer 200 and adjacent to the second trench structure 400.
In the trench type power device in the embodiment, the diode is integrated in the trench and is formed simultaneously with the trench, so that the device performance is superior, the implementation method is simple, an additional photolithography mask and additional process steps are not required, and the manufacturing complexity and cost are reduced.
In one embodiment, the depth of the first trench 310 is greater than the depth of the channel layer 200, and the depth of the second trench 410 is greater than the depth of the channel layer 200.
In one embodiment, the width of the first trench 310 is the same as the width of the second trench 410.
In one embodiment, the at least one P-doped layer and the at least one N-doped layer comprise a plurality of P-doped layers and N-doped layers alternately disposed.
In one embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of YZ plane direction, where a plurality of P-type doped layers and N-type doped layers alternately arranged include: the first P-type doped layer 331, the first N-type doped layer 332, the second P-type doped layer 333, the second N-type doped layer 334, and the third P-type doped layer 335 are sequentially disposed, wherein the first P-type doped layer 331, the first N-type doped layer 332, the second P-type doped layer 333, the second N-type doped layer 334, and the third P-type doped layer 335 are in contact with each other to form a plurality of PN junctions, so as to form a diode, and the diode is located in the first trench 310 and is formed simultaneously with an active region of the power device structure, i.e., the second trench structure 400, so that a photolithography step is omitted, and the manufacturing cost of the power device is saved.
In one embodiment, referring to fig. 3, the trench type power device further includes a first diode electrode 331b and a second diode electrode 335b, a first contact hole 331a in contact with the first P-type doped layer 331 and a second contact hole 335a in contact with the third P-type doped layer 335, the first contact hole 331a and the second contact hole 335a respectively lead out the first diode electrode 331b and the second diode electrode 335b, and the first diode electrode 331b and the second diode electrode 335b can be respectively used for being in contact with a source and a gate of the power device to serve as an ESD protection diode of the power device.
In one embodiment, the first diode electrode 331b and the second diode electrode 335b may also be not in contact with the source and the gate of the power device, but directly led out to implement a temperature sensor. Generally, the diode forming the ESD protection is usually placed under the gate pad, and the diode forming the temperature sensor is usually placed in the middle of the chip, where the temperature is highest.
In one embodiment, the first conductive type dopant ions are N-type and the second conductive type dopant ions are P-type.
In one embodiment, the polycrystalline material filling the trench is polysilicon.
It can be understood that, if the power device is an N-type device, the first conductivity type dopant ions are N-type and the second conductivity type dopant ions are P-type, or if the power device is a P-type device, the first conductivity type dopant ions are P-type and the second conductivity type dopant ions are N-type.
A second aspect of the embodiments of the present application provides a method for manufacturing a trench type power device, as shown in fig. 4, including:
step S100, as shown in fig. 5, forming an epitaxial layer 100' on the semiconductor substrate 100; wherein, the epitaxial layer 100' and the semiconductor substrate 100 are doped with first conductive type doping ions;
in one embodiment, in order to reduce the back-diffusion of the semiconductor substrate 100, an arsenic substrate is generally used; however, since the substrate resistivity of arsenic is usually higher than that of phosphorus, a phosphorus substrate may be used in order to lower the substrate resistivity. The back-diffusion of the phosphorus substrate is more severe and thus the thickness of the epitaxial layer 100' needs to be increased appropriately. The thickness and doping concentration of the epitaxial layer 100' determine the breakdown voltage of the power device.
Step S200, with reference to fig. 6, forming a channel layer 200 on the epitaxial layer 100'; wherein the channel layer 200 is doped with second conductive type dopant ions;
step S300, with reference to fig. 6, forming a first trench structure 300 and a second trench structure 400 on the channel layer 200;
in conjunction with the schematic structure of the first trench structure 300 in the YZ plane direction shown in fig. 3, the first trench structure 300 includes a first trench 310, a first insulating layer 320 covering an inner wall of the first trench 310, and a first polycrystalline material layer 330 located in the first trench 310;
the first insulating layer 320 is used to isolate the first polycrystalline material layer 330 from the epitaxial layer 100', the first polycrystalline material layer 330 includes at least one P-type doped layer and at least one N-type doped layer, the adjacent P-type doped layers and N-type doped layers form PN junctions, if there are more PN junctions, the P-type doped layers and N-type doped layers are parallel to the opening direction of the first trench 310.
The second trench structure 400 includes a second trench 410, a second insulating layer 420 covering an inner wall of the second trench 410, and a second polycrystalline material layer 430 located in the second trench 410; the second insulating layer 420 is used to isolate the second polycrystalline material layer 430 from the epitaxial layer 100', and the second polycrystalline material layer 430 is doped with second conductive type dopant ions;
the first trench structure 300 is used to form a diode, and the second trench structure 400 is used to form an active region of a power device.
In one embodiment, the first insulating layer 320 and the second insulating layer 420 are typically formed by oxidation, such as silicon dioxide.
In one embodiment, the first polycrystalline material layer 330 and the second polycrystalline material layer 430 are formed by filling P-type polysilicon directly.
In step S400, an active region is formed on the channel layer 200 adjacent to the second trench structure 400.
In one embodiment, a mask is used to implant N-type heavily doped dopant ions, the implantation energy is usually 30-100 keV, the implantation dose is usually 1e 15-1 e16/cm2, and the implanted impurity is usually arsenic or phosphorus. In the active region, an N-type source is formed, which is similar to the conventional method for manufacturing a trench MOSFET and will not be described herein.
It is to be understood that the formation of the N-type region of the diode, i.e., the N-type doped layer, in the first trench 310 is performed simultaneously with the N-type source.
In one embodiment, forming the first trench structure 300 and the second trench structure 400 on the channel layer 200, as shown in fig. 7, includes:
step S310, in conjunction with fig. 6, forming a first trench 310 and a second trench 410 on the channel layer 200;
step S320, as shown in fig. 6, forming a first insulating layer 320 and a second insulating layer 420 in the first trench 310 and the second trench 410, respectively;
step S330, with reference to fig. 6, filling polycrystalline material in the first trench 310 and the second trench 410, forming a first polycrystalline material layer 330 in the first trench 310 and a second polycrystalline material layer 430 in the second trench 410, respectively;
step S340, with reference to fig. 8, defining an N-type doped region on the first polycrystalline material layer 330 by using a first mask, defining an N-doped region on the active region, and forming a first P-type doped layer 331, a first N-type doped layer 332, a second P-type doped layer 333, a second N-type doped layer 334, and a third P-type doped layer 335 on the first polycrystalline material layer 330 by implanting N-type dopant ions, wherein the first P-type doped layer 331, the first N-type doped layer 332, the second P-type doped layer 333, the second N-type doped layer 334, and the third P-type doped layer 335 are in contact with each other to form a plurality of PN junctions.
Referring to fig. 8, a schematic structural diagram of the first trench structure 300 in the YZ plane direction, the first trench structure 300 includes a first trench 310, a first insulating layer 320 covering an inner wall of the first trench 310, and a first polycrystalline material layer 330 located in the first trench 310;
the first insulating layer 320 is used to isolate the first poly-crystalline material layer 330 from the epitaxial layer 100', and the first poly-crystalline material layer 330 includes a first P-type doped layer 331, a first N-type doped layer 332, a second P-type doped layer 333, a second N-type doped layer 334, and a third P-type doped layer 335 sequentially disposed. The second trench structure 400 includes a second trench 410, a second insulating layer 420 covering an inner wall of the second trench 410, and a second polycrystalline material layer 430 located in the second trench 410; the second insulating layer 420 is used to isolate the second polycrystalline material layer 430 from the epitaxial layer 100', and the second polycrystalline material layer 430 is doped with second conductive type dopant ions;
the first trench structure 300 is used to form a diode, and the second trench structure 400 is used to form an active region of a power device.
In one embodiment, filling the first trench 310 and the second trench 410 with a polycrystalline material, as shown in fig. 9, includes:
step S331, filling intrinsic polysilicon in the first trench 310 and the second trench 410;
in step S332, ions of the second conductive type are implanted into the intrinsic polysilicon to form a first polycrystalline material layer 330 in the first trench 310 and a second polycrystalline material layer 430 in the second trench 410, respectively.
In one embodiment, the energy of the second conductive type ion is usually 30-60 keV, the implantation dose is usually 1e 14-1 e15/cm2, and the implanted impurity is boron. Because boron diffuses through the surface of the polysilicon through the oxide, thereby affecting the threshold, in order to reduce this effect, phosphorus may be implanted first, the energy is 40-80 keV, the implantation dose is between 1e 13-5 e14 cm2, the finally formed first polycrystalline material layer 330 and second polycrystalline material layer 430 are still P-type due to the concentration difference between boron and phosphorus, and then impurities are diffused in the polysilicon through a thermal process. The temperature is usually 900 to 1000 ℃ and the time is 30 to 120 minutes.
In one embodiment, the first conductive type dopant ions are N-type and the second conductive type dopant ions are P-type.
In one embodiment, after the step of forming an active region on the channel layer 200 adjacent to the second trench structure 400, as shown in fig. 10, the method further includes:
step S500, with reference to FIG. 3, forming a first contact hole 331a and a second contact hole 335a in the first polycrystalline material layer 330; here, the first contact hole 331a contacts the first P-type impurity layer 331 for drawing out the first diode electrode 331b, and the second contact hole 335a contacts the third P-type impurity layer 335 for drawing out the second diode electrode 335 b.
In one embodiment, the first contact hole 331a and the second contact hole 335a respectively lead out a first diode electrode 331b and a second diode electrode 335b, and the first diode electrode 331b and the second diode electrode 335b can be respectively used for contacting with a source and a gate of a power device, which is an ESD protection diode of the power device.
In one embodiment, the first diode electrode 331b and the second diode electrode 335b may also be not in contact with the source and the gate of the power device, but directly led out to implement a temperature sensor.
It will be appreciated that the diode forming the ESD protection is typically placed under the gate pad of the power device, and the diode forming the temperature sensor is typically placed in the middle of the chip, where its temperature is highest.
For the MOSFET device manufactured by the above-mentioned manufacturing method, the gate is P-type, and the resistance of the P-type gate is higher than that of the conventional N-type gate because the mobility of holes is lower than that of electrons. Meanwhile, under the same structure, for example, under the condition that the thickness of the oxide layer and the doping concentration of the channel layer are the same, the threshold voltage of the P-type gate is about 1.1V higher than the threshold voltage of the N-type gate, which is helpful for realizing a high-threshold MOSFET, but for a low-threshold MOSFET device, the P-type gate MOSFET can only reduce the doping concentration of the channel, which easily causes the low doping concentration of the channel, and the device is easy to punch through or has high leakage.
In one embodiment, the width of the first trench 310 is the same as the width of the second trench 410.
In one embodiment, the width of the first trench 310 is different from the width of the second trench 410, and the width of the first trench 310 and the width of the second trench 410 of the diode can be changed arbitrarily.
In one embodiment, to improve the ESD protection capability, the power device may include a plurality of first trench structures 300 forming diodes with the same structure, and the ESD protection capability of the high power device is connected in parallel through the diodes.
It is understood that, in the present embodiment, an N-type MOSFET is taken as an example, and the manufacturing method provided in the present embodiment may also be suitable for a P-type MOSFET.
The structure of the trench type power device and the manufacturing method of the trench type power device in this embodiment are suitable for a trench type MOSFET, an SGTMOSFET, an sjfet, an IGBT, and the like.
If the MOSFET is subsequently made of silicon carbide, the structure in this embodiment is also applicable, provided that the gate is of a trench structure.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A trench power device, comprising:
a semiconductor substrate;
the epitaxial layer is positioned on the semiconductor substrate, and the epitaxial layer and the semiconductor substrate are both doped with first conductive type doping ions;
a channel layer on the epitaxial layer, wherein the channel layer is doped with second conductive type dopant ions;
a first trench structure in the channel layer;
the first groove structure comprises a first groove, a first insulating layer covering the inner wall of the first groove and a first polycrystalline material layer positioned in the first groove; the first insulating layer is used for isolating the first polycrystalline material layer from the epitaxial layer, the first polycrystalline material layer comprises at least one P-type doping layer and at least one N-type doping layer, and the directions of the P-type doping layer and the N-type doping layer are parallel to the opening direction of the first groove;
a second trench structure in the channel layer;
the second groove structure comprises a second groove, a second insulating layer covering the inner wall of the second groove and a second polycrystalline material layer positioned in the second groove; the second insulating layer is used for isolating the second polycrystalline material layer from the epitaxial layer, and the second polycrystalline material layer is doped with second conductive type doped ions;
and the active region is arranged on the channel layer and is adjacent to the second groove structure.
2. The trench power device of claim 1 wherein a depth of the first trench is greater than a thickness of the channel layer and a depth of the second trench is greater than the thickness of the channel layer.
3. The trench power device of claim 1 wherein a width of the first trench is the same as a width of the second trench.
4. The trench power device of claim 1 wherein the at least one P-doped layer and the at least one N-doped layer comprise a plurality of alternating P-doped and N-doped layers.
5. The trench power device of claim 4 wherein the plurality of alternating P-doped and N-doped layers comprises: the first P-type doped layer, the first N-type doped layer, the second P-type doped layer, the second N-type doped layer and the third P-type doped layer are sequentially arranged.
6. The trench power device of claim 5 further comprising:
a first diode electrode;
the first contact hole is in contact with the first P-type doped layer and used for leading out the first diode electrode;
a second diode electrode;
and the second contact hole is in contact with the third P-type doped layer and is used for leading out the second diode electrode.
7. A manufacturing method of a trench type power device comprises the following steps:
forming an epitaxial layer on a semiconductor substrate; the epitaxial layer and the semiconductor substrate are both doped with first conductive type doping ions;
forming a channel layer on the epitaxial layer; wherein the channel layer is doped with second conductive type dopant ions;
forming a first trench structure and a second trench structure on the channel layer; the first groove structure comprises a first groove, a first insulating layer covering the inner wall of the first groove, and a first polycrystalline material layer positioned in the first groove; the first insulating layer is used for isolating the first polycrystalline material layer from the epitaxial layer, the first polycrystalline material layer comprises at least one P-type doping layer and at least one N-type doping layer, the directions of the P-type doping layer and the N-type doping layer are parallel to the opening direction of the first groove, the second groove structure comprises a second groove, a second insulating layer covering the inner wall of the second groove, and a second polycrystalline material layer located in the second groove; the second insulating layer is used for isolating the second polycrystalline material layer from the epitaxial layer, and the second polycrystalline material layer is doped with second conductive type doped ions;
an active region is formed on the channel layer adjacent to the second trench structure.
8. The method of manufacturing of claim 7, wherein the forming a first trench structure and a second trench structure on the channel layer comprises:
forming the first trench and the second trench on the channel layer;
forming the first insulating layer and the second insulating layer in the first trench and the second trench, respectively;
filling polycrystalline materials in the first groove and the second groove, forming a first polycrystalline material layer in the first groove and a second polycrystalline material layer in the second groove respectively;
an N-type doped region is defined on the first polycrystalline material layer by adopting a first mask, an N-doped region is defined on the active region, and a first P-type doped layer, a first N-type doped layer, a second P-type doped layer, a second N-type doped layer and a third P-type doped layer which are sequentially arranged are formed on the first polycrystalline material layer by injecting N-type doped ions.
9. The method of manufacturing of claim 8, wherein filling the first trench and the second trench with a polycrystalline material comprises:
filling intrinsic polysilicon in the first trench and the second trench;
and implanting ions of a second conductive type into the intrinsic polycrystalline silicon, and respectively forming a first polycrystalline material layer in the first groove and a second polycrystalline material layer in the second groove.
10. The method of manufacturing of claim 8, wherein after the step of forming an active region on the channel layer adjacent to the second trench structure, further comprising:
forming a first contact hole and a second contact hole on the first polycrystalline material layer; the first contact hole is in contact with the first P-type doped layer, and the second contact hole is in contact with the third P-type doped layer.
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| CN116779666A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | IGBT chip with ESD structure and manufacturing method thereof |
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| CN113035714A (en) * | 2019-12-25 | 2021-06-25 | 华润微电子（重庆）有限公司 | Groove type power device and manufacturing method thereof |
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Application publication date: 20220301 |