CN110459539B - Shielded gate trench MOSFET integrated with ESD protection and method of manufacture - Google Patents

Shielded gate trench MOSFET integrated with ESD protection and method of manufacture Download PDF

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CN110459539B
CN110459539B CN201910722915.6A CN201910722915A CN110459539B CN 110459539 B CN110459539 B CN 110459539B CN 201910722915 A CN201910722915 A CN 201910722915A CN 110459539 B CN110459539 B CN 110459539B
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polysilicon
type
groove
gate
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CN110459539A (en
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潘光燃
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Shenzhen Semi One Technology Co ltd
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Shenzhen Semi One Technology Co ltd
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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Abstract

The invention discloses a shielding gate trench MOSFET integrated with ESD protection and a manufacturing method, which are realized by two layers of polysilicon and a lower cost method, wherein the polysilicon forming the shielding gate of the MOSFET and the polysilicon forming the ESD protection diode of the MOSFET are the same layer of polysilicon (first layer of polysilicon), and the polysilicon forming the grid of the MOSFET is second layer of polysilicon; the device structure of the shielded gate trench MOSFET integrated with the ESD protection can be realized by only a two-layer polysilicon method in the whole manufacturing process, compared with the traditional method, the method for realizing the device structure is simpler, the manufacturing complexity and the method cost are reduced, and the method has great progress in the prior art.

Description

Shielded gate trench MOSFET integrated with ESD protection and method of manufacture
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a shielded gate trench MOSFET integrated with ESD protection and a manufacturing method thereof.
Background
For the traditional power MOSFET device, a certain compromise relationship exists between the on-resistance (Ron) of the device and the breakdown voltage of the source and the drain, and the development of the power MOSFET device is limited for a long time. The shielded gate trench MOSFET utilizes the charge balance principle, so that the N-type drift region can realize higher breakdown voltage of the device even under the condition of higher doping concentration, thereby obtaining low on-resistance and breaking the silicon limit of the traditional power MOSFET. On the other hand, the device performance of the shielded gate trench MOSFET is significantly better than that of the normal trench MOSFET and the planar MOSFET because the shielded gate greatly reduces the capacitance (Cgd) between the gate and the drain.
In a power transmission or conversion system, low on-resistance (Ron) means low on-loss, low gate-drain capacitance (Cgd) means low switching loss, that is, shielding gate trench MOSFET reduces both on-loss and switching loss of the system, self-power consumption is smaller, and power transmission/power conversion efficiency of the system is higher.
A thin gate oxide layer exists between the gate and source of the MOSFET, which is damaged by breakdown and is not recoverable when subjected to an external, unexpected high voltage surge. It is therefore necessary in some practical applications to provide electrostatic discharge (ESD) protection to the gate of the MOSFET. It is common practice to connect a diode protection unit in parallel between the gate and source of the MOSFET, when the voltage generated by electrostatic discharge (ESD) is higher than the breakdown voltage of the diode (which is lower than the breakdown voltage value of the gate oxide layer of the MOSFET), the diode undergoes avalanche breakdown, and electrostatic energy is released from the diode, thereby avoiding the gate oxide layer between the gate and the source from being damaged. In order to reduce the size and material costs of the circuit board, diodes that provide ESD protection are typically integrated into MOSFET devices.
U.S. patent TrenchMOSFETSwithZenerDiode, publication number US8004009B2, discloses a MOSFET structure and method of fabrication that integrates an ESD protection diode, including a Cell region (Cell), a Gate (Gate) extraction region, and an ESD protection diode integrated therebetween; the ESD protection diode is arranged on the upper surface of a thick oxide layer and is formed by connecting a plurality of PN junctions arranged in polysilicon in series; source metal (SourceMetal) connects the cell and one end of the ESD protection diode together and gate metal (GATEMETAL) connects the gate and the other end of the ESD protection diode together.
Generally, in the manufacturing method of the MOSFET integrated with ESD protection, in addition to the polysilicon used to form the gate, another layer of polysilicon is required to manufacture the ESD protection diode; in the manufacturing method of the shielded gate trench MOSFET, another layer of polysilicon is needed to manufacture the shielded gate connected with the source, and if the shielded gate trench MOSFET needs to integrate ESD protection, three layers of polysilicon are needed to realize.
Disclosure of Invention
In view of the limitations of the prior art, the present invention aims to overcome the defects of the prior art, and adapt to the actual needs, and provides a shielded gate trench MOSFET integrated with ESD protection and a manufacturing method thereof, which are realized by a two-layer polysilicon, lower cost method process.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows:
The invention firstly discloses a shielded gate trench MOSFET integrated with ESD protection, which comprises an N-type epitaxial layer (2); the N-type epitaxial layer (2) is positioned on the N-type substrate (1), a first groove (4.1), a second groove (4.2) and a third groove (4.3) are formed in the N-type epitaxial layer (2), a first polysilicon gate (8.1), a second polysilicon gate (8.2) and a third polysilicon gate (8.3) are respectively filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3), the first polysilicon gate (8.1) and the second polysilicon gate (8.2) are surrounded by the lining layer (5), and the first polysilicon gate (8.1) and the second polysilicon gate (8.2) are connected with the third polysilicon gate (8.3) in the chip;
A second layer of polysilicon (10) is respectively arranged in the first groove (4.1) above the first polysilicon gate (8.1) and the second polysilicon gate (8.2), a gate oxide layer (9) is respectively arranged between the first groove (4.1) and the second groove (4.2) which are positioned on the side wall of the second layer of polysilicon (10) and the side area of the first groove (4.1), an N type heavily doped region (12) and a P type lightly doped body region (11) are filled between the gate oxide layer (9) and the N type epitaxial layer (2), wherein the N type heavily doped region (12) is positioned above the P type lightly doped body region (11);
the top of the third polysilicon gate (8.3) extends to the outside of the third groove (4.3), the periphery of the third polysilicon gate positioned in the third groove (4.3) is also positioned in the third groove (4.3) through the lining layer (5), the top of the third polysilicon gate (8.3) is also provided with a gate oxide layer (9), and the gate oxide layer (9) positioned at the top of the third polysilicon gate (8.3) is contacted with the lining layer (5) and surrounds the third polysilicon gate (8.3);
The inner liner layer (5) at the third groove (4.3) extends outwards horizontally and ends at the edge of the second groove (4.2), and a hard mask layer (3) is filled below the inner liner layer (5) outside the third groove (4.3) and is arranged above the N-type epitaxial layer (2) through the hard mask layer (3);
An ESD protection diode surrounded by an insulating layer is arranged on the lining layer (5) at the side part of the third groove (4.3); a dielectric layer (14) is arranged on the gate oxide layer;
The semiconductor device further comprises a source metal sheet (15.1), wherein the source metal sheet (15.1) is positioned above the dielectric layer (14) and extends out of two ends, one end of the source metal sheet penetrates through the hard mask layer (14) and the gate oxide layer (9) and then enters the first polysilicon gate (8.1), the second polysilicon gate (8.2) or the third polysilicon gate (8.3), and the other end of the source metal sheet penetrates through the hard mask layer (14) and the gate oxide layer (9) and then enters the P-type lightly doped body region (11);
The semiconductor device further comprises two ESD protection diode connection metal layers, wherein the two ESD protection diode connection metal layers penetrate through the hard mask layer respectively and then are connected with two poles of the ESD protection diode.
The first polysilicon gate (8.1), the second polysilicon gate (8.2) and the third polysilicon gate (8.3) are heavily doped with N type, the doping is phosphorus atoms or arsenic atoms or antimony atoms, and the doping concentration is 1E 15-2E 16 per square centimeter.
The first layer of polysilicon (7) is lightly doped in P type, the dopant is boron atoms, and the doping concentration is 1E14 to 1E15 per square centimeter.
The second layer of polysilicon (10) is heavily doped with N type, the dopant is phosphorus atom or arsenic atom or antimony atom, and the doping concentration is 1E 15-2E 16 per square centimeter.
The ESD protection diode is composed of a P-type lightly doped first layer polysilicon (7) and an N-type heavily doped first layer polysilicon (13), wherein the P-type lightly doped first layer polysilicon (7) is positioned in the middle of the N-type heavily doped first layer polysilicon (13), and the P-type lightly doped first layer polysilicon and the N-type heavily doped first layer polysilicon are surrounded by the insulating layer, and the insulating layer is a gate oxide layer (7); the two ESD protection diode connection metal layers respectively penetrate through the dielectric layer (14) and the gate oxide layer 9) and then respectively enter the N-type heavily doped first layer polysilicon (13) at the two ends of the P-type lightly doped first layer polysilicon.
The lining layer (5) is silicon oxide or silicon nitride or an overlapped layer formed by the silicon oxide and the silicon nitride; the gate oxide layer (9) is silicon oxide.
Further, the invention also discloses a manufacturing method of the shielding gate trench MOSFET integrated with the ESD protection, which is used for manufacturing the shielding gate trench MOSFET integrated with the ESD protection, and comprises the following steps:
(1) Forming a lightly doped N-type epitaxial layer (2) on the N-type heavily doped substrate (1);
(2) Forming a hard mask layer (3) on the upper surface of the N-type epitaxial layer;
(3) Forming a first trench (4.1), a second trench (4.2) and a third trench (4.3);
(4) Forming a non-conductive dielectric layer on the inner wall of the groove and the upper surface of the hard mask layer to serve as an inner liner layer (5);
(5) Forming a first layer of polysilicon (6) over the liner layer (5);
(6) P-type lightly doped first layer polysilicon (7) is formed on the surface layer of the first layer polysilicon (6);
(7) Carrying out N-type heavy doping on partial areas of the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) and forming an N-type heavy doped first layer of polysilicon (8);
(8) And (3) annealing and driving and diffusing the dopants in the first layer of polysilicon (6) to enable the first layer of polysilicon (6) filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3) to be heavily doped in the N type.
(9) Removing the first polysilicon layer (6) above the first groove (4.1) and the second groove (4.2) and part of the first polysilicon layer (6) in the first groove (4.1) and the second groove (4.2) and forming N-type heavily doped first polysilicon layer (8.1) and second polysilicon gate (8.2) and third polysilicon gate (8.3) filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3), and simultaneously forming P-type lightly doped first polysilicon layer (7) positioned on the upper surface of the hard mask layer (3);
(10) Forming a non-conductive dielectric layer on the upper surfaces of the first layer of polysilicon (8.1) and the second polysilicon gate (8.2), wherein the dielectric layer and the inner liner layer surround the first layer of polysilicon (8.1) and the second polysilicon gate (8.2);
(11) Forming a gate oxide layer (9) on the surfaces of the first groove (4.1), the second groove (4.2), the protruding surface of the third polysilicon gate (8.3) and the surface of the P-type lightly doped first layer polysilicon (7);
(12) Growing a second layer of polysilicon (10) in the first groove (4.1) and the second groove (4.2) by adopting a chemical vapor deposition method, wherein the second layer of polysilicon (10) is N-type heavily doped polysilicon;
(13) Forming a P-type lightly doped body region (11) in the surface layer of the N-type epitaxial layer (2);
(14) Forming an N-type heavy doping region (12) in the upper surface layer of the P-type light doping body region (11), and synchronously, carrying out N-type heavy doping on the two end regions of the P-type light doping first layer polysilicon (7) to form an N-type heavy doping first layer polysilicon (13); at the moment, the P-type lightly doped polysilicon (7) and the N-type heavily doped polysilicon (13) form an ESD protection diode of an NPN structure;
(15) Forming a dielectric layer (14), a metal layer and an ESD protection diode connection metal layer; the metal layer is source metal (15.1) and is provided with two end parts, one end of the metal layer enters the first layer of polysilicon (8.1) and the second polysilicon gate (8.2) or the third polysilicon gate (8.3), and the other end of the metal layer enters the P-type lightly doped body region (11);
The ESD protection diode connection metal layer comprises a first metal layer (15.2) and a second metal layer (15.3), wherein the first metal layer (15.2) and the second metal layer (15.3) respectively enter N-type heavily doped polysilicon (13) at two sides of the P-type lightly doped polysilicon (7).
In the step (2), the hard mask layer is silicon oxide, silicon nitride, or an overlapped layer formed by silicon oxide and silicon nitride. .
In the step (3), a photoetching and etching method is adopted.
In the step (4), an oxidation method or a chemical vapor deposition method is adopted.
In the step (5), undoped first layer polysilicon (6) is grown by adopting a chemical vapor deposition method.
In the step (6), the surface layer of the first layer of polysilicon (6) is lightly doped with P type by adopting an ion implantation method, wherein the doping is boron atoms, and the doping concentration is 1E14 to 1E15 per square centimeter.
In the step (7), the partial areas of the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) are subjected to N-type heavy doping by adopting a photoetching and ion implantation method, wherein the doping is phosphorus atoms or arsenic atoms or antimony atoms, and the doping concentration is 1E 15-2E 16 per square centimeter.
In the step (8), a high-temperature diffusion method is adopted to anneal and drive in and diffuse dopants in the first layer of polysilicon (6), and after the dopants are diffused, the first layer of polysilicon is fully lightly doped with P type and heavily doped with N type: the first layer of polysilicon (6) filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3), the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) are heavily doped in N type, and the first layer of polysilicon (6) in other areas are lightly doped in P type.
In the step (9), a photoetching and etching method is adopted.
In the step (10), an oxidation method or a chemical vapor deposition method and a silicon oxide etching method are adopted, and the dielectric layer is silicon oxide.
In step (11), the gate oxide layer (9) is grown by an oxidation method.
In the step (12), the second layer of polysilicon is grown by adopting a chemical vapor deposition method, and meanwhile, the second layer of polysilicon (10) except the first groove (4.1) and the second groove (4.2) is removed by adopting an etching method.
In the step (13), ion implantation and annealing are adopted.
In the step (14), an N-type heavy doping region (12) is formed in the upper surface layer of the P-type light doping body region (11) by adopting photoetching, ion implantation and annealing methods, and N-type heavy doping is carried out on the two end regions of the P-type light doping first layer polysilicon (7) synchronously to form an N-type heavy doping first layer polysilicon (13).
The invention has the beneficial effects that:
In the manufacturing method disclosed by the invention, the polysilicon forming the MOSFET shielding gate and the polysilicon forming the ESD protection diode of the MOSFET are the same layer of polysilicon (first layer of polysilicon), and the polysilicon forming the grid electrode of the MOSFET is the second layer of polysilicon; the device structure of the shielded gate trench MOSFET integrated with the ESD protection can be realized by only a two-layer polysilicon method in the whole manufacturing process, compared with the traditional method, the method for realizing the device structure is simpler, the manufacturing complexity and the method cost are reduced, and the method has great progress in the prior art.
Drawings
FIG. 1 shows the structure corresponding to step (1) in the method of the present invention;
FIG. 2 shows the structure corresponding to step (2) in the method of the present invention;
FIG. 3 shows the structure corresponding to step (3) in the method of the present invention;
FIG. 4 shows the structure corresponding to step (4) in the method of the present invention;
FIG. 5 shows the structure corresponding to step (5) in the method of the present invention;
FIG. 6 shows the structure corresponding to step (6) in the method of the present invention;
FIG. 7 shows the structure corresponding to step (7) in the method of the present invention;
FIG. 8 shows the structure corresponding to step (8) in the method of the present invention;
FIG. 9 shows the structure corresponding to step (9) in the method of the present invention;
FIG. 10 shows the structure corresponding to step (10) in the method of the present invention;
FIG. 11 shows the structure corresponding to step (11) in the method of the present invention;
FIG. 12 shows the structure corresponding to step (12) in the method of the present invention;
FIG. 13 shows the structure corresponding to step (13) in the method of the present invention;
FIG. 14 shows the structure corresponding to step (14) in the method of the present invention;
fig. 15 is a cross-sectional view of a shielded gate trench MOSFET with integrated ESD protection according to the invention, and a structure corresponding to step (13) in the method according to the invention.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
Example 1: a shielded gate trench MOSFET integrated with ESD protection, see fig. 15.
A shielded gate trench MOSFET integrated with ESD protection comprising an N-type epitaxial layer 2; the N-type epitaxial layer 2 is located on the N-type substrate 1, a first groove 4.1, a second groove 4.2 and a third groove 4.3 are formed in the N-type epitaxial layer 2, a first polysilicon gate 8.1, a second polysilicon gate 8.2 and a third polysilicon gate 8.3 are respectively filled in the first groove 4.1, the second groove 4.2 and the third groove 4.3, wherein the first polysilicon gate 8.1 and the second polysilicon gate 8.2 are surrounded by the liner 5, and the first polysilicon gate 8.1, the second polysilicon gate 8.2 and the third polysilicon gate 8.3 are connected with each other inside the chip.
Further, a second layer of polysilicon 10 is respectively disposed in the first trench 4.1 above the first polysilicon gate 8.1 and the second polysilicon gate 8.2, a gate oxide layer 9 is respectively disposed between the sidewall of the second layer of polysilicon 10 and the first trench 4.1 and the second trench 4.2 in the side region of the first trench 4.1, and an N-type heavily doped region 12 and a P-type lightly doped region 11 are filled between the gate oxide layer 9 and the N-type epitaxial layer 2, wherein the N-type heavily doped region 12 is disposed above the P-type lightly doped region 11.
Further, the top of the third polysilicon gate 8.3 extends to the outside of the third trench 4.3, the periphery of the third polysilicon gate located in the third trench 4.3 is also located in the third trench 4.3 through the liner 5, the top of the third polysilicon gate 8.3 is also provided with the gate oxide layer 9, and the gate oxide layer 9 located at the top of the third polysilicon gate 8.3 contacts with the liner 5 and surrounds the third polysilicon gate 8.3.
Further, the liner layer 5 at the third trench 4.3 extends horizontally outwards and ends at the edge of the second trench 4.2, and the hard mask layer 3 is filled under the liner layer 5 outside the third trench 4.3 and is placed on the N-type epitaxial layer 2 through the hard mask layer 3.
Further, an ESD protection diode surrounded by an insulating layer is disposed on the liner layer 5 at the side of the third trench 4.3; a dielectric layer 14 is provided over the gate oxide layer.
Further, the semiconductor device further includes a source metal sheet 15.1, wherein the source metal sheet 15.1 is located above the dielectric layer 14 and extends out of two ends, one end of the source metal sheet penetrates through the hard mask layer 14 and the gate oxide layer 9 and then enters the first polysilicon gate 8.1, the second polysilicon gate 8.2 or the third polysilicon gate 8.3, and the other end penetrates through the hard mask layer 14 and the gate oxide layer 9 and then enters the P-type lightly doped body region 11.
Further, the semiconductor device further comprises two ESD protection diode connection metal layers, wherein the two ESD protection diode connection metal layers penetrate through the hard mask layer and are connected with two poles of the ESD protection diode respectively, the ESD protection diode is composed of a P-type lightly doped first layer polysilicon 7 and an N-type heavily doped first layer polysilicon 13, the P-type lightly doped first layer polysilicon 7 is located in the middle of the N-type heavily doped first layer polysilicon 13, the P-type lightly doped first layer polysilicon and the N-type heavily doped first layer polysilicon are surrounded by the insulating layer, and the insulating layer is a gate oxide layer 7; the two ESD protection diode connection metal layers respectively penetrate through the dielectric layer 14 and the gate oxide layer 9 and then respectively enter the N-type heavily doped first layer polysilicon 13 at the two ends of the P-type lightly doped first layer polysilicon. The P-type lightly doped polysilicon 7 and the N-type heavily doped polysilicon 13 form an ESD protection diode of an NPN structure, where the ESD protection diode includes at least two PN junctions, or may be a series connection of more PN junctions, such as NPNPNPN structures. The first metal layer (15.2) and the second metal layer (15.3) are metals connected with two ends of the ESD protection diode, wherein one end of the metal is connected to the source electrode of the MOSFET, the other end of the metal is connected to the grid electrode of the MOSFET, namely, the ESD protection diode is connected between the grid electrode and the source electrode of the MOSFET in parallel, and the purpose of ESD protection is achieved, namely, the source electrode (the N-type heavily doped region 12) of the MOSFET and the third polysilicon gate 8.3 are short-circuited. The third polysilicon gate 8.3 is communicated with the first polysilicon gate 8.1 and the second polysilicon gate 8.2 in the chip, namely, the first polysilicon gate 8.1 and the second polysilicon gate 8.2 are in short circuit with the source electrode, so that the purpose of shielding the gate structure is achieved.
In the above structure, the first polysilicon gate 8.1 and the second polysilicon gate 8.2 are shielding gates of the MOSFET surrounded by the insulating layer, the second layer polysilicon 10 filled in the first trench 4.1 and the second trench 4.2 forms a gate of the MOSFET, the N-type heavily doped region 12 is a source of the MOSFET,
Further, the first polysilicon gate 8.1, the second polysilicon gate 8.2 and the third polysilicon gate 8.3 are heavily doped with N type, the dopant is phosphorus atom or arsenic atom or antimony atom, and the doping concentration is 1E15 to 2E16 per square centimeter. The first layer of polysilicon 7 is lightly doped with P type dopant which is boron atoms and has doping concentration of 1E14 to 1E15 per square centimeter. The second layer of polysilicon 10 is heavily doped with N type, the dopant is phosphorus atom or arsenic atom or antimony atom, and the doping concentration is 1E 15-2E 16 per square centimeter. The lining layer 5 is silicon oxide or silicon nitride or an overlapped layer formed by the silicon oxide and the silicon nitride; the gate oxide layer 9 is silicon oxide.
Embodiment 2 of the present invention further discloses a method for manufacturing an ESD protection integrated shielded gate trench MOSFET, for manufacturing the ESD protection integrated shielded gate trench MOSFET as described above, see fig. 1 to 15, comprising the steps of:
(1) Forming a lightly doped N-type epitaxial layer 2 on the N-type heavily doped substrate 1; as in fig. 1.
(2) A hard mask layer 3 is formed on the upper surface of the N-type epitaxial layer 2, the hard mask layer being silicon oxide, or silicon nitride, or an overlying layer of silicon oxide and silicon nitride, as shown in fig. 2.
(3) Forming grooves by adopting a photoetching and etching method, wherein the grooves comprise a first groove 4.1, a second groove 4.2 and a third groove 4.3; as in fig. 3.
(4) An oxidation method or a chemical vapor deposition method is adopted to form a non-conductive dielectric layer on the inner wall of the groove to serve as an inner liner layer 5, wherein the inner liner layer is silicon oxide or silicon nitride or an overlapped layer formed by the silicon oxide and the silicon nitride, as shown in fig. 4.
(5) A first layer of polysilicon 6 is grown over the liner layer 5 by chemical vapor deposition, the first layer of polysilicon 6 being undoped polysilicon during growth, as shown in fig. 5.
(6) And carrying out P-type light doping on the surface layer of the first layer of polysilicon 6 by adopting an ion implantation method to form a P-type light doped first layer of polysilicon 7 (the surface layer area shown in the figure 7 is the P-type light doped first layer of polysilicon 7), wherein the doping is boron atoms, and the doping concentration is 1E14 to 1E15 per square centimeter, as shown in figure 6.
(7) And carrying out N-type heavy doping on partial areas of the P-type lightly doped first layer polysilicon 7 above the first groove 4.1, the second groove 4.2 and the third groove (4.3) by adopting a photoetching and ion implantation method to form N-type heavily doped first layer polysilicon 8 (the surface layer area shown in the figure is N-type heavily doped first layer polysilicon 8), wherein the doping is phosphorus atoms or arsenic atoms or antimony atoms, and the doping concentration is 1E 15-2E 16 per square centimeter, as shown in figure 7.
(8) Annealing and driving diffusion are carried out on the dopant in the first layer of polysilicon 6 by adopting a high-temperature diffusion method, and after the dopant is diffused, the first layer of polysilicon 6 is fully lightly doped by P type or heavily doped by N type: the first layer of polysilicon filled in the first, second and third trenches 4.1, 4.2, 4.3 is heavily doped with N-type, and the other regions are lightly doped with P-type first layer of polysilicon 7, as shown in fig. 8.
(9) Removing the first layer of polysilicon 6 above the first groove 4.1 and the second groove 4.2 and in partial areas of the inner parts of the first groove 4.1 and the second groove 4.2 by adopting a photoetching and etching method to form N-type heavily doped first layer of polysilicon 8.1, second polysilicon gate 8.2 and third polysilicon gate 8.3 filled in the first groove 4.1, the second groove 4.2 and the third groove 4.3, and simultaneously forming P-type lightly doped first layer of polysilicon 7 positioned on the upper surface of the hard mask layer; as in fig. 9.
(10) By adopting an oxidation method or a chemical vapor deposition method and a silicon oxide corrosion method, a non-conductive dielectric layer is formed on the upper surfaces of the first polysilicon gate 8.1 and the second polysilicon gate 8.2, the dielectric layer is usually silicon oxide, the dielectric layer and the liner layer 5 surround the first polysilicon gate 8.1 and the second polysilicon gate 8.2, and the first polysilicon gate 8.1 and the second polysilicon gate 8.2 are shielding gates of the MOSFET surrounded by the insulating layer, as shown in fig. 10.
(11) The oxidation method is adopted to grow the gate oxide layer 9 on the surfaces of the first groove 4.1 and the second groove 4.2, and as the oxidation method is not zone-selective, the surfaces of the third polysilicon gate 8.3 and the P-type lightly doped first layer polysilicon 7 are synchronously grown with silicon oxide, as shown in fig. 11.
(12) Growing a second layer of polysilicon 10 in the first groove 4.1 and the second groove 4.2 by adopting a chemical vapor deposition method, and removing the second layer of polysilicon 10 outside the first groove 4.1 and the second groove 4.2 by adopting an etching method; the second layer of polysilicon 10 is heavily doped with N-type while growing; the second polysilicon layer 10 filled in the first trench 4.1 and the second trench 4.2 forms the gate of the MOSFET, as shown in fig. 12.
(13) Forming a P-type lightly doped body region 11 in the surface layer of the N-type epitaxial layer 2 by adopting an ion implantation and annealing method; as shown in fig. 13.
(14) An N-type heavily doped region 12, that is, a source electrode of the MOSFET, is formed in the surface layer of a partial region of the P-type lightly doped body region 11 by photolithography, ion implantation, and annealing, and simultaneously, the partial region of the P-type lightly doped first layer polysilicon 7 is heavily doped to form an N-type heavily doped first layer polysilicon 13, as shown in fig. 14.
The P-type lightly doped polysilicon 7 and the N-type heavily doped polysilicon 13 form an ESD protection diode of an NPN structure, where the ESD protection diode includes at least two PN junctions, or may be a series connection of more PN junctions, such as NPNPNPN structures.
(15) The dielectric layer 14, the metal layer, and the ESD protection diode connection metal layer are formed by vapor deposition, photolithography, etching, etc., and the specific process is the same as the method for forming the dielectric layer contact hole and the metal layer in the prior art, and the steps of these methods also belong to the conventional process in the semiconductor device manufacturing field, and the specific details are not repeated, as shown in fig. 15.
In the step, the metal layer is source metal (15.1) and has two ends, wherein one end enters the first layer polysilicon (8.1) and the second polysilicon gate (8.2) or the third polysilicon gate (8.3), and the other end enters the P-type lightly doped body region (11); the ESD protection diode connection metal layer comprises a first metal layer (15.2) and a second metal layer (15.3), wherein the first metal layer (15.2) and the second metal layer (15.3) respectively enter N-type heavily doped polysilicon (13) at two sides of the P-type lightly doped polysilicon (7).
As shown in fig. 15, 15.1 is a source metal shorting the source of the MOSFET (the N-type heavily doped region 12) to the third polysilicon gate 8.3. The third polysilicon gate 8.3 is communicated with the first polysilicon gate 8.1 and the second polysilicon gate 8.2 in the chip, namely, the first polysilicon gate 8.1 and the second polysilicon gate 8.2 are in short circuit with the source electrode, so that the purpose of shielding the gate structure is achieved.
The first metal layer (15.2) and the second metal layer (15.3) are metals connected with two ends of the ESD protection diode, wherein one end of the metal is connected to the source electrode of the MOSFET, and the other end of the metal is connected to the grid electrode of the MOSFET, namely the ESD protection diode is connected between the grid electrode and the source electrode of the MOSFET in parallel, so that the purpose of ESD protection is achieved.
The method can manufacture the shielding gate trench MOSFET integrated with ESD protection, and has the advantages compared with the prior art: in the manufacturing method disclosed by the invention, the polysilicon forming the MOSFET shielding gate and the polysilicon forming the ESD protection diode of the MOSFET are the same layer of polysilicon (first layer of polysilicon), and the polysilicon forming the grid electrode of the MOSFET is the second layer of polysilicon; the device structure of the shielded gate trench MOSFET integrated with the ESD protection can be realized by only a two-layer polysilicon method in the whole manufacturing process, compared with the traditional method, the method for realizing the device structure is simpler, the manufacturing complexity and the method cost are reduced, and the method has great progress in the prior art.
It should be noted that, the photolithography, etching method, oxidation method, chemical vapor deposition method, photolithography, ion implantation method, high temperature diffusion method, photolithography, etching method and the like are all common methods in the art, and the detailed description of the method is omitted.
The embodiments of the present invention are disclosed as preferred embodiments, but not limited thereto, and those skilled in the art will readily appreciate from the foregoing description that various extensions and modifications can be made without departing from the spirit of the present invention.

Claims (4)

1. A method for manufacturing a shielded gate trench MOSFET integrated with ESD protection, characterized by: it comprises the following steps:
(1) Forming a lightly doped N-type epitaxial layer (2) on the N-type heavily doped substrate (1);
(2) Forming a hard mask layer (3) on the upper surface of the N-type epitaxial layer;
(3) Forming a first trench (4.1), a second trench (4.2) and a third trench (4.3);
(4) Forming a non-conductive dielectric layer on the inner wall of the groove and the upper surface of the hard mask layer to serve as an inner liner layer (5);
(5) Forming a first layer of polysilicon (6) over the liner layer (5);
(6) P-type lightly doped first layer polysilicon (7) is formed on the surface layer of the first layer polysilicon (6);
(7) Carrying out N-type heavy doping on partial areas of the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) and forming an N-type heavy doped first layer of polysilicon (8);
(8) Annealing and driving-in diffusion of dopants in the first layer of polysilicon (6) to make the first layer of polysilicon (6) filled in the first trench (4.1), the second trench (4.2) and the third trench (4.3) heavily doped with N-type;
(9) Removing the first polysilicon layer (6) above the first groove (4.1) and the second groove (4.2) and part of the first polysilicon layer (6) in the first groove (4.1) and the second groove (4.2) and forming N-type heavily doped first polysilicon layer (8.1) and second polysilicon gate (8.2) and third polysilicon gate (8.3) filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3), and simultaneously forming P-type lightly doped first polysilicon layer (7) positioned on the upper surface of the hard mask layer (3);
(10) Forming a non-conductive dielectric layer on the upper surfaces of the first layer of polysilicon (8.1) and the second polysilicon gate (8.2), wherein the dielectric layer and the inner liner layer surround the first layer of polysilicon (8.1) and the second polysilicon gate (8.2);
(11) Forming a gate oxide layer (9) on the surfaces of the first groove (4.1), the second groove (4.2), the protruding surface of the third polysilicon gate (8.3) and the surface of the P-type lightly doped first layer polysilicon (7);
(12) Growing a second layer of polysilicon (10) in the first groove (4.1) and the second groove (4.2) by adopting a chemical vapor deposition method, wherein the second layer of polysilicon (10) is N-type heavily doped polysilicon;
(13) Forming a P-type lightly doped body region (11) in the surface layer of the N-type epitaxial layer (2);
(14) Forming an N-type heavy doping region (12) in the upper surface layer of the P-type light doping body region (11), and synchronously, carrying out N-type heavy doping on the two end regions of the P-type light doping first layer polysilicon (7) to form an N-type heavy doping first layer polysilicon (13); at the moment, the P-type lightly doped polysilicon (7) and the N-type heavily doped polysilicon (13) form an ESD protection diode of an NPN structure;
(15) Forming a dielectric layer (14), a metal layer and an ESD protection diode connection metal layer; the metal layer is source metal (15.1) and is provided with two end parts, one end of the metal layer enters the first layer of polysilicon (8.1) and the second polysilicon gate (8.2) or the third polysilicon gate (8.3), and the other end of the metal layer enters the P-type lightly doped body region (11);
The ESD protection diode connection metal layer comprises a first metal layer (15.2) and a second metal layer (15.3), wherein the first metal layer (15.2) and the second metal layer (15.3) respectively enter N-type heavily doped polysilicon (13) at two sides of the P-type lightly doped polysilicon (7).
2. The method of manufacturing a shielded gate trench MOSFET integrated with ESD protection of claim 1, wherein: in the step (7), the partial areas of the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) are subjected to N-type heavy doping by adopting a photoetching and ion implantation method, wherein the doping is phosphorus atoms or arsenic atoms or antimony atoms, and the doping concentration is 1E 15-2E 16 per square centimeter.
3. The method of manufacturing a shielded gate trench MOSFET integrated with ESD protection of claim 1, wherein: in the step (8), a high-temperature diffusion method is adopted to anneal and drive in and diffuse dopants in the first layer of polysilicon (6), and after the dopants are diffused, the first layer of polysilicon is fully lightly doped with P type and heavily doped with N type: the first layer of polysilicon (6) filled in the first groove (4.1), the second groove (4.2) and the third groove (4.3), the first layer of polysilicon (6) above the first groove (4.1), the second groove (4.2) and the third groove (4.3) are heavily doped in N type, and the first layer of polysilicon (6) in other areas are lightly doped in P type.
4. The method of manufacturing a shielded gate trench MOSFET integrated with ESD protection of claim 1, wherein: in the step (14), an N-type heavy doping region (12) is formed in the upper surface layer of the P-type light doping body region (11) by adopting photoetching, ion implantation and annealing methods, and N-type heavy doping is carried out on the two end regions of the P-type light doping first layer polysilicon (7) synchronously to form an N-type heavy doping first layer polysilicon (13).
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