CN116130522B - Low grid charge shielding grid semiconductor device capable of reducing manufacturing cost and manufacturing method - Google Patents
Low grid charge shielding grid semiconductor device capable of reducing manufacturing cost and manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 205
- 229920005591 polysilicon Polymers 0.000 claims abstract description 164
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims description 61
- 238000002347 injection Methods 0.000 claims description 51
- 239000007924 injection Substances 0.000 claims description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention provides a low gate charge shielding gate semiconductor device with reduced manufacturing cost, comprising: a first conductivity type silicon substrate on which a first conductivity type epitaxial layer is provided; a single cell groove and a partial pressure groove are arranged in the first conductive type epitaxial layer; the single-cell groove is internally provided with source polycrystalline silicon, first grid polycrystalline silicon and second grid polycrystalline silicon which are mutually separated, and the partial pressure groove is internally provided with first field plate polycrystalline silicon, second field plate polycrystalline silicon and third field plate polycrystalline silicon which are mutually separated; the first grid polysilicon and the second grid polysilicon are respectively positioned at two sides above the source polysilicon, and the second field plate polysilicon and the third field plate polysilicon are respectively positioned at two sides above the first field plate polysilicon; the source polycrystalline silicon, the first grid polycrystalline silicon and the second grid polycrystalline silicon in the unit cell groove are mutually insulated through an insulating medium layer; the invention also provides a manufacturing method of the semiconductor device; the number of times of photolithography can be reduced, so that the manufacturing process thereof is simplified.
Description
Technical Field
The invention relates to a MOSFET power semiconductor device, in particular to a low-grid charge shielding grid semiconductor device with reduced manufacturing cost and a manufacturing method thereof.
Background
The MOSFET power semiconductor device has high integration level, low on-resistance, high switching speed and small switching loss, and is widely applied to various power management and switching conversion. As the national importance of energy conservation and emission reduction is increased, the requirements on the loss and conversion efficiency of the power device are higher and higher, and the conduction loss is mainly influenced by the magnitude of the on-resistance; wherein, the smaller the characteristic on-resistance, the smaller the on-loss; the switching loss is mainly affected by the gate charge, the smaller the switching loss. Thus, reducing the characteristic on-resistance and gate charge is two effective ways to reduce power consumption of a power device, particularly in high frequency applications and in which the switching loss of the device is a duty cycle enhancement, which is directly related to the gate charge size of the device, and thus reducing the gate charge, particularly the gate drain charge and/or the gate source charge, of the device is particularly important.
In addition, as the design of the MOSFET is mature, competition is increased, cost reduction is more and more important, the manufacturing cost of the MOSFET is related to photoetching times, and the existing shielded gate MOSFET generally adopts a manufacturing technology of photoetching for 6-7 times in the number of layers of illumination, so that the cost is high, the manufacturing period is long, and the competitiveness is low.
Disclosure of Invention
In order to solve at least one technical problem in the prior art, the embodiment of the invention provides a low-grid charge shielding grid semiconductor device and a manufacturing method thereof for reducing the manufacturing cost, so as to reduce the grid charge of a MOSFET power semiconductor device, and ensure that the semiconductor device has high switching speed and low switching loss; meanwhile, the photoetching times in the manufacturing process of the MOSFET power semiconductor device are reduced, so that the manufacturing process is simplified, and the manufacturing cost is greatly reduced. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention is as follows:
in a first aspect, embodiments of the present invention provide a low gate charge shield gate semiconductor device with reduced manufacturing cost, comprising:
a first conductivity type silicon substrate on which a first conductivity type epitaxial layer is provided; the surface of the first conductive type epitaxial layer, which faces away from the silicon substrate, is a first main surface, and the surface of the silicon substrate, which faces away from the first conductive type epitaxial layer, is a second main surface;
a single cell groove and a partial pressure groove are arranged in the first conductive type epitaxial layer, and the partial pressure groove is arranged around all the single cell grooves; the unit cell groove is positioned in a unit cell area of the device, and the voltage dividing groove is positioned in a terminal protection area of the device;
the single-cell groove is internally provided with source polycrystalline silicon, first grid polycrystalline silicon and second grid polycrystalline silicon which are mutually separated, and the partial pressure groove is internally provided with first field plate polycrystalline silicon, second field plate polycrystalline silicon and third field plate polycrystalline silicon which are mutually separated; the first grid polysilicon and the second grid polysilicon are respectively positioned at two sides above the source polysilicon, and the second field plate polysilicon and the third field plate polysilicon are respectively positioned at two sides above the first field plate polysilicon; the source polycrystalline silicon, the first grid polycrystalline silicon and the second grid polycrystalline silicon in the unit cell groove are mutually insulated through an insulating medium layer, and the first field plate polycrystalline silicon, the second field plate polycrystalline silicon and the third field plate polycrystalline silicon in the partial pressure groove are mutually insulated through the insulating medium layer; the source polycrystalline silicon in the single cell groove is isolated from the first conductive type epitaxial layer through an insulating dielectric layer on the inner wall of the single cell groove, and the first grid polycrystalline silicon and the second grid polycrystalline silicon are isolated from the first conductive type epitaxial layer through a grid oxide layer on the side wall of the single cell groove; the first field plate polysilicon in the partial pressure groove is isolated from the first conductive type epitaxial layer through an insulating dielectric layer on the inner wall of the partial pressure groove, and the second field plate polysilicon and the third field plate polysilicon are isolated from the first conductive type epitaxial layer through a grid oxide layer on the side wall of the partial pressure groove;
forming a second conductive type injection layer and a first conductive type injection layer which are distributed from bottom to top on the top of the first conductive type epitaxial layer between the single cell grooves, and forming a second conductive type injection layer on the top of the first conductive type epitaxial layer between the single cell groove at the most side and the partial pressure groove and on the top of the first conductive type epitaxial layer at the two sides of the partial pressure groove;
the first main surface is provided with an insulating dielectric layer and fills the tops of the unit cell grooves and the partial pressure grooves; a source metal and a gate metal are arranged on the insulating medium layer of the first main surface; the source metal is connected with source polycrystalline silicon in the unit cell groove and first field plate polycrystalline silicon in the partial pressure groove through a source contact hole; the gate metal is connected with the first gate polysilicon and the second gate polysilicon in the unit cell groove through the gate contact hole; the third field plate polysilicon in the partial pressure groove, which is away from the unit cell groove, is arranged in a suspending manner; the second main surface is provided with a drain metal.
Further, there is no overlapping area between the first gate polysilicon and the second gate polysilicon and the source polysilicon.
Further, the widths of the first grid polysilicon and the second grid polysilicon are 0.5-1.2 μm, and the spacing is 0.5-1.2 μm.
Further, the source metal is also connected with the second conductivity type injection layer through the injection layer contact hole.
Further, the second field plate polysilicon in the voltage division groove, which is close to the unit cell groove, is connected with source electrode metal or grid electrode metal.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a low gate charge shielding gate semiconductor device with reduced manufacturing cost, including the steps of:
step S1, providing a first conductivity type silicon substrate, and growing a first conductivity type epitaxial layer on the silicon substrate; the surface of the first conductive type epitaxial layer, which faces away from the silicon substrate, is a first main surface, and the surface of the silicon substrate, which faces away from the first conductive type epitaxial layer, is a second main surface;
step S2, a hard mask layer is deposited on the first main surface, a hard mask etching area is formed by photoetching, and the hard mask layer is etched to form a hard mask for trench etching; then etching the first main surface, and forming a unit cell groove and a partial pressure groove in the first conductive type epitaxial layer, wherein the partial pressure groove is arranged around all the unit cell grooves;
step S3, depositing or growing a first dielectric layer with an insulating effect in the first main surface, the unit cell groove and the partial pressure groove;
step S4, depositing photoresist on the first main surface, wherein the photoresist fills the single cell groove and the partial pressure groove;
step S5, removing the photoresist on the first main surface, exposing the first dielectric layer on the first main surface, and reserving the photoresist in the unit cell groove and the partial pressure groove;
step S6, wet etching the first dielectric layer to remove the first main surface and the first dielectric layer at the upper part in the single cell groove and the partial pressure groove;
in the step, the top sections of the photoresist in the single cell groove and the partial pressure groove are exposed;
step S7, removing photoresist in the single cell groove and the partial pressure groove;
step S8, growing a grid oxide layer on the first main surface and the inner walls of the unit cell groove and the partial pressure groove;
step S9, depositing conductive polysilicon in the unit cell groove and the partial pressure groove;
step S10, etching conductive polysilicon, forming source polysilicon, first grid polysilicon and second grid polysilicon which are mutually separated in a single cell groove, and forming first field plate polysilicon, second field plate polysilicon and third field plate polysilicon which are mutually separated in a partial pressure groove; the first grid polysilicon and the second grid polysilicon are respectively positioned at two sides above the source polysilicon, and the second field plate polysilicon and the third field plate polysilicon are respectively positioned at two sides above the first field plate polysilicon;
step S11, forming a second conductive type injection layer on the top of the first conductive type epitaxial layer through injection and annealing processes; then, photoresist is deposited on the first main surface, a first conductive type injection layer pattern is formed by using photomask lithography, and then, a first conductive type injection layer is formed on the top of the first conductive type epitaxial layer through injection and annealing processes;
forming a second conductive type injection layer and a first conductive type injection layer which are distributed from bottom to top on the top of the first conductive type epitaxial layer between the single cell grooves, and forming a second conductive type injection layer on the top of the first conductive type epitaxial layer between the single cell groove at the most side and the partial pressure groove and on the top of the first conductive type epitaxial layer at the two sides of the partial pressure groove;
step S12, depositing a second dielectric layer with an insulating effect on the first main surface, wherein the second dielectric layer fills the tops of the single cell groove and the partial pressure groove;
step S13, depositing photoresist on the first main surface, photoetching a source electrode contact hole, a grid electrode contact hole and an injection layer contact hole pattern by using a photomask, and etching to manufacture the source electrode contact hole, the grid electrode contact hole and the injection layer contact hole;
step S14, depositing metal on the second dielectric layer of the first main surface; depositing photoresist, photoetching a source metal and a grid metal pattern by using a photomask, and etching to manufacture the source metal and the grid metal; the source metal is connected with source polycrystalline silicon in the unit cell groove and first field plate polycrystalline silicon in the partial pressure groove through a source contact hole; the gate metal is connected with the first gate polysilicon and the second gate polysilicon in the unit cell groove through the gate contact hole; the third field plate polysilicon in the partial pressure groove, which is away from the unit cell groove, is arranged in a suspending manner; the source metal is also connected with the second conductive type injection layer through the injection layer contact hole;
step S15, depositing a drain metal on the second main surface.
Further, there is no overlapping area between the first gate polysilicon and the second gate polysilicon and the source polysilicon.
Further, the widths of the first grid polysilicon and the second grid polysilicon are 0.5-1.2 μm, and the spacing is 0.5-1.2 μm.
Further, the second field plate polysilicon in the voltage division groove, which is close to the unit cell groove, is connected with source electrode metal or grid electrode metal.
The technical scheme provided by the embodiment of the invention has the beneficial effects that:
1) The photoetching times are reduced to 4 times, and compared with the 6-7 times photoetching manufacturing procedures in the prior art, the method has the advantages of simplifying the manufacturing procedures and greatly reducing the manufacturing cost.
2) And the grid charge of the MOSFET power semiconductor device is reduced, so that the semiconductor device has high switching speed and low switching loss.
Drawings
FIG. 1 is a schematic diagram of etched cell trenches and partial pressure trenches in an embodiment of the invention.
FIG. 2 is a schematic illustration of depositing or growing a first dielectric layer in an embodiment of the present invention.
FIG. 3 is a schematic diagram of a deposited photoresist in an embodiment of the invention.
Fig. 4 is a schematic view of photoresist removal from a first major surface in an embodiment of the invention.
FIG. 5 is a schematic diagram of a first dielectric layer for removing upper portions in a cell trench and a partial pressure trench in an embodiment of the present invention.
FIG. 6 is a schematic diagram of photoresist removal in a single cell trench and a partial pressure trench in an embodiment of the invention.
FIG. 7 is a schematic diagram of a gate oxide grown on the inner walls of a single cell trench and a partial pressure trench in an embodiment of the invention.
Fig. 8 is a schematic diagram of a deposited conductive polysilicon in an embodiment of the invention.
Fig. 9 is a schematic diagram of etched conductive polysilicon in an embodiment of the invention.
Fig. 10 is a schematic diagram of forming a second conductivity type implanted layer and a first conductivity type implanted layer according to an embodiment of the present invention.
FIG. 11 is a schematic illustration of depositing a second dielectric layer in an embodiment of the present invention.
FIG. 12 is a schematic diagram of deposited metal, source metal and gate metal in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Embodiment one; taking an N-type MOSFET power semiconductor device as an example, the first conductivity type is N-type, and the second conductivity type is P-type;
an embodiment of the present invention provides a low gate charge shielding gate semiconductor device with reduced manufacturing cost, as shown in fig. 12, comprising:
a first conductivity type silicon substrate 1, on which a first conductivity type epitaxial layer 2 is provided on the silicon substrate 1; the surface of the first conductive type epitaxial layer 2 facing away from the silicon substrate 1 is a first main surface, and the surface of the silicon substrate 1 facing away from the first conductive type epitaxial layer 2 is a second main surface;
a single cell trench 31 and a partial pressure trench 32 are provided in the first conductivity type epitaxial layer 2, the partial pressure trench 32 being provided around all the single cell trenches 31; wherein, the unit cell groove 31 is positioned in the unit cell area of the device, and the voltage dividing groove 32 is positioned in the terminal protection area of the device;
a source polysilicon 711, a first gate polysilicon 712, and a second gate polysilicon 713 are provided in the cell trench 31, and a first field plate polysilicon 721, a second field plate polysilicon 722, and a third field plate polysilicon 723 are provided in the partial pressure trench 32; the first gate polysilicon 712 and the second gate polysilicon 713 are respectively located on both sides above the source polysilicon 711, and the second field plate polysilicon 722 and the third field plate polysilicon 723 are respectively located on both sides above the first field plate polysilicon 721; the source polysilicon 711, the first gate polysilicon 712, and the second gate polysilicon 713 in the cell trench 31 are insulated from each other by an insulating dielectric layer, and the first field plate polysilicon 721, the second field plate polysilicon 722, and the third field plate polysilicon 723 in the partial pressure trench 32 are insulated from each other by an insulating dielectric layer; the source polysilicon 711 in the unit cell groove 31 is isolated from the first conductive type epitaxial layer 2 through the insulating dielectric layer on the inner wall of the unit cell groove 31, and the first gate polysilicon 712 and the second gate polysilicon 713 are isolated from the first conductive type epitaxial layer 2 through the gate oxide layer 6 on the side wall of the unit cell groove 31; the first field plate polysilicon 721 in the voltage division trench 32 is isolated from the first conductivity type epitaxial layer 2 by the insulating dielectric layer on the inner wall of the voltage division trench 32, and the second field plate polysilicon 722 and the third field plate polysilicon 723 are isolated from the first conductivity type epitaxial layer 2 by the gate oxide layer 6 on the side wall of the voltage division trench 32;
forming a second conductive type injection layer 8 and a first conductive type injection layer 9 distributed from bottom to top on top of the first conductive type epitaxial layer 2 between the unit cell grooves 31, and forming a second conductive type injection layer 8 on top of the first conductive type epitaxial layer 2 between the unit cell groove 31 and the partial pressure groove 32 at the side and on top of the first conductive type epitaxial layer 2 at both sides of the partial pressure groove 32;
the first main surface is provided with an insulating dielectric layer and fills the tops of the unit cell grooves 31 and the partial pressure grooves 32; a source metal and a gate metal are arranged on the insulating medium layer of the first main surface; the source metal is connected with the source polysilicon 711 in the unit cell groove 31 and the first field plate polysilicon 721 in the partial pressure groove 32 through a source contact hole; the gate metal connects the first gate polysilicon 712 and the second gate polysilicon 713 in the unit cell trench 31 through the gate contact hole; the third field plate polysilicon 723 in the partial pressure groove 32, which is far away from the single cell groove 31, is arranged in a suspending manner, so that the pressure resistance can be realized, the electric field distribution at the position can be optimized, and the reliability can be enhanced; the second main surface is provided with a drain metal.
Further, there is no overlapping area between the first gate polysilicon 712 and the second gate polysilicon 713 and the source polysilicon 711, so that the gate-source capacitance can be reduced, and the gate-source charge can be reduced, and the gate charge of the semiconductor device is small;
specifically, the first gate polysilicon 712 and the second gate polysilicon 713 have a width of 0.5 μm to 1.2 μm and a pitch of 0.5 μm to 1.2 μm.
Further, the source metal is also connected to the second conductivity type injection layer 8 through an injection layer contact hole 11;
optionally, the second field plate polysilicon 722 in the voltage dividing trench 32 near the unit cell trench 31 is connected to the source metal or the gate metal;
the voltage dividing groove 32 may function to improve the withstand voltage of the device.
Embodiment two; in the second embodiment, taking an N-type MOSFET power semiconductor device as an example, the first conductivity type is N-type, and the second conductivity type is P-type;
the second embodiment of the invention provides a manufacturing method of a low-grid charge shielding grid semiconductor device for reducing manufacturing cost, which comprises the following steps:
step S1, providing a first conductivity type silicon substrate 1, and growing a first conductivity type epitaxial layer 2 on the silicon substrate 1; the surface of the first conductive type epitaxial layer 2 facing away from the silicon substrate 1 is a first main surface, and the surface of the silicon substrate 1 facing away from the first conductive type epitaxial layer 2 is a second main surface; as shown in fig. 1;
step S2, a hard mask layer is deposited on the first main surface, a hard mask etching area is formed by photoetching, and the hard mask layer is etched to form a hard mask for trench etching; then etching the first main surface to form a unit cell trench 31 and a partial pressure trench 32 in the first conductivity type epitaxial layer 2, the partial pressure trench 32 being disposed around all the unit cell trenches 31; as shown in fig. 1;
this step is the first lithography in this embodiment; at least one partial pressure groove 32 is required; one cell groove 31 and two partial pressure grooves 32 are exemplarily shown in fig. 1; typically several unit cells 31 are arranged in parallel, one unit cell 31 being shown on the extreme side in fig. 1;
step S3, depositing or growing a first dielectric layer 4 in the first main surface, the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 2; the first dielectric layer 4 may serve as an insulation function;
step S4, depositing a photoresist 5 on the first main surface, wherein the photoresist 5 fills the single cell groove 31 and the partial pressure groove 32; as shown in fig. 3;
step S5, removing the photoresist 5 on the first main surface, exposing the first dielectric layer 4 on the first main surface, and reserving the photoresist 5 in the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 4;
step S6, wet etching the first dielectric layer 4 to remove the first main surface and the first dielectric layer 4 at the upper part in the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 5;
in this step, the top of the photoresist 5 in the cell grooves 31 and the partial pressure grooves 32 is exposed;
step S7, removing the photoresist 5 in the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 6;
thereby, spaces with wide upper portions and narrow lower portions are formed in the cell grooves 31 and the partial pressure grooves 32, respectively;
step S8, growing a gate oxide layer 6 on the first main surface and on the inner walls of the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 7;
step S9, depositing conductive polysilicon 7 in the unit cell groove 31 and the partial pressure groove 32; as shown in fig. 8;
step S10, etching the conductive polysilicon 7, forming a source polysilicon 711, a first gate polysilicon 712, and a second gate polysilicon 713 in the unit cell trench 31, and forming a first field plate polysilicon 721, a second field plate polysilicon 722, and a third field plate polysilicon 723 in the voltage division trench 32; the first gate polysilicon 712 and the second gate polysilicon 713 are respectively located on both sides above the source polysilicon 711, and the second field plate polysilicon 722 and the third field plate polysilicon 723 are respectively located on both sides above the first field plate polysilicon 721; as shown in fig. 9;
wherein the width of the first gate polysilicon 712 and the second gate polysilicon 713 is 0.5 μm to 1.2 μm and the pitch is 0.5 μm to 1.2 μm; a space exists between the separated first gate polysilicon 712 and the second gate polysilicon 713, so that no overlapping area exists between the first gate polysilicon 712, the second gate polysilicon 713 and the source polysilicon 711, thereby reducing the gate-source capacitance, and also reducing the gate-source charge, and the gate charge of the semiconductor device is small;
step S11, forming a second conductivity type injection layer 8 on the top of the first conductivity type epitaxial layer 2 through injection and annealing processes; then, photoresist is deposited on the first main surface, a first conductive type injection layer pattern is formed by using a photomask in a photoetching mode, and then a first conductive type injection layer 9 is formed on the top of the first conductive type epitaxial layer 2 through injection and annealing processes;
wherein, a second conductivity type injection layer 8 and a first conductivity type injection layer 9 are formed on top of the first conductivity type epitaxial layer 2 between the unit cell grooves 31, and a second conductivity type injection layer 8 is formed on top of the first conductivity type epitaxial layer 2 between the unit cell groove 31 and the partial pressure groove 32 on the side and on top of the first conductivity type epitaxial layer 2 on both sides of the partial pressure groove 32; as shown in fig. 10;
this step is the second photolithography in this embodiment;
step S12, depositing a second dielectric layer 10 on the first main surface, wherein the second dielectric layer 10 fills the tops of the single cell groove 31 and the partial pressure groove 32; as shown in fig. 11;
the second dielectric layer 10 also plays an insulating role, so that the source polysilicon 711, the first gate polysilicon 712 and the second gate polysilicon 713 in the unit cell trench 31 are mutually insulated by the insulating dielectric layer, and the first field plate polysilicon 721, the second field plate polysilicon 722 and the third field plate polysilicon 723 in the partial pressure trench 32 are mutually insulated by the insulating dielectric layer;
step S13, depositing photoresist on the first main surface, photoetching a source electrode contact hole, a grid electrode contact hole and an injection layer contact hole pattern by using a photomask, and etching to manufacture a source electrode contact hole, a grid electrode contact hole and an injection layer contact hole 11;
this step is the third photolithography in this embodiment; as shown in fig. 12, the source contact hole and the gate contact hole are not shown in fig. 12;
step S14, then depositing a metal 12 on the second dielectric layer 10 on the first main surface, as shown in fig. 12;
depositing photoresist, photoetching a source metal and a grid metal pattern by using a photomask, and etching to manufacture the source metal and the grid metal; the source metal is connected with the source polysilicon 711 in the unit cell groove 31 and the first field plate polysilicon 721 in the partial pressure groove 32 through a source contact hole; the gate metal connects the first gate polysilicon 712 and the second gate polysilicon 713 in the unit cell trench 31 through the gate contact hole; the third field plate polysilicon 723 in the partial pressure groove 32, which is far away from the single cell groove 31, is arranged in a suspending manner, so that the pressure resistance can be realized, the electric field distribution at the position can be optimized, and the reliability can be enhanced;
further, the source metal is also connected to the second conductivity type injection layer 8 through an injection layer contact hole 11;
optionally, the second field plate polysilicon 722 in the voltage dividing trench 32 near the unit cell trench 31 is connected to the source metal or the gate metal;
this step is the fourth photolithography in this embodiment;
step S15, depositing drain metal on the second main surface;
the drain metal is not shown in this embodiment, and this part of the structure is conventional.
The number of illumination layers of the existing shielded gate MOSFET generally adopts a manufacturing technology of 6-7 times of photoetching, and the existing shielded gate MOSFET has the disadvantages of more procedures and high cost; according to the manufacturing method of the low-grid charge shielding grid semiconductor device with the manufacturing cost reduced, only 4 times of photoetching are needed, so that the manufacturing process can be simplified, and the manufacturing cost is greatly reduced.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to the examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (6)
1. A low gate charge shielded gate semiconductor device with reduced manufacturing costs, comprising:
a first conductivity type silicon substrate (1), on which a first conductivity type epitaxial layer (2) is provided on the silicon substrate (1); the surface of the first conductive type epitaxial layer (2) facing away from the silicon substrate (1) is a first main surface, and the surface of the silicon substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface;
a single cell trench (31) and a partial pressure trench (32) are provided in the first conductivity type epitaxial layer (2), the partial pressure trench (32) being provided around all the single cell trenches (31); wherein, the unit cell groove (31) is positioned in the unit cell area of the device, and the voltage dividing groove (32) is positioned in the terminal protection area of the device;
it is characterized in that the method comprises the steps of,
a source polysilicon (711), a first gate polysilicon (712) and a second gate polysilicon (713) which are mutually separated are arranged in the unit cell groove (31), and a first field plate polysilicon (721), a second field plate polysilicon (722) and a third field plate polysilicon (723) which are mutually separated are arranged in the partial pressure groove (32); the first gate polysilicon (712) and the second gate polysilicon (713) are respectively positioned at two sides above the source polysilicon (711), and the second field plate polysilicon (722) and the third field plate polysilicon (723) are respectively positioned at two sides above the first field plate polysilicon (721); the source polycrystalline silicon (711), the first gate polycrystalline silicon (712) and the second gate polycrystalline silicon (713) in the unit cell groove (31) are mutually insulated through an insulating medium layer, and the first field plate polycrystalline silicon (721), the second field plate polycrystalline silicon (722) and the third field plate polycrystalline silicon (723) in the partial pressure groove (32) are mutually insulated through the insulating medium layer; the source polycrystalline silicon (711) in the unit cell groove (31) is isolated from the first conductive type epitaxial layer (2) through an insulating medium layer on the inner wall of the unit cell groove (31), and the first grid polycrystalline silicon (712) and the second grid polycrystalline silicon (713) are isolated from the first conductive type epitaxial layer (2) through a grid oxide layer (6) on the side wall of the unit cell groove (31); the first field plate polysilicon (721) in the voltage division groove (32) is isolated from the first conductive type epitaxial layer (2) through an insulating medium layer on the inner wall of the voltage division groove (32), and the second field plate polysilicon (722) and the third field plate polysilicon (723) are isolated from the first conductive type epitaxial layer (2) through a gate oxide layer (6) on the side wall of the voltage division groove (32);
forming a second conductive type injection layer (8) and a first conductive type injection layer (9) which are distributed from bottom to top on the top of the first conductive type epitaxial layer (2) between the single cell grooves (31), and forming a second conductive type injection layer (8) on the top of the first conductive type epitaxial layer (2) between the single cell groove (31) at the most side and the partial pressure groove (32) and on the top of the first conductive type epitaxial layer (2) at the two sides of the partial pressure groove (32);
the first main surface is provided with an insulating dielectric layer and fills the tops of the unit cell grooves (31) and the partial pressure grooves (32); a source metal and a gate metal are arranged on the insulating medium layer of the first main surface; the source metal is connected with source polycrystalline silicon (711) in the unit cell groove (31) and first field plate polycrystalline silicon (721) in the partial pressure groove (32) through a source contact hole; the gate metal is connected with the first gate polysilicon (712) and the second gate polysilicon (713) in the unit cell groove (31) through the gate contact hole; the third field plate polysilicon (723) in the partial pressure groove (32) facing away from the unit cell groove (31) is suspended; the second main surface is provided with drain metal;
the second field plate polysilicon (722) in the partial pressure groove (32) close to the unit cell groove (31) is connected with source metal or grid metal;
there is no overlapping area between the first gate polysilicon (712) and the second gate polysilicon (713) and the source polysilicon (711).
2. The reduced cost of manufacture low gate charge shield gate semiconductor device of claim 1,
the first gate polysilicon (712) and the second gate polysilicon (713) have a width of 0.5 μm to 1.2 μm and a pitch of 0.5 μm to 1.2 μm.
3. The reduced cost of manufacture low gate charge shield gate semiconductor device of claim 1,
the source metal is also connected to the second conductivity type injection layer (8) through an injection layer contact hole (11).
4. The manufacturing method of the low-grid charge shielding grid semiconductor device for reducing the manufacturing cost is characterized by comprising the following steps of:
step S1, providing a first conductivity type silicon substrate (1), and growing a first conductivity type epitaxial layer (2) on the silicon substrate (1); the surface of the first conductive type epitaxial layer (2) facing away from the silicon substrate (1) is a first main surface, and the surface of the silicon substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface;
step S2, a hard mask layer is deposited on the first main surface, a hard mask etching area is formed by photoetching, and the hard mask layer is etched to form a hard mask for trench etching; then etching the first main surface, and forming a unit cell groove (31) and a partial pressure groove (32) in the first conductive type epitaxial layer (2), wherein the partial pressure groove (32) is arranged around all the unit cell grooves (31);
step S3, depositing or growing a first dielectric layer (4) with an insulating effect in the first main surface, the unit cell groove (31) and the partial pressure groove (32);
step S4, depositing photoresist (5) on the first main surface, wherein the photoresist (5) fills the single cell groove (31) and the partial pressure groove (32);
s5, removing the photoresist (5) on the first main surface, exposing the first dielectric layer (4) on the first main surface, and reserving the photoresist (5) in the unit cell grooves (31) and the partial pressure grooves (32);
step S6, wet etching the first dielectric layer (4) to remove the first main surface and the first dielectric layer (4) at the upper part in the unit cell groove (31) and the partial pressure groove (32);
in the step, the top sections of the photoresist (5) in the single cell groove (31) and the partial pressure groove (32) are exposed;
step S7, removing the photoresist (5) in the single cell groove (31) and the partial pressure groove (32);
step S8, growing a grid oxide layer (6) on the first main surface and on the inner walls of the unit cell groove (31) and the partial pressure groove (32);
step S9, depositing conductive polysilicon (7) in the unit cell groove (31) and the partial pressure groove (32);
step S10, etching the conductive polysilicon (7), forming source polysilicon (711), first gate polysilicon (712) and second gate polysilicon (713) which are separated from each other in the unit cell trench (31), and forming first field plate polysilicon (721), second field plate polysilicon (722) and third field plate polysilicon (723) which are separated from each other in the partial pressure trench (32); the first gate polysilicon (712) and the second gate polysilicon (713) are respectively positioned at two sides above the source polysilicon (711), and the second field plate polysilicon (722) and the third field plate polysilicon (723) are respectively positioned at two sides above the first field plate polysilicon (721);
step S11, forming a second conductive type injection layer (8) on the top of the first conductive type epitaxial layer (2) through injection and annealing processes; then, photoresist is deposited on the first main surface, a first conductive type injection layer pattern is formed by using a photomask in a photoetching mode, and then a first conductive type injection layer (9) is formed on the top of the first conductive type epitaxial layer (2) through injection and annealing processes;
forming a second conductive type injection layer (8) and a first conductive type injection layer (9) which are distributed from bottom to top on the top of the first conductive type epitaxial layer (2) between the single cell grooves (31), and forming the second conductive type injection layer (8) on the top of the first conductive type epitaxial layer (2) between the single cell groove (31) at the most side and the partial pressure groove (32) and on the top of the first conductive type epitaxial layer (2) at two sides of the partial pressure groove (32);
step S12, depositing a second dielectric layer (10) with an insulating effect on the first main surface, wherein the second dielectric layer (10) fills the tops of the unit cell grooves (31) and the partial pressure grooves (32);
step S13, photoresist is deposited on the first main surface, source electrode contact holes, grid electrode contact holes and injection layer contact hole patterns are formed by using photomask lithography, and then the source electrode contact holes, the grid electrode contact holes and the injection layer contact holes (11) are manufactured by etching;
step S14, then depositing metal (12) on the second dielectric layer (10) of the first main surface; depositing photoresist, photoetching a source metal and a grid metal pattern by using a photomask, and etching to manufacture the source metal and the grid metal; the source metal is connected with source polycrystalline silicon (711) in the unit cell groove (31) and first field plate polycrystalline silicon (721) in the partial pressure groove (32) through a source contact hole; the gate metal is connected with the first gate polysilicon (712) and the second gate polysilicon (713) in the unit cell groove (31) through the gate contact hole; the third field plate polysilicon (723) in the partial pressure groove (32) facing away from the unit cell groove (31) is suspended; the source metal is also connected with the second conductivity type injection layer (8) through an injection layer contact hole (11);
step S15, depositing drain metal on the second main surface;
there is no overlapping area between the first gate polysilicon (712) and the second gate polysilicon (713) and the source polysilicon (711).
5. The method for manufacturing a low gate charge shield gate semiconductor device with reduced manufacturing cost as recited in claim 4,
the first gate polysilicon (712) and the second gate polysilicon (713) have a width of 0.5 μm to 1.2 μm and a pitch of 0.5 μm to 1.2 μm.
6. The method for manufacturing a low gate charge shield gate semiconductor device with reduced manufacturing cost as recited in claim 4,
the second field plate polysilicon (722) in the voltage division groove (32) close to the unit cell groove (31) is connected with source metal or gate metal.
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| CN107403839A (en) * | 2017-07-25 | 2017-11-28 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure and manufacture method of deep trench |
| CN110459539A (en) * | 2019-08-06 | 2019-11-15 | 深圳市芯电元科技有限公司 | The shield grid groove MOSFET and manufacturing method of integrated ESD protection |
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| CN110459539A (en) * | 2019-08-06 | 2019-11-15 | 深圳市芯电元科技有限公司 | The shield grid groove MOSFET and manufacturing method of integrated ESD protection |
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Effective date of registration: 20231207 Address after: 1401-01, Building 1, No. 688, Zhenze Road, the Taihu Lake Street, Economic Development Zone, Wuxi City, Jiangsu Province, 214000 Patentee after: Wuxi Yifan Microelectronics Co.,Ltd. Address before: 903, Building 1, No. 688, Zhenze Road, the Taihu Lake Street, Wuxi Economic Development Zone, Jiangsu Province, 214000 Patentee before: Jiangsu Linde Semiconductor Co.,Ltd. |