CN110739346A - SJ MOS device terminal structure with shielding grid and manufacturing method thereof - Google Patents

SJ MOS device terminal structure with shielding grid and manufacturing method thereof Download PDF

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CN110739346A
CN110739346A CN201911078650.7A CN201911078650A CN110739346A CN 110739346 A CN110739346 A CN 110739346A CN 201911078650 A CN201911078650 A CN 201911078650A CN 110739346 A CN110739346 A CN 110739346A
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layer
type epitaxial
terminal
groove
conductive type
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吴宗宪
陈彦豪
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Xiamen Xinheda Investment Co ltd
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Suzhou Phoenix Core Electronic Technology Co Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

The invention relates to a terminal structure of an SJ MOS device with a shielding grid and a manufacturing method thereof, and the terminal structure comprises a conductive type heavily doped substrate, a conductive type epitaxial layer, an oxide layer, the shielding grid, grid conductive polysilicon, a second conductive type epitaxial body, a conductive type source region, source contact metal, an insulating dielectric layer, a source metal layer, a field oxide layer, a lower terminal field plate, an upper terminal field plate and a field oxide bar block.

Description

SJ MOS device terminal structure with shielding grid and manufacturing method thereof
Technical Field
The invention relates to a SJ MOS device terminal structure with a shielding grid and a manufacturing method thereof, belonging to the technical field of MOS.
Background
The trench technology MOS device has better electric energy conversion efficiency than a planar MOS device in the application field of low-voltage MOS in circuits (such as green power supplies, electric vehicles, battery management and the like) of lithium battery protection, CPU power supplies, direct current to direct current power supply conversion or synchronous rectification, but the trench technology MOS device faces the problems of on-resistance and capacitance parameters of the device, particularly switching loss caused by sharp increase of input capacitance in the process of miniaturization, and the trench shielding gate structure is of the technology for improving the switching loss, but the problems of increase of output capacitance and reduction of avalanche energy caused by the shielding gate structure are solved, so that the trench technology MOS device is limited in the application field of inductive loads such as large-current motor drive and brushless direct current motors.
Disclosure of Invention
The purpose of the invention is to overcome the defects in the prior art, and provide SJ MOS device terminal structures with shielding grids, which have smaller switching loss and can improve the cost performance and the reliability.
Another object of the present invention is to provide a method for fabricating a terminal structure of an SJ MOS device having a shield gate.
According to the technical scheme provided by the invention, the SJ MOS device terminal structure with the shielding grid comprises a terminal area and a cellular area, wherein the terminal area is positioned at the periphery of the device and surrounds the cellular area, the cellular area is positioned in the central area of the SJ MOS device, and the cellular area is formed by connecting a plurality of MOS device unit bodies in parallel;
the SJ MOS device comprises a semiconductor substrate, wherein the semiconductor substrate comprises an th conduction type heavily doped substrate and a th conduction type epitaxial layer positioned on the upper surface of the th conduction type heavily doped substrate, a cell groove is formed downwards on the left side of the upper surface of the th conduction type epitaxial layer, an oxide layer is arranged in the cell groove, the upper surface of the oxide layer protrudes out of the upper surface of the th conduction type epitaxial layer, shielding grids and grid conduction polycrystalline silicon which are arranged at intervals up and down are arranged inside the oxide layer, the shielding grids are positioned below the grid conduction polycrystalline silicon, a step-shaped second conduction type epitaxial body groove is formed downwards on the upper surface of the th conduction type epitaxial layer between the oxide layers, a second conduction type epitaxial body is filled in the second conduction type epitaxial body groove, the upper surface of the second conduction type epitaxial body is lower than the upper surface of the oxide layer, and the inner diameter of the second conduction type epitaxial body groove is gradually reduced in the direction from top to bottom;
a terminal groove is formed in the right side of the upper surface of the th conductive type epitaxial layer in a downward mode, a field oxide layer is arranged in the terminal groove, the upper surface of the field oxide layer protrudes out of the upper surface of the th conductive type epitaxial layer, a lower layer terminal field plate and an upper layer terminal field plate which are arranged at intervals up and down are arranged in the field oxide layer, the lower layer terminal field plate is located below the upper layer terminal field plate, a stepped second conductive type epitaxial body groove is formed in the lower surface of the th conductive type epitaxial layer between the field oxide layer and the oxide layer, a second conductive type epitaxial body is filled in the second conductive type epitaxial body groove, the upper surface of the second conductive type epitaxial body is lower than the upper surface of the field oxide layer, and the upper surface of the second conductive type epitaxial body protrudes out of the th conductive type epitaxial layer;
an th conductive type source region and source contact metal are arranged on the upper surface of the second conductive type epitaxial body, an insulating medium layer is arranged on the upper surfaces of the th conductive type source region and the oxide layer, and a source metal layer is arranged on the upper surfaces of the insulating medium layer and the source contact metal;
and a field oxygen bar block is arranged on the upper surface of the right side of the conductive type epitaxial layer, and the lower surface of the right end of the source metal layer is in contact with the upper surface of the left end part of the field oxygen bar block and the upper surface of the leftmost field oxygen layer.
, the thickness of the oxide layer between the shielding grid and the grid conductive polysilicon is 1000A-5000A.
And , the thickness of the field oxide layer between the lower terminal field plate and the upper terminal field plate is 1000-5000A.
And , the depths of the cell grooves and the terminal grooves are both 4-10 um.
And , the height of each step of the second conductive type epitaxial body groove is 1-5 um.
, the source metal layer and the grid conductive polysilicon are separated by an insulating medium layer.
, when the conductive heavily doped substrate, the conductive epitaxial layer and the conductive source region are N-type conductive, the second conductive epitaxial body is P-type conductive, or when the conductive heavily doped substrate, the conductive epitaxial layer and the conductive source region are P-type conductive, the second conductive epitaxial body is N-type conductive.
The manufacturing method of the SJ MOS device terminal structure with the shielding grid comprises the following steps:
step , providing a conductivity type heavily doped substrate, and growing a conductivity type epitaxial layer on the upper surface of the conductivity type heavily doped substrate;
etching downwards from the upper surface of the th conductive type epitaxial layer through the shielding of the graphical photoetching plate, simultaneously forming a cell groove and a terminal groove in the th conductive type epitaxial layer, growing an oxidation material in the terminal groove and the cell groove, and filling the terminal groove and the cell groove with the oxidation material to form a field oxide layer and an oxidation layer;
etching the field oxide layer and the oxide layer through the shielding of the graphical photoetching plate, forming a lower terminal field plate groove in the field oxide layer, and forming a shielding gate groove in the oxide layer; depositing polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove, back-etching the polycrystalline silicon, and only reserving the polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove to form a lower terminal field plate and a shielding grid; then, etching the field oxide layers on two sides above the lower-layer terminal field plate and the oxide layers on two sides above the shielding grid by adopting a wet etching process, controlling the etching depth, and removing the field oxide layers on two sides above the lower-layer terminal field plate and the oxide layers on two sides above the shielding grid;
step four, adopting a thermal oxidation process to grow layers of oxidation materials above the lower-layer terminal field plate and the shielding grid, etching the oxidation materials above the lower-layer terminal field plate and the shielding grid through shielding of a patterned photoetching plate to form an upper-layer field plate groove body and an upper-layer grid groove body, then depositing polycrystalline silicon in the upper-layer field plate groove body and the upper-layer grid groove body, filling the upper-layer field plate groove body and the upper-layer grid groove body with the polycrystalline silicon to form an upper-layer terminal field plate and grid conductive polycrystalline silicon, covering layers of oxidation materials on the upper-layer terminal field plate and the grid conductive polycrystalline silicon by using the thermal oxidation process, and finally etching the oxidation materials to expose the upper surface of a conductive type epitaxial layer;
etching the upper surface of the th conductive type epitaxial layer between the cell grooves and the terminal groove downwards under the shielding of the graphical photoetching plate to form a step-type second conductive type epitaxial body groove;
filling a second conductive type epitaxy in the second conductive type epitaxy groove to form a second conductive type epitaxy;
step seven, conductive type impurities are injected into the upper surface of the second conductive type epitaxial body, and a conductive type source region is formed after the well is pushed;
step eight, after etching between the terminal grooves, layers of oxide layers are grown to form field oxide strips;
and step nine, depositing an insulating medium layer on the th conductive type source region and the upper surface of the oxide layer, etching the insulating medium layer to form a source contact hole, filling metal into the source contact hole and the upper surface of the insulating medium layer, and performing dry etching on the metal to form source contact metal and a source metal layer.
, in step two, growing layers of oxide material on the top surface of the conductive type epitaxial layer, the cell trenches and the terminal trenches, and removing the oxide material on the top surface of the conductive type epitaxial layer by wet etching, wherein only the oxide material in the cell trenches and the terminal trenches is remained to form a field oxide layer and an oxide layer.
, in the fourth step, layers of oxide material are grown on the lower terminal field plate and the shield grid, the oxide material covers the upper surface of the conductive type epitaxial layer, polysilicon is deposited in the upper field plate groove, the upper grid electrode groove and the upper surface of the conductive type epitaxial layer, and then the polysilicon and the oxide material on the upper surface of the conductive type epitaxial layer are etched to expose the upper surface of the conductive type epitaxial layer.
The invention has the following advantages:
according to the device, the terminal ring design can be optimized and the electric field distribution of the terminal ring can be dispersed by forming the structures of the upper terminal field plate and the lower terminal field plate in the field oxide layer of the terminal area;
the invention adopts the structure of the upper grid conductive polysilicon and the lower shielding grid in the oxide layer of the device cellular region, thus reducing the input capacitance and the switching loss of the device;
a step type second conduction type epitaxial body is adopted in the th conduction type epitaxial layer of the device cellular region, and the effect of SJ MOS is formed by the epitaxial body and the th conduction type epitaxial layer;
compared with the traditional shielding grid device structure, the device has lower on-resistance;
compared with the traditional shielding grid device structure, the device has lower input and output parasitic capacitance values;
compared with the traditional shielded gate device structure, the device has better avalanche energy characteristic;
compared with the traditional shielding grid device structure, the device has better terminal electric field distribution, smaller terminal ring design and better device reliability.
Drawings
FIG. 1 is a block diagram of step of the present invention.
FIG. 2 is a block diagram of step two of the present invention.
FIG. 3 is a block diagram of step three of the present invention.
FIG. 4 is a block diagram of step four of the present invention.
Fig. 5 is a block diagram of step five of the present invention.
Fig. 6 is a block diagram of step six of the present invention.
Fig. 7 is a block diagram of step seven of the present invention.
Fig. 8 is a block diagram of step eight of the present invention.
Fig. 9 is a block diagram of step nine of the present invention.
Fig. 10 is a structural view of a conventional trench device.
Fig. 11 is a structural view of a conventional shielded gate device.
Detailed Description
The invention is further illustrated in with reference to specific examples.
The invention relates to a terminal structure of an SJ MOS device with a shielding grid, which comprises a terminal area and a cellular area, wherein the terminal area is positioned at the periphery of the device and surrounds the cellular area;
the SJ MOS device comprises a semiconductor substrate, the semiconductor substrate comprises an th conduction type heavily doped substrate 1 and a th conduction type epitaxial layer 2 located on the upper surface of the th conduction type heavily doped substrate 1, a cell groove 3 is formed in the left side of the upper surface of the th conduction type epitaxial layer 2 downwards, an oxide layer 4 is arranged in the cell groove 3, the upper surface of the oxide layer 4 protrudes out of the upper surface of the th conduction type epitaxial layer 2, a shielding grid 5 and a grid conducting polycrystalline silicon 8 which are arranged at intervals up and down are arranged in the oxide layer 4, the shielding grid 5 is located below the grid conducting polycrystalline silicon 8, a stepped second conduction type epitaxial body groove 9 is formed in the lower surface of the th conduction type epitaxial layer 2 between the oxide layers 4, the second conduction type epitaxial body 10 is filled in the second conduction type epitaxial body groove 9, the upper surface of the second conduction type epitaxial body 10 is lower than the upper surface of the oxide layer 4, and the inner diameter of the second conduction type epitaxial body groove 9 is gradually reduced from top to bottom, therefore, the second conduction type epitaxial body 10 is of a stepped conduction type epitaxial structure, and the outer diameter of the second conduction type epitaxial body 10 is gradually reduced from top to bottom;
a terminal groove 15 is formed in the right side of the upper surface of the th conductive type epitaxial layer 2 in a downward mode, a field oxide layer 16 is arranged in the terminal groove 15, the upper surface of the field oxide layer 16 protrudes out of the upper surface of the th conductive type epitaxial layer 2, a lower layer terminal field plate 17 and an upper layer terminal field plate 18 which are arranged at intervals up and down are arranged in the field oxide layer 16, the lower layer terminal field plate 17 is positioned below the upper layer terminal field plate 18, a stepped second conductive type epitaxial body groove 9 is formed in the lower portion of the upper surface of the th conductive type epitaxial layer 2 between the field oxide layer 16 and the oxide layer 4, the second conductive type epitaxial body 10 is filled in the second conductive type epitaxial body groove 9, the upper surface of the second conductive type epitaxial body 10 is lower than the upper surface of the field oxide layer 16, and the upper surface of the second conductive type epitaxial body 10 protrudes out of the upper surface of the th conductive type epitaxial layer 2;
an th conductive type source region 11 and a source contact metal 12 are arranged on the upper surface of the second conductive type epitaxial body 10, an insulating medium layer 13 is arranged on the upper surfaces of the th conductive type source region 11 and the oxide layer 4, and a source metal layer 14 is arranged on the upper surfaces of the insulating medium layer 13 and the source contact metal 12;
a field oxide bar 19 is provided on the right upper surface of the th conductive type epitaxial layer 2, and the right lower surface of the source metal layer 14 is in contact with the left upper surface of the field oxide bar 19 and the upper surface of the leftmost field oxide layer 16.
, the thickness of the oxide layer 4 between the shielding grid 5 and the grid conductive polysilicon 8 is 1000A-5000A.
, the thickness of the field oxide layer 16 between the lower terminal field plate 17 and the upper terminal field plate 18 is 1000A-5000A.
, the depth of the cell trench 3 and the terminal trench 15 are both 4-10 um.
And , the height of each step of the second conductive type epitaxial body groove 9 is 1-5 um.
, the source metal layer 14 and the gate conductive polysilicon 8 are separated by an insulating dielectric layer 13.
, when the conductive heavily doped substrate 1, the conductive epitaxial layer 2 and the conductive source region 11 are N-type conductive, the second conductive epitaxial body 10 is P-type conductive, or when the conductive heavily doped substrate 1, the conductive epitaxial layer 2 and the conductive source region 11 are P-type conductive, the second conductive epitaxial body 10 is N-type conductive.
In the invention, the number of the cell grooves 3 is two or more, and the number of the terminal grooves 15 can be designed according to the voltage requirement of the device; the upper terminal field plate 18 and the lower terminal field plate 17 can be suspended independently; the shield grid 5 may be in contact with the source or grounded or independently floating.
manufacturing methods of SJ MOS device terminal structures with shielding grids comprise the following steps:
step , providing a conductivity type heavily doped substrate 1, and growing a conductivity type epitaxial layer 2 on the upper surface of the conductivity type heavily doped substrate 1;
etching downwards from the upper surface of the th conduction type epitaxial layer 2 through shielding of a graphical photoetching plate, simultaneously forming a cell groove 3 and a terminal groove 15 in the th conduction type epitaxial layer, growing an oxidation material in the terminal groove 15 and the cell groove 3, and filling the terminal groove 15 and the cell groove 3 with the oxidation material to form a field oxide layer 16 and an oxidation layer 4;
etching the field oxide layer 16 and the oxide layer 4 through the shielding of the graphical photoetching plate, forming a lower terminal field plate groove in the field oxide layer 16, and forming a shielding gate groove in the oxide layer 4; depositing polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove, back-etching the polycrystalline silicon, and only reserving the polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove to form a lower terminal field plate 17 and a shielding grid 5; then, etching the field oxide layers 16 on two sides above the lower-layer terminal field plate 17 and the oxide layers 4 on two sides above the shielding grid 5 by adopting a wet etching process, controlling the etching depth, and removing the field oxide layers 16 on two sides above the lower-layer terminal field plate 17 and the oxide layers 4 on two sides above the shielding grid 5;
step four, adopting a thermal oxidation process to grow layers of oxidation materials above the lower-layer terminal field plate 17 and the shielding grid 5, etching the oxidation materials above the lower-layer terminal field plate 17 and the shielding grid 5 through shielding of a patterned photoetching plate to form an upper-layer field plate groove body and an upper-layer grid electrode groove body, then depositing polycrystalline silicon in the upper-layer field plate groove body and the upper-layer grid electrode groove body, filling the upper-layer field plate groove body and the upper-layer grid electrode groove body with the polycrystalline silicon to form an upper-layer terminal field plate 18 and grid conductive polycrystalline silicon 8, covering the upper-layer terminal field plate 18 and the grid conductive polycrystalline silicon 8 by using the thermal oxidation process to generate layers of oxidation materials, and finally etching the oxidation materials to expose the upper surface of the conductive type epitaxial layer 2;
etching the upper surface of the th conductive type epitaxial layer 2 between the cell grooves and the terminal groove downwards under the shielding of the graphical photoetching plate to form a step-type second conductive type epitaxial body groove 9;
filling a second conductive type epitaxy into the second conductive type epitaxy body groove 9 to form a second conductive type epitaxy body 10;
step seven, conductive type impurities are injected into the upper surface of the second conductive type epitaxial body 10, and after the well is pushed, a conductive type source region 11 is formed;
step eight, after etching between the terminal grooves 15, layers of oxide layers are grown to form field oxide bars 19;
and step nine, depositing an insulating medium layer 13 on the upper surfaces of the th conductive type source region 11 and the oxide layer 4, then etching the insulating medium layer 13 to form a source contact hole, filling metal into the source contact hole and the upper surface of the insulating medium layer 13, and performing dry etching on the metal to form a source contact metal 12 and a source metal layer 14.
, in step two, layers of oxide material are grown on the upper surface of the conductivity type epitaxial layer 2, the cell trenches 3 and the termination trenches 15, and then the oxide material on the upper surface of the conductivity type epitaxial layer 2 is removed by wet etching, and only the oxide material in the cell trenches 3 and the termination trenches 15 remains to form the field oxide layer 16 and the oxide layer 4.
, in the fourth step, layers of oxide materials are grown on the lower terminal field plate 17 and the shield grid 5, and the oxide materials cover the upper surface of the epitaxial layer 2 of the th conduction type, polysilicon is deposited in the upper field plate groove, the upper grid electrode groove and the upper surface of the epitaxial layer 2 of the conduction type, and then the polysilicon and the oxide materials on the upper surface of the epitaxial layer 2 of the conduction type are etched to expose the upper surface of the epitaxial layer 2 of the conduction type.
Compared with the traditional trench device structure (figure 10) and the prior shielded gate device structure (figure 11), the device has higher breakdown voltage and lower on-resistance when withstanding voltage: the device structure of the invention changes the design of the terminal groove 15 on the structure of the existing terminal area, the terminal groove 15 is divided into two layers, namely an upper terminal field plate 18 structure and a lower terminal field plate 17 structure, thus reducing the peak value of the terminal electric field, reducing the length of the terminal ring, reducing the chip area and simultaneously increasing the reliability of the device;
the device structure is designed outside the shielding grid structure of the existing cellular region, and the stepped P-type second conduction type epitaxial body 10 is adopted, so that the SJ MOS electric field distribution formed between the P-type second conduction type epitaxial body 10 and the N-type th conduction type epitaxial layer 2 can be greatly optimized, the electric field distribution of the peak electric field on the surface of the device can be more smooth and uniform, and the peak position of the device is not easy to break down when the device is subjected to voltage withstanding, so that the breakdown voltage of the device can be effectively improved;
after the device is conducted, compared with the traditional groove device structure and the existing shielding grid device structure, under the condition of the same withstand voltage, the device can adopt the higher-doped N-type conductive type epitaxial layer 2, so that the resistance of the N-type conductive type epitaxial layer 2 is reduced, and the on-resistance of the device is reduced;
after the device is conducted, compared with the traditional groove structure and the traditional shielding grid structure, the SJ MOS structure is formed between the stepped P type second conduction type epitaxial body 10 and the N layer th conduction type epitaxial layer 2, and through the design of optimizing the step number of the stepped P type second conduction type epitaxial body 10, the avalanche energy characteristic of the device can be improved, output and input capacitances are reduced, and therefore the switching loss of the device is reduced.

Claims (10)

1. SJMOS device terminal structure with shielding grid, it includes terminal area and cell area, the terminal area is located at the periphery of the device and surrounds the cell area, the cell area is located at the central area of the SJ MOS device, and the cell area is formed by connecting several MOS device units in parallel, it is characterized in that:
the SJ MOS device comprises a semiconductor substrate, the semiconductor substrate comprises an th conduction type heavily doped substrate (1) and a th conduction type epitaxial layer (2) positioned on the upper surface of the th conduction type heavily doped substrate (1), a cell trench (3) is formed in the left side of the upper surface of the th conduction type epitaxial layer (2) downwards, an oxide layer (4) is arranged in the cell trench (3), the upper surface of the oxide layer (4) protrudes out of the upper surface of the th conduction type epitaxial layer (2), a shielding gate (5) and a grid conduction polysilicon (8) which are arranged at intervals up and down are arranged in the oxide layer (4), the shielding gate (5) is positioned below the grid conduction polysilicon (8), a stepped second conduction type epitaxial body groove (9) is formed in the lower surface of the th conduction type epitaxial layer (2) between the oxide layers (4), a second conduction type epitaxial body (10) is filled in the second conduction type epitaxial body groove (9), the upper surface of the second conduction type epitaxial body (10) is lower than the oxide layer, and the inner diameter of the second conduction type epitaxial body (9) is gradually reduced from top to the lower surface;
a terminal groove (15) is formed in the right side of the upper surface of the th conductive type epitaxial layer (2) in a downward mode, a field oxide layer (16) is arranged in the terminal groove (15), the upper surface of the field oxide layer (16) protrudes out of the upper surface of the th conductive type epitaxial layer (2), a lower terminal field plate (17) and an upper terminal field plate (18) which are arranged at intervals are arranged in the field oxide layer (16), the lower terminal field plate (17) is located below the upper terminal field plate (18), a stepped second conductive type epitaxial body groove (9) is formed in the lower surface of the th conductive type epitaxial layer (2) between the field oxide layer (16) and the oxide layer (4), a second conductive type epitaxial body (10) is filled in the second conductive type epitaxial body groove (9), the upper surface of the second conductive type epitaxial body (10) is lower than the upper surface of the field oxide layer (16), and the upper surface of the second conductive type epitaxial body (10) protrudes out of the th conductive type epitaxial layer (2);
an th conductive type source region (11) and a source contact metal (12) are arranged on the upper surface of the second conductive type epitaxial body (10), an insulating medium layer (13) is arranged on the upper surfaces of the th conductive type source region (11) and the oxide layer (4), and a source metal layer (14) is arranged on the upper surfaces of the insulating medium layer (13) and the source contact metal (12);
a field oxygen bar block (19) is arranged on the upper surface of the right side of the conductive type epitaxial layer (2), and the lower surface of the right end of the source metal layer (14) is in contact with the upper surface of the left end part of the field oxygen bar block (19) and the upper surface of the leftmost field oxygen layer (16).
2. A SJ MOS device termination structure with a shielding gate as claimed in claim 1 wherein: the thickness of the oxide layer (4) between the shielding grid (5) and the grid conductive polycrystalline silicon (8) is 1000-5000A.
3. A SJ MOS device termination structure with a shielding gate as claimed in claim 1 wherein: the thickness of the field oxide layer (16) between the lower-layer terminal field plate (17) and the upper-layer terminal field plate (18) is 1000-5000A.
4. A SJ MOS device termination structure with a shielding gate as claimed in claim 1 wherein: the depth of the cell groove (3) and the depth of the terminal groove (15) are both 4-10 um.
5. A SJ MOS device termination structure with a shielding gate as claimed in claim 1 wherein: the height of each step of the second conductive type epitaxial body groove (9) is 1-5 um.
6. A SJ MOS device termination structure with a shielding gate as claimed in claim 1 wherein: the source metal layer (14) and the grid conductive polysilicon (8) are separated by an insulating medium layer (13).
7. The terminal structure of SJ MOS device with shielding gate of claim 1, wherein the second conductivity type epitaxial body (10) is P-type conductivity when the th conductivity type heavily doped substrate (1), the th conductivity type epitaxial layer (2) and the th conductivity type source region (11) are N-type conductivity, or wherein the second conductivity type epitaxial body (10) is N-type conductivity when the th conductivity type heavily doped substrate (1), the th conductivity type epitaxial layer (2) and the th conductivity type source region (11) are P-type conductivity.
8. The SJ MOS device terminal structure with the shielding grid and the manufacturing method thereof comprise the following steps:
step , providing a conductivity type heavily doped substrate (1), and growing a conductivity type epitaxial layer (2) on the upper surface of the conductivity type heavily doped substrate (1);
etching downwards from the upper surface of the th conductive type epitaxial layer (2) through shielding of a graphical photoetching plate, simultaneously forming a cell groove (3) and a terminal groove (15) in the th conductive type epitaxial layer, growing an oxidation material in the terminal groove (15) and the cell groove (3), filling the terminal groove (15) and the cell groove (3) with the oxidation material, and forming a field oxide layer (16) and an oxidation layer (4);
etching the field oxide layer (16) and the oxide layer (4) through shielding of the graphical photoetching plate, forming a lower-layer terminal field plate groove in the field oxide layer (16), and forming a shielding gate groove in the oxide layer (4); depositing polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove, back-etching the polycrystalline silicon, and only reserving the polycrystalline silicon in the lower terminal field plate groove and the shielding grid groove to form a lower terminal field plate (17) and a shielding grid (5); then, etching the field oxide layers (16) on the two sides above the lower-layer terminal field plate (17) and the oxide layers (4) on the two sides above the shielding grid (5) by adopting a wet etching process, controlling the etching depth, and removing the field oxide layers (16) on the two sides above the lower-layer terminal field plate (17) and the oxide layers (4) on the two sides above the shielding grid (5);
adopting a thermal oxidation process to grow layers of oxidation materials above the lower-layer terminal field plate (17) and the shielding grid (5), etching the oxidation materials above the lower-layer terminal field plate (17) and the shielding grid (5) through shielding of a patterned photoetching plate to form an upper-layer field plate groove body and an upper-layer grid groove body, then depositing polycrystalline silicon in the upper-layer field plate groove body and the upper-layer grid groove body, filling the upper-layer field plate groove body and the upper-layer grid groove body with the polycrystalline silicon to form an upper-layer terminal field plate (18) and grid conductive polycrystalline silicon (8), covering the upper-layer terminal field plate (18) and the grid conductive polycrystalline silicon (8) by using the thermal oxidation process to generate layers of oxidation materials, and finally etching the oxidation materials to expose the upper surface of the conductive type epitaxial layer (2);
etching the upper surface of the th conductive type epitaxial layer (2) between the cell grooves and the terminal groove downwards under the shielding of the graphical photoetching plate to form a stepped second conductive type epitaxial body groove (9);
filling a second conductive type epitaxy into the second conductive type epitaxy body groove (9) to form a second conductive type epitaxy body (10);
step seven, conductive type impurities are injected into the upper surface of the second conductive type epitaxial body (10), and a conductive type source region (11) is formed after the well is pushed;
step eight, after etching between the terminal grooves (15), growing layers of oxide layers to form field oxide bars (19);
and step nine, depositing an insulating medium layer (13) on the upper surfaces of the th conductive type source region (11) and the oxide layer (4), etching the insulating medium layer (13) to form a source contact hole, filling metal into the source contact hole and the upper surface of the insulating medium layer (13), and performing dry etching on the metal to form source contact metal (12) and a source metal layer (14).
9. The method for fabricating a terminal structure of an SJ MOS device having a shield gate as claimed in claim 1, wherein in the second step, layers of oxide material are grown on the upper surface of the th conductive type epitaxial layer (2), in the cell trenches (3) and in the terminal trenches (15), and then the oxide material on the upper surface of the th conductive type epitaxial layer (2) is removed by wet etching, so that only the oxide material in the cell trenches (3) and in the terminal trenches (15) remains, thereby forming the field oxide layer (16) and the oxide layer (4).
10. The method for manufacturing SJ MOS device terminal structure with shielding grid as claimed in claim 1, wherein in the fourth step, layers of oxide material are grown on the lower layer terminal field plate (17) and the shielding grid (5), the oxide material covers the upper surface of the conductive type epitaxial layer (2), polysilicon is deposited in the upper layer field plate groove, the upper layer grid electrode groove and the upper surface of the conductive type epitaxial layer (2), and then the polysilicon and the oxide material on the upper surface of the conductive type epitaxial layer (2) are etched to expose the upper surface of the conductive type epitaxial layer (2).
CN201911078650.7A 2019-11-07 2019-11-07 SJ MOS device terminal structure with shielding grid and manufacturing method thereof Pending CN110739346A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113066865A (en) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 Semiconductor device for reducing switching loss and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113066865A (en) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 Semiconductor device for reducing switching loss and manufacturing method thereof
CN113066865B (en) * 2021-03-15 2022-10-28 无锡新洁能股份有限公司 Semiconductor device for reducing switching loss and manufacturing method thereof

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