CN206134689U - Low pressure trench gate DMOS device of high integration - Google Patents
Low pressure trench gate DMOS device of high integration Download PDFInfo
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- CN206134689U CN206134689U CN201621188364.8U CN201621188364U CN206134689U CN 206134689 U CN206134689 U CN 206134689U CN 201621188364 U CN201621188364 U CN 201621188364U CN 206134689 U CN206134689 U CN 206134689U
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Abstract
The utility model provides a low pressure trench gate DMOS device of high integration, including a conductivity type heavy doping substrate, there are a conductivity type epitaxial layer and the 2nd conductivity type tagma on a conductivity type substrate upper portion, there is the trench gate electrode in top -down among the conduction type epitaxial layer, the high salient epitaxial layer of gate electrode, the gate oxide layer electrical insulation is passed through in gate electrode and the 2nd conductivity type tagma, be equipped with a conductivity type source electrode at gate electrode both sides, the 2nd conductivity type tagma top, also through the gate oxide layer electrical insulation between a gate electrode and a conductivity type source electrode, openly be equipped with the source electrode metal at the DMOS device, a source electrode metal and a conductivity type source electrode and the 2nd conductivity type tagma direct contact, the utility model discloses mainly solve the not enough problem of contact hole alignment precision that trench DMOS meets when the cellular design size is reduced to furthest reduces the cellular size, reduces unit area's conducting resistance.
Description
Technical field
This utility model is related to semiconductor integrated circuit manufacture field, especially a kind of low pressure Trench of high integration
（Trench gate）The manufacture method and structure of DMOS.
Background technology
At present, in semiconductor integrated circuit, common low pressure Trench（Trench gate）The cellular region of DMOS transistors
As shown in Fig. 1, the structure cell is mainly made up of structure groove and contact hole, and contact hole is by injecting high dose alloy shape
Into Ohmic contact, body area and source region are drawn, and contact hole is that dry etching dielectric layer is formed after one photolithographic exposure.This
Plant structure to be generally used for more than in 0.9 μm of cellular size design.
Low pressure Trench DMOS classical production process is：The first step：First conduction type heavy doping substrate 1 is provided, and
The first conduction type lightly doped epitaxial layer 2 is formed on first conduction type heavy doping substrate 1；Second step：In the first conduction type
Etching groove barrier layer is deposited in lightly doped epitaxial layer 2；3rd step：Selectively sheltered by reticle, dry etching is formed
The groove of multiple array types；4th step：Wet method peels off etching groove barrier layer；5th step：Grid oxygen is formed using thermal oxide mode
Structure 5（Grid oxide layer）, and deposit gate electrode layer；6th step：Retain polycrystalline formation gate electrode 6 by being dry-etched in groove；
7th step：The second conductive type impurity is injected, and is annealed, form the second conductivity type body region 8；8th step：Inject first conductive
Type dopant, and anneal, form the first conduction type source electrode 10；9th step：Deposit insulating medium layer 11, and flow back；Tenth step：
Selectively sheltered by reticle, dry etching insulating medium layer 11；11st step：Dry etching certain depth silicon substrate is just
Face, forms contact hole；12nd step：Front metal technique is carried out, device Facad structure is completed, source metal 12 is formed；Tenth
Four steps, carry out back metal technique, form device drain 13, complete resulting devices structure；
In order to further lift gully density, reduce device on-resistance per unit（RSP）, simplest way be into
One step reduces cellular size design.Due to being limited by producing line technological ability, during design size reduces, tradition
DMOS manufacture methods will meet with not caused enough the grid of alignment precision between contact hole and gate trench, source short circuit, component failure, raceway groove
Doping content is affected the problems such as causing raceway groove cut-in voltage lack of homogeneity by contact hole injection.
The content of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, there is provided a kind of low pressure ditch of high integration
The manufacture method of groove grid DMOS devices, on the basis of photoetching number of times is not increased, mainly solves Trench DMOS and designs in cellular
The inadequate problem of the contact hole alignment precision that runs into during size reduction, so as to reduce cellular size to greatest extent, reduces unit
The conducting resistance of area.This utility model also proposes a kind of Low-voltage trench grid DMOS devices of high integration；This utility model is adopted
Technical scheme is：
A kind of manufacture method of the Low-voltage trench grid DMOS devices of high integration, comprises the following steps：
Step one：First conduction type heavy doping substrate is provided, and is formed in the first conduction type heavy doping substrate face
First conductive type epitaxial layer；
Step 2：Etching groove barrier layer is deposited on the first conductive type epitaxial layer；
Step 3：The groove of multiple array types is formed by photoetching, dry etching in substrate face；
Step 4：Wet method peels off etching groove barrier layer；
Step 5：In epi-layer surface and epitaxial layer, trenched side-wall forms grid oxide layer, Ran Hou using thermal oxide mode
Grid oxide layer surface deposition polysilicon, and by etching the thickness of adjustment polysilicon to desired value；
Step 6：The first insulating medium layer is deposited in substrate face；
Step 7：By photoetching process, the first insulating medium layer of selectivity dry etching, polysilicon, gate electrode is formed；Grid
Retain the first insulating medium layer at the top of electrode height protrusion epitaxial layer, and gate electrode；
Step 8：The second conductive type impurity is injected in substrate face, and annealed, form the second conductivity type body region；
Step 9：The first conductive type impurity is injected in substrate face, and annealed, form the first conduction type source layer；
Step 10：The second insulating medium layer is deposited in substrate face, and is flowed back；
Step 11：By photoetching process, etched area is determined on the gate electrode of cellular region periphery, it is complete in whole cellular region
Portion is set to etched area；Divider wall etch the second insulating medium layer of dry etching, insulate in gate electrode sidewall member-retaining portion second
Dielectric layer；
Step 12：The silicon of dry etching substrate face, forms contact hole；First conduction type source layer is stayed after being etched
Lower first conduction type source electrode；First conduction type source electrode is at the top of gate electrode both sides, the second conductivity type body region；
Step 13, carries out front metal technique, completes DMOS device Facad structures；Form source metal；Source metal
With the first conduction type source electrode and the second conductivity type body region directly contact；
Step 14, carries out back metal technique, forms the drain metal of DMOS devices；Drain metal is straight with substrate back
Contact.
Further, the first insulating medium layer is undoped silicon glass USG.
Further, the second insulating medium layer is silester LPTEOS, or boron-phosphorosilicate glass BPSG.
Further, the contact hole in step 12, its depth are more than the first conduction type source electrode layer depth, and less than the
Two conductivity type body region depth.
A kind of Low-voltage trench grid DMOS devices of the high integration formed by above-mentioned manufacturing process, including the first conductive-type
Type heavy doping substrate,
There is the first conductive type epitaxial layer and the second conductivity type body region on the first conductivity type substrate top；
There is trench gate electrode in first conductive type epitaxial layer from top to bottom；Gate height protrudes epitaxial layer；Grid electricity
Pole is electrically insulated by grid oxide layer with the second conductivity type body region；
The first conduction type source electrode is provided with the top of gate electrode both sides, the second conductivity type body region；Gate electrode is led with first
Electric type source interpolar is electrically insulated also through grid oxide layer；
Source metal, the source metal and the first conduction type source electrode and the second conductive-type are provided with DMOS devices front
Xing Ti areas directly contact；Source metal is exhausted by the first insulating medium layer at the top of gate electrode and gate electrode sidewall second with gate electrode
The electric insulation isolation of edge dielectric layer；
Substrate back is provided with drain metal, drain metal and the first conductivity type substrate directly contact.
Further, the bottom of drain metal is downwards more than the friendship of the first conduction type source electrode and the second conductivity type body region
At boundary, but less than the depth of the second conductivity type body region.
Further, the material of gate electrode is polysilicon.
Specifically, the first conductivity type substrate is N+ type substrates；First conductive type epitaxial layer is N-type epitaxy layer；Second
Conductivity type body region is PXing Ti areas；First conduction type source electrode is N+ type source electrodes.
The utility model has the advantage of：
1）Compared to classical production process, structure cell contact hole is returned to carve by the second insulating medium layer and is formed, it is to avoid
Not caused enough the grid of alignment precision, source short circuit, component failure between contact hole and gate trench；
2）Compared with classical production process, contact hole apart from very little, can further improve cellular apart between gate trench
Design size, improves on-resistance per unit（RSP）, reduce chip cost.
Description of the drawings
Fig. 1 is low pressure Trench DMOS classical production process structure cell figures.
Fig. 2 is manufacture method step one schematic diagram of the present utility model.
Fig. 3 is manufacture method step 2 schematic diagram of the present utility model.
Fig. 4 is manufacture method step 3 schematic diagram of the present utility model.
Fig. 5 is manufacture method step 4 schematic diagram of the present utility model.
Fig. 6 is manufacture method step 5 schematic diagram of the present utility model.
Fig. 7 is manufacture method step 6 schematic diagram of the present utility model.
Fig. 8 is manufacture method step 7 schematic diagram of the present utility model.
Fig. 9 is manufacture method step 8 schematic diagram of the present utility model.
Figure 10 is manufacture method step 9 schematic diagram of the present utility model.
Figure 11 is manufacture method step 10 schematic diagram of the present utility model.
Figure 12 is manufacture method step 11 schematic diagram of the present utility model.
Figure 13 is manufacture method step 12 schematic diagram of the present utility model.
Figure 14 is manufacture method step 13 schematic diagram of the present utility model.
Figure 15 completes sectional view after all techniques for manufacture method of the present utility model.
Specific embodiment
With reference to concrete drawings and Examples, the utility model is described in further detail.
Embodiment one, in the present embodiment, the first conduction type is N-type, and the second conduction type is p-type；
The present embodiment provides a kind of manufacture method of the Low-voltage trench grid DMOS devices of high integration, is etched by gate electrode
When its above the first insulating medium layer for retaining, and the second insulating medium layer returns and carves the part for being retained in gate electrode sidewall, altogether
With the electric insulation formed between source metal and gate electrode, so as to reduce cellular size, the integrated level of unit area is improved.
The method is realized by following steps：
Step one：As shown in Fig. 2 supplying N+ types substrate 1, and N-type epitaxy layer 2 is formed in 1 front of N+ types substrate；
Step 2：As shown in figure 3, etching groove barrier layer 3 is deposited in N-type epitaxy layer 2；Etching groove barrier layer 3
Material is SiO2；
Step 3：As shown in figure 4, the groove 4 of multiple array types is formed in substrate face by photoetching, dry etching；
Step 4：As shown in figure 5, wet method peels off etching groove barrier layer 3；
Step 5：As shown in fig. 6,4 side wall of groove is formed using thermal oxide mode in 2 surface of epitaxial layer and epitaxial layer 2
Grid oxide layer 5, then in grid oxide layer surface deposition polysilicon 6 ', and by etching the thickness of adjustment polysilicon 6 ' to desired value；
The thickness of polysilicon 6 ' needs and follow-up divider wall etch（Spacer corrodes）Process matching；
Step 6：The first insulating medium layer 7 is deposited in substrate face；First insulating medium layer 7 is undoped silicon glass
（USG）Deng the insulating medium layer in quasiconductor meaning；
Step 7：As shown in figure 8, pass through photoetching process, selectivity dry etching the first insulating medium layer 7, polysilicon 6 ',
Form gate electrode 6；The first insulating medium layer 7 is remained with the top of gate electrode 6 height protrusion epitaxial layer 2, and gate electrode 6；
Step 8：As shown in figure 9, injecting the second conductive type impurity, such as p type impurity boron in substrate face, and anneal, shape
Into PXing Ti areas 8；
Step 9：As shown in Figure 10, the first conductive type impurity, such as Arsenic are injected in substrate face（N+ type impurity
Arsenic）, and anneal, form N+ types source layer 10 '；
Step 10：As shown in figure 11, the second insulating medium layer 11 is deposited in substrate face, and flow back；
Second insulating medium layer is silester（LPTEOS）, or boron-phosphorosilicate glass（BPSG）Deng in quasiconductor meaning
Insulating medium layer；
Step 11：As shown in figure 12, by photoetching process, etched area is determined on the gate electrode of cellular region periphery, it is whole
All it is set to etched area in individual cellular region；Divider wall etch（Spacer corrodes）The second insulating medium layer of dry etching 11,
6 the second dielectric of side wall member-retaining portion 11 of gate electrode；In this step, the grid oxide layer on 10 ' surface of N+ types source layer is also gone in the lump
Remove；
Step 12：As shown in figure 13, the silicon of dry etching substrate face, forms contact hole 101；N+ types source layer 10 '
N+ types source electrode 10 is left after being etched；N+ types source electrode 10 is at the top of 6 both sides of gate electrode, PXing Ti areas 8；
101 depth of contact hole is more than 10 ' depth of N+ types source layer, and is less than 8 depth of PXing Ti areas.
Step 13, as shown in figure 14, carries out front metal technique, completes DMOS device Facad structures；Form source electrode gold
Category 12；Source metal 12 and 8 directly contact of N-type source 10 and PXing Ti areas；
Step 14, such as Figure 15, carry out back metal technique, form the drain metal 13 of DMOS devices；Drain metal 13
With substrate back directly contact.Complete resulting devices structure.
Spirit of the technical staff in general field according to above-mentioned manufacture method, can also carry out various changing to which
Become or replace.Such as, in the embodiment of a change, it is also possible to be initially formed PXing Ti areas and N+ source layers, then carry out groove quarter
Erosion makes the subsequent actions such as trench gate；
The Low-voltage trench grid DMOS devices of the high integration that the present embodiment is formed, including N+ types substrate 1, in N+ types substrate 1
There is N-type epitaxy layer 2 and PXing Ti areas 8 in top；
There is trench gate electrode 6 in N-type epitaxy layer 2 from top to bottom；6 height protrusion epitaxial layer 2 of gate electrode；Gate electrode 6 and P
Xing Ti areas 8 are electrically insulated by grid oxide layer 5；
N+ types source electrode 10 is provided with the top of 6 both sides of gate electrode, PXing Ti areas 8；Between gate electrode 6 and N+ types source electrode 10 also through
Grid oxide layer 5 is electrically insulated；
Source metal 12 is provided with DMOS devices front, the source metal 12 is direct with N+ types source electrode 10 and PXing Ti areas 8
Contact；Source metal 12 is insulated and is situated between by the first insulating medium layer 7 at the top of gate electrode 6 and 6 side wall second of gate electrode with gate electrode 6
The electric insulation isolation of matter layer 11；
1 back side of substrate is provided with drain metal 13, drain metal 13 and 1 directly contact of N+ types substrate.
The bottom of drain metal 12 downwards more than the intersection in N+ types source electrode 10 and Xing Ti areas 8, but less than Xing Ti areas 8
Depth.
In the above-described embodiments, with first conduction type as N types, as a example by second conduction type is P types
It is introduced, in other embodiments for changing, it is also possible to which, so that the first conduction type is p-type, second conduction type is N
Type, now using the Semiconductor substrate 1 of P-type；Remaining Each part is also corresponding N<->The conversion of P.
Claims (4)
1. a kind of Low-voltage trench grid DMOS devices of high integration, including the first conduction type heavy doping substrate, it is characterised in that
There is the first conductive type epitaxial layer and the second conductivity type body region on the first conductivity type substrate top；
There is trench gate electrode in first conductive type epitaxial layer from top to bottom；Gate height protrudes epitaxial layer；Gate electrode with
Second conductivity type body region is electrically insulated by grid oxide layer；
The first conduction type source electrode is provided with the top of gate electrode both sides, the second conductivity type body region；Gate electrode and the first conductive-type
It is electrically insulated also through grid oxide layer between type source electrode；
Source metal, the source metal and the first conduction type source electrode and the second conduction type body are provided with DMOS devices front
Area's directly contact；Source metal is situated between by the first insulating medium layer at the top of gate electrode and the insulation of gate electrode sidewall second with gate electrode
The electric insulation isolation of matter layer；
Substrate back is provided with drain metal, drain metal and the first conductivity type substrate directly contact.
2. Low-voltage trench grid DMOS devices of high integration as claimed in claim 1, it is characterised in that
The bottom of drain metal is downwards more than the first conduction type source electrode and the intersection of the second conductivity type body region, but is less than
The depth of the second conductivity type body region.
3. Low-voltage trench grid DMOS devices of high integration as claimed in claim 2, it is characterised in that
The material of gate electrode is polysilicon.
4. Low-voltage trench grid DMOS devices of high integration as claimed in claim 1, it is characterised in that
First conductivity type substrate is N+ type substrates；First conductive type epitaxial layer is N-type epitaxy layer；Second conductivity type body region
For PXing Ti areas；First conduction type source electrode is N+ type source electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201621188364.8U CN206134689U (en) | 2016-11-04 | 2016-11-04 | Low pressure trench gate DMOS device of high integration |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621188364.8U CN206134689U (en) | 2016-11-04 | 2016-11-04 | Low pressure trench gate DMOS device of high integration |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340537A (en) * | 2016-11-04 | 2017-01-18 | 无锡新洁能股份有限公司 | Low-voltage trench DMOS device of high integrated level and manufacture method of device |
| CN111081774A (en) * | 2018-10-18 | 2020-04-28 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
-
2016
- 2016-11-04 CN CN201621188364.8U patent/CN206134689U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340537A (en) * | 2016-11-04 | 2017-01-18 | 无锡新洁能股份有限公司 | Low-voltage trench DMOS device of high integrated level and manufacture method of device |
| CN111081774A (en) * | 2018-10-18 | 2020-04-28 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
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