CN111081774A

CN111081774A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN111081774A
Application number: CN201811214243.XA
Authority: CN
Inventors: 肖魁; 方冬; 卞铮
Original assignee: CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab2 Co Ltd; CSMC Technologies Corp
Priority date: 2018-10-18
Filing date: 2018-10-18
Publication date: 2020-04-28
Also published as: WO2020078419A1

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: a semiconductor substrate; a trench formed in the semiconductor substrate; the bottom of the polycrystalline silicon layer is positioned in the groove, the top height position of the polycrystalline silicon layer is higher than that of the groove, and the semiconductor device and the manufacturing method thereof can improve the stability of threshold voltage on the premise that the manufacturing process is completely compatible and a mask plate or a process step is not added.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device structure and a manufacturing method thereof.

Background

The groove type VDMOS product is a power device which is widely applied, on one hand, the unit cell size is further reduced due to the maturity of the groove process, on the other hand, as the groove region penetrates through the lowest end of the P type base region, the formed groove is located between the source region and the drift region, compared with the common VDMOS, the JFET region is eliminated, the on-resistance is greatly reduced, and therefore the performance of the MOS power device is greatly improved. For a trench-type VDMOS, a structure adopted at present is that a polysilicon gate plane in a trench is lower than a silicon plane, and a manufacturing process includes trench etching, gate oxide growth, polysilicon deposition, polysilicon etching, well region formation, NSD formation, hole formation, metal electrode formation, and back surface process. Because the polysilicon etching must ensure that the polysilicon above the silicon is completely etched, otherwise, the device has the problems of gate-source short circuit and the like, the process sets that when the oxide layer above the silicon is etched, a certain etching amount is increased so as to ensure that all the polysilicon above the silicon is completely etched. That is, the polysilicon gate plane in the trench is lower than the silicon plane, which causes the problem that the subsequent well region implantation and source region implantation will affect the channel, resulting in unstable threshold voltage.

Therefore, the invention provides a semiconductor device structure and a manufacturing method thereof, wherein the polysilicon gate plane is higher than the silicon plane, so that the problem of unstable threshold voltage is solved.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the foregoing, an aspect of the present invention provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; and the bottom of the polycrystalline silicon layer is positioned in the groove, and the height position of the top of the polycrystalline silicon layer is higher than that of the top of the groove.

Optionally, the semiconductor device further comprises a well region formed in the semiconductor substrate.

Optionally, the semiconductor device further includes a source/drain region formed in the well region.

Optionally, the source/drain region includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region have two doping types, where the doping type of the first source/drain is opposite to the doping type of the well region.

Optionally, the semiconductor device further comprises contact layers formed above and below the semiconductor device and connected to the source and the drain, so as to form a cellular structure.

In another aspect, the present invention provides a method for manufacturing a semiconductor, including: providing a semiconductor substrate; forming a groove in the semiconductor substrate; depositing a polysilicon layer, wherein the bottom of the polysilicon layer is positioned in the groove; and etching the polycrystalline silicon layer, wherein the height position of the top of the etched polycrystalline silicon layer is higher than that of the top of the groove.

Optionally, the method further comprises: a well region is formed in the semiconductor substrate.

Optionally, source/drain regions of a first doping type are formed in the well region.

Optionally, the method further comprises: an interlayer dielectric layer is formed over the trench and the first source/drain region.

Optionally, the method further comprises: and forming a contact hole on the interlayer dielectric layer, wherein the contact hole extends from the top end to the bottom end of the interlayer dielectric layer, the bottom end of the contact hole is lower than the lower surface of the first source/drain region, and a second source/drain region is formed by injecting through the contact hole, and the second source/drain region and the first source/drain region have different doping types.

Optionally, a filling step of the contact hole is further included.

Optionally, the method further comprises: and forming contact layers above the interlayer dielectric layer and below the semiconductor substrate, and respectively forming leads through the contact layers to be connected with the source electrode and the drain electrode so as to form a cellular structure.

In another aspect, the invention provides a VDMOS device comprising, a semiconductor substrate; a trench formed in the semiconductor substrate; the grid is composed of a polycrystalline silicon layer, the bottom of the polycrystalline silicon layer is positioned in the groove, the top height position of the polycrystalline silicon layer is higher than that of the groove, and the plane of the grid is higher than that of the semiconductor substrate; and contact layers respectively formed above and below the semiconductor device and connected to the source electrode and the drain electrode to form a cellular structure.

The semiconductor device and the manufacturing method thereof can improve the stability of the threshold voltage on the premise that the manufacturing process is completely compatible and a mask plate or a process step is not added.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A to 1K are schematic cross-sectional views of devices obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2A to 2K are schematic cross-sectional views of devices obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

figure 3 shows a schematic flow diagram of an embodiment of the present invention.

Description of the reference numerals

100, 200 silicon wafer

101, 201 silicon epitaxial layer

102, 202 first oxide layer

103, 203 second oxide layer

104, 204 polysilicon layer

105, 205 well region

106, 206 first source/drain regions

107, 207 interlayer dielectric layer

108, 208 contact holes

109, 209 second source/drain regions

1101,1102, 2101,2102 contact layer

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In order to solve the foregoing technical problem, the present invention provides a semiconductor device and a method for manufacturing the same, including: a semiconductor substrate; a trench formed in the semiconductor substrate; the polycrystalline silicon layer is positioned in the groove, and the top height position of the polycrystalline silicon layer is higher than that of the groove.

The process of manufacturing a VDMOS will be described with reference to schematic cross-sectional views of devices obtained in relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention shown in fig. 1A to 1K.

Step 1, providing a silicon wafer 100 as a substrate, and forming a silicon epitaxial layer 101 on the silicon substrate, as shown in fig. 1A;

step 2, forming an oxide layer 102, and forming a first oxide layer 102 on the silicon epitaxial layer 101, optionally, the first oxide layer 102 is a thermal oxide layer TOX, as shown in fig. 1B;

step 3, forming a trench, and forming a trench in the first oxide layer 102 and the silicon epitaxial layer 101, as shown in fig. 1C;

optionally, step 3 further comprises: after the groove is formed, removing the first oxide layer 102 above the silicon epitaxial layer 101;

step 4, forming a second oxide layer 103, and forming the second oxide layer 103 in the surface of the silicon epitaxial layer 101 and the trench, wherein optionally, the second oxide layer is a gate oxide layer, as shown in fig. 1D;

step 5, filling the polysilicon 104, depositing the polysilicon 104 on the surface of the gate oxide layer 103, and filling the trench and the upper part of the trench, as shown in fig. 1E;

step 6, etching the polysilicon layer 104, and etching the polysilicon layer 104, wherein the top height of the etched polysilicon layer 104 is lower than the top surface of the groove, as shown in fig. 1F;

step 7, forming a well region 105, and injecting the silicon epitaxial layer to form a P-well region, as shown in fig. 1G;

step 8, forming an NSD106, and injecting and forming an N-type source/drain region 106 in the well region, as shown in fig. 1H;

step 9, forming an ILD107, and forming an interlayer dielectric layer 107 over the trench and the NSD106, as shown in fig. 1I;

step 10, forming a hole 108, forming a CT contact hole 108 on the interlayer dielectric layer, wherein the contact hole 108 extends from the top end to the bottom end of the interlayer dielectric layer 107, and the bottom end of the contact hole 108 is lower than the lower surface of the NSD106, and performing implantation through the hole 108 to form a PSD109, i.e. a P-type source/drain, as shown in fig. 1J;

step 11, forming a cellular structure, forming

contact layers

1101 and 1102 above the interlayer dielectric layer ILD107 and below the silicon wafer 100 substrate, and forming leads respectively through the

contact layers

1101 and 1102 to be connected to a source (S) and a drain (D), thereby forming the cellular structure, as shown in FIG. 1K.

The disadvantages of the previous embodiments are as follows:

in the manufacturing process from step 5 to step 6, the polysilicon 104 above the silicon is completely etched, so that the well 105 implantation and the NSD106 implantation in steps 7 and 8 affect the channel and thus the stability of the threshold voltage.

Referring to fig. 2A to 2K, a cross-sectional view of a device obtained through the relevant steps of the method for manufacturing a VDMOS device according to an embodiment of the present invention will be described.

Step 1, providing a silicon wafer 200 as a substrate, and forming a silicon epitaxial layer 201 on the silicon substrate, as shown in fig. 2A;

optionally, the semiconductor substrate comprises the silicon wafer 200 and the silicon epitaxial layer 201;

wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member, which may be a gate, a source, or a drain of a transistor, or the like, may be formed in the semiconductor substrate.

Step 2, forming an oxide layer 202, and forming a first oxide layer 202 on the silicon epitaxial layer 201, optionally, the first oxide layer 202 is a thermal oxide layer TOX, as shown in fig. 2B;

various oxides, such as silicon dioxide, may be used for the first oxide layer 202. The first oxide layer may be fabricated by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), and the like.

Step 3, forming a trench, and forming a trench in the first oxide layer 202 and the silicon epitaxial layer 201, as shown in fig. 2C;

step 4, forming a second oxide layer 203, and forming the second oxide layer 203 in the trench, wherein optionally, the second oxide layer 203 is a gate oxide layer, and the first oxide layer 202 still remains above the silicon epitaxial layer 201, as shown in fig. 2D;

the second oxide layer 203 may be made of various insulating materials, such as oxide, nitride, oxynitride, and the like. The second oxide layer may be fabricated by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), and the like.

Illustratively, the second oxide layer employs a TEOS (tetraethylorthosilicate, Si (OC2H5)4) oxide, i.e., a silicon dioxide layer formed using TEOS (tetraethylorthosilicate, Si (OC2H5) 4). Illustratively, the second insulating layer 304 is fabricated using a furnace process, the process temperature is illustratively 680 degrees, and the thickness of the second insulating layer 304 is illustratively

Step 5, filling the polysilicon 204, depositing the polysilicon 204 on the surface of the first oxide layer 202 and the second oxide layer 203, and filling the trench and the upper part of the trench, as shown in fig. 2E;

step 6, etching the polysilicon layer 204, and etching the polysilicon layer 204, wherein the top height of the etched polysilicon layer 204 is higher than the top surface of the groove, as shown in fig. 2F;

the polysilicon layer 204 is fabricated by a method such as furnace process, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), etc., and patterned by a photolithographic etching method commonly used in the art. Of course, the filling material in the trench may be made of other suitable materials, and is not limited to polysilicon.

Step 7, forming a well region 205, and implanting a well region of a second doping type, such as a P-well region 205, in the silicon epitaxial layer 201, as shown in fig. 2G;

optionally, the well region 205 may also be a first doping type, such as an N-well region;

step 8, forming a first source/drain region 206, and forming the first source/drain region 206 in the well region 205, where the first source/drain region 206 is of a first doping type, for example, an N-type source/drain region, as shown in fig. 2H;

alternatively, the first source/drain regions 206 may be doped with a second doping type, such as P-type source/drain regions,

wherein the source/drain regions 206 are formed by implantation, an ion implantation doping process may be employed, in which an ion beam accelerated to a certain high energy is implanted into the surface layer of the solid material to change the physical and chemical properties of the surface layer. The surface conductivity of the semiconductor can be changed or a PN junction can be formed by implanting corresponding impurity atoms into the semiconductor (e.g., implanting boron, phosphorus, or arsenic into silicon) to form an N-type source/drain region, and implanting phosphorus or arsenic into silicon to form a P-type source/drain region, but the choice of the dopant is not limited to these.

It should be noted that, in the present specification, the first doping type and the second doping type generally refer to P type or N type, wherein the first doping type and the second doping type are opposite, for example, the first doping type is one of P type, low doping P-type, and high doping P + type, and the second doping type is one of N type, low doping N-type, and high doping N + type. Or conversely, the first doping type is one of an N type, a low-doping N-type and a high-doping N + type, and the second doping type is one of a P type, a low-doping P-type and a high-doping P + type.

Step 9, forming an ILD207, forming an interlayer dielectric layer 207 above the trench and the first source/drain region 206, as shown in fig. 2I;

the interlayer dielectric layer 207 is deposited between different layers to isolate the conductive layer to be deposited next, and generally refers to an insulating layer between the semiconductor layer and the metal layer, which may be a single-layer structure or a multi-layer structure, and can obtain the required thermal conductivity and RC delay time constant by selecting parameters of the dielectric layer itself, such as the number of node systems, thermal conductivity, etc.

Step 10, forming a hole 208, forming a CT contact hole 208 on the interlayer dielectric layer 207, wherein the contact hole 208 extends from the top end to the bottom end of the interlayer dielectric layer 207, the bottom end of the contact hole 208 is lower than the lower surface of the NSD206, and forming a second source/drain region 209 through the hole 208, wherein the second source/drain region 209 is of a second doping type, such as a P-type source/drain region, as shown in fig. 2J;

alternatively, the second source/drain region 209 may also be a first doping type, such as an N-type source/drain region, wherein the source/drain region is formed by implantation, and an ion implantation doping process may be adopted, wherein an ion beam accelerated to a certain high energy is implanted into the surface layer of the solid material to change the physical and chemical properties of the surface layer. Implanting impurity atoms into the semiconductor (e.g., implanting boron, phosphorus, or arsenic into silicon) to change the surface conductivity or form PN junctions to form N-type source/drain regions, optionally implanting phosphorus or arsenic into silicon to form P-type source/drain regions, optionally implanting boron into silicon, although the choice of dopants is not limited to these,

Optionally, step 10 further includes a filling step of the CT contact hole 208;

step 11, forming a cellular structure, forming

contact layers

2101 and 2102 above the interlayer dielectric layer ILD207 and below the silicon chip 200 substrate, and forming leads respectively through the

contact layers

2101 and 2102 to be connected to a source (S) and a drain (D), thereby forming the cellular structure, as shown in FIG. 2K.

Alternatively, in the process of forming the trench, the polysilicon layer and/or the contact hole in step 3, step 6 and step 10, respectively, an etching method may be used, and the etching includes wet etching and/or dry etching.

Alternatively, when the implantation operations are performed in step 7, step 8, and step 10, respectively, a mask implantation is employed.

The embodiment shown in figure 2 is comparable to the embodiment shown in figure 1,

1. step 3 to step 4: the TOX oxide layer is completely etched by a wet method, and the embodiment of FIG. 2 is kept;

2. step 5 to step 6: due to the existence of the TOX oxide layer, the embodiment of the attached figure 2 obtains a structure that the plane of the polysilicon gate is higher than the plane of the silicon by adopting the same etching mode;

the existence of the oxide layer enables the height of the top plane of the polycrystalline silicon to be higher than the height of the top surface of the silicon epitaxial layer, and the specific higher part of the oxide layer can be determined by the thickness of the oxide layer;

3. the injection process of the steps 7 and 8 will not affect the channel, and the threshold voltage of the device can be stabilized.

Because the height of the top plane of the polysilicon is relatively high, the top of the polysilicon can block implanted ions when the implantation step is performed, so that the influence of the implantation step on a channel is reduced, and the influence of the implantation step on the threshold voltage is avoided.

Therefore, by adopting the mode of reserving the TOX oxide layer, a structure that the plane of the polysilicon gate is higher than the plane of the silicon is formed during the polysilicon etching. The structure with the polysilicon gate plane higher than the silicon plane and the manufacturing method thereof solve the problem of unstable threshold voltage in the mass production and manufacturing of devices. Compared with the prior art, the manufacturing process of the invention does not add a mask plate or a new process step, and the manufacturing process is completely compatible.

Reference is now made to fig. 3, which is a schematic diagram illustrating the steps associated with a method of fabricating a VDMOS device in accordance with an embodiment of the present invention.

Step S101, providing a semiconductor substrate;

step S102, forming a groove in the semiconductor substrate;

step S103, depositing polycrystalline silicon in the groove;

and step S104, etching the polycrystalline silicon layer, wherein the height position of the top of the etched polycrystalline silicon layer is higher than that of the top of the groove.

In another embodiment, the present invention also provides a semiconductor device including: a semiconductor substrate; a trench formed in the semiconductor substrate; the polycrystalline silicon layer is positioned in the groove, the height position of the top of the polycrystalline silicon layer is higher than that of the top of the groove, and optionally, the polycrystalline silicon layer further comprises a well region which is formed in the semiconductor substrate.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a trench formed in the semiconductor substrate;

and the bottom of the polycrystalline silicon layer is positioned in the groove, and the height position of the top of the polycrystalline silicon layer is higher than that of the top of the groove.

2. The semiconductor device according to claim 1, further comprising

A well region formed in the semiconductor substrate.

3. The semiconductor device according to claim 2, further comprising

A source/drain region formed in the well region.

4. The semiconductor device of claim 3, wherein the source/drain regions comprise a first source/drain region and a second source/drain region, the first source/drain region and the second source/drain region having two doping types, wherein the first source/drain doping type is opposite to the well region doping type.

5. The semiconductor device according to any one of claims 1 to 4, further comprising contact layers formed above and below the semiconductor device, respectively, and connected to the source and drain electrodes, thereby forming a cell structure.

6. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a groove in the semiconductor substrate;

depositing a polysilicon layer, wherein the bottom of the polysilicon layer is positioned in the groove;

and etching the polycrystalline silicon layer, wherein the height position of the top of the etched polycrystalline silicon layer is higher than that of the top of the groove.

7. The method of manufacturing of claim 6, further comprising: a well region is formed in the semiconductor substrate.

8. The method of manufacturing of claim 7, further comprising: source/drain regions of a first doping type are formed in the well region.

9. The manufacturing method according to claim 8,

further comprising: an interlayer dielectric layer is formed over the trench and the first source/drain region.

10. The manufacturing method according to claim 9,

further comprising: and forming a contact hole on the interlayer dielectric layer, wherein the contact hole extends from the top end to the bottom end of the interlayer dielectric layer, the bottom end of the contact hole is lower than the lower surface of the first source/drain region, and a second source/drain region is formed by injecting through the contact hole, and the second source/drain region and the first source/drain region have different doping types.

11. The manufacturing method according to claim 10, further comprising a filling step of the contact hole.

12. The manufacturing method according to any one of claims 9 to 11,

further comprising: and forming contact layers above the interlayer dielectric layer and below the semiconductor substrate, and respectively forming leads through the contact layers to be connected with the source electrode and the drain electrode so as to form a cellular structure.

13. A VDMOS device comprises a substrate, a first substrate,

a semiconductor substrate;

a trench formed in the semiconductor substrate;

the grid is composed of a polycrystalline silicon layer, the bottom of the polycrystalline silicon layer is positioned in the groove, the top height position of the polycrystalline silicon layer is higher than that of the groove, and the plane of the grid is higher than that of the semiconductor substrate;

and contact layers respectively formed above and below the semiconductor device and connected to the source electrode and the drain electrode to form a cellular structure.