CN111146288A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN111146288A
CN111146288A CN201811314323.2A CN201811314323A CN111146288A CN 111146288 A CN111146288 A CN 111146288A CN 201811314323 A CN201811314323 A CN 201811314323A CN 111146288 A CN111146288 A CN 111146288A
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source
drain region
forming
semiconductor substrate
contact hole
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肖魁
方冬
卞铮
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CSMC Technologies Fab2 Co Ltd
CSMC Technologies Corp
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CSMC Technologies Fab2 Co Ltd
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Priority to CN201811314323.2A priority Critical patent/CN111146288A/en
Priority to PCT/CN2019/115932 priority patent/WO2020094044A1/en
Publication of CN111146288A publication Critical patent/CN111146288A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed over the trench and the semiconductor substrate; a contact hole formed in the interlayer dielectric layer and the semiconductor substrate; the first source/drain region and the second source/drain region are formed through the contact holes, a source/drain region mask plate can be omitted, a photoetching link is omitted, and manufacturing cost is saved.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device structure and a manufacturing method thereof.
Background
The groove type VDMOS product is a power device which is widely applied, on one hand, the unit cell size is further reduced due to the maturity of the groove process, on the other hand, as the groove region penetrates through the lowest end of the P type base region, the formed groove is located between the source region and the drift region, compared with the common VDMOS, the JFET region is eliminated, the on-resistance is greatly reduced, and therefore the performance of the MOS power device is greatly improved. For a trench-type VDMOS, a structure adopted at present is that a polysilicon gate plane in a trench is lower than a silicon plane, and a manufacturing process includes trench etching, gate oxide growth, polysilicon deposition, polysilicon etching, well region formation, NSD formation, hole formation, metal electrode formation, and back surface process. The mask plate used based on the manufacturing method at least comprises a groove mask plate, an NSD mask plate, a CT mask plate and a metal mask plate, and then a passivation layer mask plate and the like can be added for improving the performance.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the foregoing, one aspect of the present invention provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed over the trench and the semiconductor substrate; a contact hole formed in the interlayer dielectric layer and the semiconductor substrate; a first source/drain region and a second source/drain region, both formed by the contact hole.
Optionally, the semiconductor device further includes a well region formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
Optionally, the size of the first source/drain region is larger than the size of the second source/drain region.
Optionally, the method further comprises: and contact layers respectively formed above and below the semiconductor device and connected to the source and drain electrodes to form a cell structure.
In still another aspect, the present invention provides a method of manufacturing, comprising: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming an interlayer dielectric layer over the trench and the semiconductor substrate; forming a contact hole on the interlayer dielectric layer, the contact hole extending from the top to the bottom of the interlayer dielectric layer; forming a first source/drain region by injecting through the contact hole; and forming a second source/drain region by injecting through the contact hole.
Optionally, the method further comprises: and forming a well region, wherein the well region is formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
Optionally, the method further comprises: and forming a well region, wherein the well region is formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
Optionally, expanding the first source/drain region is achieved using a thermal treatment.
Optionally, the method further comprises a step of deepening the contact hole, wherein the contact hole is further processed after the first source/drain region is formed, so that the depth of the contact hole is deepened, and the bottom of the contact hole is lower than the lower surface of the first source/drain region.
Optionally, the second source/drain region is formed by using the deepened contact hole.
Optionally, a filling step of the contact hole is further included.
Optionally, contact layers are formed above the interlayer dielectric layer and below the semiconductor substrate, and leads are respectively formed through the contact layers and connected to the source and the drain, thereby forming a cellular structure.
The invention can save a source/drain region mask plate, and simultaneously save the manufacturing photoetching link and the manufacturing cost.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1J are schematic cross-sectional views of devices obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2A to 2K are schematic cross-sectional views of devices obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
figure 3 shows a schematic flow diagram of an embodiment of the present invention.
Description of the reference numerals
100, 200 silicon wafer
101, 201 silicon epitaxial layer
102, 202 first oxide layer
103, 203 second oxide layer
104, 204 polysilicon layer
105, 205 well region
106, 206 first source/drain regions
107, 207 interlayer dielectric layer
108, 208 contact holes
109, 209 second source/drain regions
1101,1102, 2101,2102 contact layer
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the foregoing technical problem, the present invention provides, in one aspect, a semiconductor device and a method for manufacturing the same, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed over the trench and the semiconductor substrate; a contact hole formed in the interlayer dielectric layer and the semiconductor substrate; a first source/drain region and a second source/drain region, both formed by the contact hole.
In summary, the invention can omit a source/drain region mask plate, and simultaneously omit a photoetching process, thereby saving the manufacturing cost.
The process of manufacturing a VDMOS will be described with reference to schematic cross-sectional views of devices obtained in relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention shown in fig. 1 to 1J.
Step 1, providing a silicon wafer 100 as a substrate, and forming a silicon epitaxial layer 101 on the silicon substrate, as shown in fig. 1A;
step 2, forming an oxide layer 102, forming a first oxide layer 102 on the silicon epitaxial layer 101, and forming a trench, wherein the trench is formed in the first oxide layer 102 and the silicon epitaxial layer 102, and the first oxide layer is a thermal oxide layer, as shown in fig. 1B;
in one embodiment, after the trench is formed, the first oxide layer 102 above the silicon epitaxial layer 101 is removed;
and 3, forming a second oxide layer 103 and filling the polysilicon 104, forming the second oxide layer 103 on the surface of the silicon epitaxial layer 101 and in the trench, wherein the second oxide layer is a gate oxide layer GOX, depositing the polysilicon 104 on the surface of the gate oxide layer GOX, and filling the trench and the upper part of the trench.
In an embodiment, the method further includes a step of etching the polysilicon layer 104, in which the polysilicon layer 104 is etched, and the top height of the etched polysilicon layer 104 is lower than the top surface of the groove, as shown in fig. 1C;
step 4, forming a well region 105, and injecting the silicon epitaxial layer 101 to form a P-well region, as shown in fig. 1D;
step 5, forming an N-type source/drain 106, and injecting the N-type source/drain 106 into the well region 105, as shown in fig. 1E;
step 6, forming an ILD107, and forming an interlayer dielectric layer 107 over the trench and the NSD106, as shown in fig. 1F;
step 7, forming a hole 108, and forming a CT contact hole 108 on the interlayer dielectric layer 107, wherein the contact hole 108 extends from the top end to the bottom end of the interlayer dielectric layer 107, and the bottom end of the contact hole 108 is located on the upper surface of the NSD106, as shown in fig. 1G;
step 8, deepening the hole, and further processing the CT contact hole, such as photolithography, to deepen the contact hole 108, as shown in fig. 1H;
step 9, injecting through the contact hole 108 to form a PSD109, i.e. a P-type source/drain 109, as shown in fig. 1I;
step 10, forming a cellular structure, forming contact layers 1101 and 1102 above the interlayer dielectric layer ILD107 and below the silicon substrate 100, and forming leads respectively connected to the source (S) and the drain (D) through the contact layers 1101 and 1102, thereby forming the cellular structure, as shown in FIG. 1J.
The disadvantages of the previous embodiments are as follows:
in the processes of steps 2, 7, 8 and 10 in the manufacturing process, photoetching steps are required, and steps such as a mask plate, gluing, developing, exposing, removing glue and the like are required in each photoetching step, so that the preparation process is complicated, the cost is increased, and the efficiency is low.
Referring to fig. 2A to 2K, a cross-sectional view of a device obtained through the relevant steps of the method for manufacturing a VDMOS device according to an embodiment of the present invention will be described.
Step 1, providing a silicon wafer 200 as a substrate, and forming a silicon epitaxial layer 201 on the silicon substrate, as shown in fig. 2A;
the silicon wafer 200 and the silicon epitaxial layer 201 as semiconductor substrate material may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member, which may be a gate, a source, or a drain of a transistor, or the like, may be formed in the semiconductor substrate.
Step 2, forming an oxide layer 202, forming a first oxide layer 202 on the silicon epitaxial layer 201, and forming a trench, wherein the trench is formed in the first oxide layer 202 and the silicon epitaxial layer 201, and the first oxide layer is a thermal oxide layer TOX, as shown in fig. 2B;
various oxides, such as silicon dioxide, may be used for the first oxide layer 202. The first oxide layer may be fabricated by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), and the like.
After the trench is formed, the method further comprises the step of removing the first oxide 202 layer;
and 3, forming a second oxide layer 203 and filling the polysilicon 204, forming the second oxide layer 203 on the surface of the silicon epitaxial layer and in the trench, wherein the second oxide layer is a gate oxide layer GOX, depositing the polysilicon 204 on the surface of the gate oxide layer GOX, and filling the trench and the upper part of the trench.
In an embodiment, the method further includes a step of etching the polysilicon layer 204, in which the polysilicon layer 204 is etched, and the top height of the etched polysilicon layer 204 is lower than the top surface of the groove, as shown in fig. 2C;
the second oxide layer 203 may be made of various insulating materials, such as oxide, nitride, oxynitride, and the like. The second oxide layer may be fabricated by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), and the like. Illustratively, the second oxide layer employs a TEOS (tetraethylorthosilicate, Si (OC2H5)4) oxide, i.e., a silicon dioxide layer formed using TEOS (tetraethylorthosilicate, Si (OC2H5) 4). Illustratively, the second oxide layer 203 is fabricated by a furnace process, the process temperature is illustratively 680 degrees, and the thickness of the second oxide layer 203 is illustratively
Figure BDA0001855866740000071
Step 4, forming a well region 205, and implanting a well region of a second doping type, such as a P-well region 205, in the silicon epitaxial layer 201, as shown in fig. 2D;
optionally, the well region 205 may also be a first doping type, such as an N-well region;
step 5, forming an ILD207, and forming an interlayer dielectric layer 207 over the trench and the P-well region 205, as shown in fig. 2E;
the interlayer dielectric layer is deposited between different layers to isolate the conductive layer to be deposited next, and the interlayer dielectric layer is usually an insulating layer between the semiconductor layer and the metal layer, and can be a single-layer structure or a multi-layer structure.
Step 6, forming a hole 208, and forming a CT contact hole 208 on the interlayer dielectric layer 207, wherein the contact hole 208 extends from the top end to the bottom end of the interlayer dielectric layer 207, and the bottom end of the contact hole 208 is located on the upper surface of the P-well region 205, as shown in fig. 2F;
step 7, forming a first source/drain region 206, and forming the first source/drain region 206 in the well region 205, where the first source/drain region 206 is of a first doping type, for example, an N-type source/drain region, as shown in fig. 2G; the first source/drain regions 206 may also be of a second doping type, such as P-type source/drain regions.
The implantation of the N-type source/drain regions 206 is accomplished through the CT contact holes 208;
wherein the source/drain regions 206 are formed by implantation, an ion implantation doping process may be employed, in which an ion beam accelerated to a certain high energy is implanted into the surface layer of the solid material to change the physical and chemical properties of the surface layer. The surface conductivity of the semiconductor can be changed or a PN junction can be formed by implanting corresponding impurity atoms into the semiconductor (e.g., implanting boron, phosphorus, or arsenic into silicon) to form an N-type source/drain region, and implanting phosphorus or arsenic into silicon to form a P-type source/drain region, but the choice of the dopant is not limited to these.
It should be noted that, in the present specification, the first doping type and the second doping type generally refer to P type or N type, wherein the first doping type and the second doping type are opposite, for example, the first doping type is one of P type, low doping P-type, and high doping P + type, and the second doping type is one of N type, low doping N-type, and high doping N + type. Or conversely, the first doping type is one of an N type, a low-doping N-type and a high-doping N + type, and the second doping type is one of a P type, a low-doping P-type and a high-doping P + type.
Step 9, expanding the size of the first source/drain region 206 to expand it to the lateral region to make it larger in size and closer to the trench location, as shown in fig. 2H; the method for expanding the size of the first source/drain region can adopt heat treatment;
step 10, deepening the hole, and performing further processing, such as photolithography, on the CT contact hole 208 to deepen the contact hole 208, so that the bottom of the contact hole 208 is lower than the lower surface of the first source/drain region, as shown in fig. 2I;
step 11, forming a second source/drain region 209, and forming a second source/drain region 209, such as a P-type source/drain region, through the deepening hole 208, as shown in fig. 2J; the source/drain regions 209 may also be first doping type N-type source/drain regions.
In another embodiment, step 10 further comprises a filling step of CT contact holes;
step 12, forming a cellular structure, forming contact layers 2101 and 2102 above the interlayer dielectric layer ILD207 and below the silicon substrate, and forming leads respectively through the contact layers 2101 and 2102 to be connected to a source (S) and a drain (D), thereby forming the cellular structure, as shown in FIG. 2K. In the process of forming the trench, the polysilicon layer and/or the contact hole in steps 2, 3, 6 and 9, respectively, an etching method may be used, and the etching includes wet etching and/or dry etching. When the implantation operation is performed in steps 4, 7, and 10, a mask implantation is used.
The embodiment shown in figure 2 is comparable to the embodiment shown in figure 1,
the step of forming the first source/drain region is formed after the step of forming the CT contact hole by etching the interlayer dielectric layer, and a mask plate is not used in the process of forming the N-type source/drain region, so that the photoetching link in the manufacturing process is saved, the manufacturing cost is saved, the process complexity is reduced, and the production efficiency is improved.
Compared with the embodiment shown in fig. 1, only one first source/drain diffusion is added, the diffusion can be realized by adopting a thermal process, and the manufacturing process can be completely compatible with the existing process.
Because the first source/drain region mask plate and the corresponding photoetching link are not used in the process of forming the first source/drain region, the use of the mask plate and the photoetching process can be reduced in the process of forming the cellular device in the embodiment shown in the attached figure 2, and on the premise of being completely compatible with the existing process, the process complexity is reduced, the production efficiency is improved, the production cost is saved, and the like.
Reference is now made to fig. 3, which is a schematic diagram illustrating the steps associated with a method of fabricating a VDMOS device in accordance with an embodiment of the present invention. A method of manufacturing a semiconductor device, comprising:
step S101, providing a semiconductor substrate;
step S102, forming a groove in the semiconductor substrate;
step S103, forming an interlayer dielectric layer above the groove and the semiconductor substrate;
step S104, forming a contact hole on the interlayer dielectric layer, wherein the contact hole extends from the top end to the bottom end of the interlayer dielectric layer;
step S105, forming a first source/drain region through the contact hole by injection;
and S106, forming a second source/drain region through the contact hole by injection.
In another embodiment, the present invention also provides a semiconductor device including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed over the trench and the semiconductor substrate; a contact hole formed in the interlayer dielectric layer and the semiconductor substrate; a first source/drain region and a second source/drain region, both formed by the contact hole.
The semiconductor device further comprises a well region formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
The semiconductor device further includes contact layers formed above and below the semiconductor device, respectively, connected to the source and drain electrodes, thereby forming a cell structure.
According to the analysis, the invention can save a source/drain region mask plate, and simultaneously save the manufacturing photoetching link and the manufacturing cost. The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (12)

1. A semiconductor device, comprising:
a semiconductor substrate;
a trench formed in the semiconductor substrate;
an interlayer dielectric layer formed over the trench and the semiconductor substrate;
a contact hole formed in the interlayer dielectric layer and the semiconductor substrate;
a first source/drain region and a second source/drain region, both formed by the contact hole.
2. The semiconductor device according to claim 1, further comprising
And the well region is formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
3. The semiconductor device according to claim 1 or 2, wherein a size of the first source/drain region is larger than a size of the second source/drain region.
4. The semiconductor device according to claim 1 or 2, further comprising: and contact layers respectively formed above and below the semiconductor device and connected to the source and drain electrodes to form a cell structure.
5. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a groove in the semiconductor substrate;
forming an interlayer dielectric layer over the trench and the semiconductor substrate;
forming a contact hole on the interlayer dielectric layer, the contact hole extending from the top to the bottom of the interlayer dielectric layer;
forming a first source/drain region by injecting through the contact hole;
and forming a second source/drain region by injecting through the contact hole.
6. The method of manufacturing of claim 5, further comprising: and forming a well region, wherein the well region is formed in the semiconductor substrate, and the first source/drain region and the second source/drain region are both formed in the well region.
7. The method of manufacturing of claim 5, further comprising, between the steps of forming the first source/drain region and the second source/drain region, the steps of: the first source/drain region is extended closer to the trench.
8. The method of manufacturing of claim 7, wherein extending the first source/drain region is accomplished using a thermal process.
9. The manufacturing method of claim 5, further comprising a step of deepening the hole, which is further processed after the first source/drain region is formed, to deepen the contact hole such that a bottom of the contact hole is lower than a lower surface of the first source/drain region.
10. The manufacturing method of claim 9, wherein the second source/drain region is formed using the deepened contact hole.
11. The manufacturing method according to any one of claims 5 to 10, further comprising a step of filling the contact hole.
12. The manufacturing method according to any one of claims 5 to 10,
and forming contact layers above the interlayer dielectric layer and below the semiconductor substrate, and respectively forming leads through the contact layers to be connected with the source electrode and the drain electrode so as to form a cellular structure.
CN201811314323.2A 2018-11-06 2018-11-06 Semiconductor device and manufacturing method thereof Pending CN111146288A (en)

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Application publication date: 20200512