CN117711937A

CN117711937A - Semiconductor device, preparation method thereof and electronic device

Info

Publication number: CN117711937A
Application number: CN202311785225.8A
Authority: CN
Inventors: 黄旭波; 孙思瑶; 汪旭东
Original assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Current assignee: Xinlian Integrated Circuit Manufacturing Co ltd
Priority date: 2023-12-22
Filing date: 2023-12-22
Publication date: 2024-03-15

Abstract

The invention provides a semiconductor device, a preparation method thereof and an electronic device, wherein the method comprises the following steps: providing a substrate, wherein at least two deep trenches are formed in the substrate, and the deep trenches are filled with a grid material layer; ion implantation is carried out on the substrate between the adjacent deep trenches so as to form ion implantation areas; performing an annealing process in an oxygen-containing atmosphere to oxidize a partial region adjoining the deep trench in the ion implantation region into an oxide; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the ion implantation region and the gate material layer; and etching the interlayer dielectric layer and the non-oxidized ion implantation region in sequence to form a contact hole. According to the invention, after ion implantation, an annealing process is performed in an oxygen-containing atmosphere to oxidize part of the ion implantation region, and the non-oxidized ion implantation region is etched to form the contact hole, so that the contact hole is prevented from being deviated.

Description

Semiconductor device, preparation method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.

Background

An IGBT (insulated Gate bipolar Transistor) is a common power device, and is composed of a BJT (Bipolar Junction Transistor, bipolar Transistor (Metal Oxide Semiconductor, insulated Gate field effect Transistor)), and the ideal IGBT has advantages of high breakdown voltage, low on-voltage drop, short off time, and long short-circuit resistance.

The IGBT process in the related art generally uses a photolithography mask to define a pattern, for example, contact hole etching is performed by photoresist coating and mask alignment, however, the contact Kong Jiyi in the related art is shifted to a single side, which affects the threshold voltage of the device and the saturation voltage drop of the collector-emitter, and even causes chip shorting.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the problems existing at present, an aspect of an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:

providing a substrate, wherein at least two deep trenches are formed in the substrate, and a grid material layer is filled in the deep trenches;

performing ion implantation on the substrate between the adjacent deep trenches to form ion implantation regions;

performing an annealing process in an oxygen-containing atmosphere to oxidize a partial region adjacent to the deep trench in the ion implantation region into an oxide;

forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the ion implantation region and the gate material layer;

and etching the interlayer dielectric layer and the ion implantation region which is not oxidized in sequence to form a contact hole.

In one embodiment, the thickness of the oxide decreases gradually in a direction away from the deep trench.

In one embodiment, the oxide is symmetrically distributed on both sides of the ion implantation region.

In one embodiment, the contact holes include a first contact hole in the interlayer dielectric layer and a second contact hole in the ion implantation region;

the width of the first contact hole is larger than that of the second contact hole.

In one embodiment, the etching the interlayer dielectric layer and the ion implantation region that is not oxidized sequentially to form a contact hole includes:

etching the interlayer dielectric layer to form a first contact hole exposing the whole surface of the non-oxidized ion implantation region;

and etching the non-oxidized ion implantation area exposed at the bottom of the first contact hole to form the second contact hole.

In one embodiment, a gate dielectric layer is also formed in the deep trench, the gate dielectric layer being located between the gate material layer and the substrate.

In one embodiment, the ion implantation implant is performed with N-type dopant ions.

In one embodiment, the etching comprises dry etching.

In another aspect, the embodiment of the invention provides a semiconductor device, which is prepared by the method.

In one embodiment, the semiconductor device comprises an insulated gate bipolar transistor.

In still another aspect, an embodiment of the present invention provides an electronic apparatus, including the semiconductor device described above.

According to the semiconductor device, the preparation method of the semiconductor device and the electronic device, an annealing process is performed in an oxygen-containing atmosphere after ion implantation to oxidize partial areas adjacent to the grooves in the ion implantation area into oxides, the oxides are symmetrically positioned on two sides of the non-oxidized ion implantation area, namely the non-oxidized ion implantation area is positioned in the middle of the adjacent deep groove, and the non-oxidized ion implantation area is etched to form contact holes, so that the formed contact holes are not deviated, the problem of deviation of the contact holes is solved, and the product yield is improved.

Drawings

The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.

In the accompanying drawings:

fig. 1A and 1B show schematic cross-sectional views of a related art semiconductor device;

fig. 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 3A to 3D are schematic cross-sectional views showing a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

In the related art, as shown in fig. 1A and 1B, a semiconductor device includes a substrate 100, a deep trench, a gate material layer 101, a gate dielectric layer 102, and a contact hole 103. In the related art, a photolithography mask is generally used to define a pattern, for example, contact hole etching is performed by photoresist coating and mask alignment, and generally, the contact hole 103 should be located in the middle of the adjacent deep trench as shown in fig. 1A, but during the pattern transfer process, the front layer process is very easy to cause deformation of the wafer, and thus the accuracy is inaccurate during alignment, resulting in a problem that the etched contact hole 103 is shifted to a single side as shown in fig. 1B. For example, the contact hole 103 in fig. 1B is significantly offset to the left. Generally, in order to reduce the contact resistance of the contact hole 103, ion impurities are implanted into the contact hole 103, the ion impurities at the bottom of the contact hole 103 are spread laterally to two sides at a certain activation temperature, and the offset of the contact hole 103 can cause the ion impurities to enter a channel region at one side, so that the threshold voltage and the collector-emitter saturation voltage drop of the device can be affected, and even when the contact hole 103 is offset to a deep trench, chip shorting can be caused.

Therefore, in view of the foregoing technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, which mainly includes the following steps:

step S210, providing a substrate, wherein at least two deep trenches are formed in the substrate, and the deep trenches are filled with a gate material layer;

step S220, carrying out ion implantation on the substrate between the adjacent deep trenches to form ion implantation regions;

step S230, performing an annealing process in an oxygen-containing atmosphere to oxidize a partial region adjacent to the deep trench in the ion implantation region into oxide;

step S240, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the ion implantation region and the gate material layer;

step S250, etching the interlayer dielectric layer and the ion implantation region that is not oxidized in order to form a contact hole.

According to the preparation method of the semiconductor device, after ion implantation, an annealing process is performed under an oxygen-containing atmosphere to oxidize partial areas adjacent to the grooves in the ion implantation area into oxides, the oxides are symmetrically positioned on two sides of the non-oxidized ion implantation area, namely the non-oxidized ion implantation area is positioned in the middle of the adjacent deep groove, and the non-oxidized ion implantation area is etched to form contact holes, so that the formed contact holes are not deviated, the problem of deviation of the contact holes is solved, and the product yield is improved.

Example 1

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3D, wherein fig. 3A to 3D are schematic cross-sectional views of semiconductor devices obtained by sequentially implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device in the embodiment of the present invention includes an IGBT device, and the semiconductor device may be any suitable device known to those skilled in the art, and in this embodiment, the technical solution of the present application is mainly explained and illustrated by taking the case where the semiconductor device is an IGBT device as an example.

Illustratively, the method for manufacturing the semiconductor device according to the embodiment of the invention comprises the following steps:

first, as shown in fig. 3A, a substrate 300 is provided, in which at least two deep trenches 301 are formed, the deep trenches 301 being filled with a gate material layer 302.

In one example, the substrate 300 may include at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductor, or substrate 300 may also comprise silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which substrate 300 may be formed are described herein, any material that may serve as substrate 300 falls within the spirit and scope of the present application.

Illustratively, the substrate 300 includes a semiconductor base and an epitaxial layer formed on the semiconductor base. Alternatively, the semiconductor substrate and the epitaxial layer may have the same conductivity type. For example, the semiconductor substrate and the epitaxial layer may have different doping concentrations, e.g., the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor substrate, alternatively, the epitaxial layer may act as a drift region of the semiconductor device of the present application. In one embodiment, the substrate 300 may be of an N-type conductivity type, and in other embodiments, the substrate 300 may also be of a P-type conductivity type, and in particular, a suitable substrate may be selected according to the type of device.

Next, at least two deep trenches 301 are formed in the substrate 300 extending from the first surface of the substrate 300 into the substrate 300, a gate material layer 302 is formed in the deep trenches 301, and the gate material layer 302 fills the deep trenches 301 of partial depth. Illustratively, the gate material layer 302 is comprised of a polysilicon material, and metals, metal nitrides, metal silicides, or similar compounds may also be generally used as the gate layer material.

In one example, as shown in fig. 3A, a gate dielectric layer 303 is also formed in the deep trench 301, the gate dielectric layer 303 covering the bottom and sidewalls of the deep trench 301 and being located between the gate material layer 302 and the substrate 300. Alternatively, the gate dielectric layer 303 may comprise conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, gate dielectric layer 303 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).

Next, ion implantation is performed on the substrate 300 between adjacent deep trenches 301 to form ion implanted regions 304, and then an annealing process is performed under an oxygen-containing atmosphere to oxidize partial regions of the ion implanted regions 304 adjacent to the deep trenches 301 to oxides 305.

As shown in fig. 3B, the ion implantation region 304 extends from the first surface of the substrate 300 into the substrate 300. Illustratively, the ion implantation region 304 has the same conductivity type as the substrate 300, in this embodiment, both the substrate 300 and the ion implantation region 304 are of an N-type conductivity type. Illustratively, the doping concentration of the ion-implanted region 304 is greater than the doping concentration of the substrate 300. The ion implantation region 304 may serve as a source region for an IGBT device.

Performing an annealing process after the ion implantation process can activate the dopant ions within the ion implantation region 304 while repairing lattice damage caused by the ion implantation process. In one example, as shown in fig. 3B, the region of the first surface of the substrate 300 adjacent to the deep trench 301 is oxidized to an oxide 305 while the annealing process is performed under an oxygen-containing atmosphere. Specifically, after ion implantation, the region of the first surface of the substrate 300 adjacent to the deep trench 301 has a higher doping concentration, and taking the substrate 300 made of silicon as an example, silicon with a high doping concentration is easy to react with oxygen to generate silicon oxide when an annealing process is performed in an oxygen-containing atmosphere. By way of example, any suitable annealing process known to those skilled in the art may be employed, such as rapid thermal annealing, furnace tube annealing, and the like.

In one example, as shown in fig. 3B, the thickness of the oxide 305 gradually decreases in a direction away from the deep trench 301. Further, the oxide 305 is symmetrically located at both sides of the ion implantation region 304, so that the ion implantation region 304 is located in the middle of the adjacent deep trench 301 without being offset to one side.

In one example, body regions can also be formed in the substrate, the body regions being located between adjacent deep trenches 301, and ion implantation regions 304 being located on and in contact with the body regions. Illustratively, the body region has a different conductivity type than the substrate 300, e.g., the substrate 300 is of an N-type conductivity type and the body region is of a P-type conductivity type. Illustratively, the body region is formed using a standard ion implantation process, which may be combined with a high energy ion implantation and a high temperature thermal annealing process. Illustratively, the body region is of a P-type conductivity and the ion implantation region 304 is of an N-type conductivity, an N-channel may be formed in the body region. Illustratively, since the channel is to be formed in the body region, the depth of the deep trench 301 is greater than the depth of the body region, so that the channel can be formed due to the flow of carriers in the body region on both sides of the deep trench 301.

As shown in fig. 3C, after the ion implantation region 304 is formed, an interlayer dielectric layer 306 is deposited, the interlayer dielectric layer 306 covering the ion implantation region 304 and covering the gate material layer 302. Then, the interlayer dielectric layer 306 and the non-oxidized ion implantation region 304 are sequentially etched to form a contact hole. Wherein the contact holes include a first contact hole 307 located in the interlayer dielectric layer 306 and a second contact hole 308 located in the ion implantation region, wherein a width of the first contact hole 307 is greater than a width of the second contact hole 308.

Specifically, the interlayer dielectric layer 306 is etched first to form a plurality of first contact holes 307, and the first contact holes 307 expose at least the entire surface of the non-oxidized ion implantation region 304. Illustratively, the interlayer dielectric layer 306 may be formed using various deposition methods commonly used in the art, and may be formed, for example, by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. Illustratively, the interlayer dielectric layer 306 may be made of silicon dioxide, fluorocarbon, carbon doped silicon oxide, or silicon carbonitride, which is not limited in this application.

In one example, etching the interlayer dielectric layer 306 to form the plurality of first contact holes 307 includes the steps of: forming a patterned masking layer, such as a photoresist layer, over the interlayer dielectric layer 306; the interlayer dielectric layer 306 is etched using the mask layer as a mask to form a plurality of first contact holes 307. Dry etching may be selected for this step, including but not limited to Reactive Ion Etching (RIE), ion beam etching, plasma etching, and the like.

Next, the non-oxidized ion implantation region 304 exposed at the bottom of the first contact hole 307 is etched to form a second contact hole 308. The etching step uses the oxide 305 as a mask to perform self-aligned etching on the non-oxidized ion implantation region 304, so that etching can be ensured to only occur in the non-oxidized ion implantation region 304, but not in the oxide 305, and even if the pattern of the mask layer formed on the interlayer dielectric layer 306 is offset, the second contact hole 308 is not offset.

Specifically, the material of the substrate 300 includes silicon, the material of the oxide 305 includes silicon oxide, and the oxide 305 is symmetrically located at two sides of the non-oxidized ion implantation region 304, so that the non-oxidized ion implantation region 304 is located in the middle of the adjacent deep trench 301 and is not offset to a single side, a dry etching process with high etching ratio anisotropy to silicon can be used to etch the non-oxidized ion implantation region 304 to form the second contact hole 308, and the surface position of the non-oxidized ion implantation region 304 defines the opening position of the second contact hole 308, so that the finally formed second contact hole is not offset to the single side, and the problem of contact hole offset is solved.

In one example, as shown in fig. 3D, the second contact hole 308 extends through the ion implantation region 304 and into the body region, such that the second contact hole 308 simultaneously leads out the ion implantation region 304 and the body region.

In one example, after forming the first contact hole 307 and the second contact hole 308, filling a metal material in the first contact hole 307 and the second contact hole 308 to form a contact plug is further included. Illustratively, the material of the contact plug includes, but is not limited to, copper, tungsten, gold, silver, aluminum, and the like.

The method for manufacturing the semiconductor device of the present invention has the advantages that the key steps of the method for manufacturing the semiconductor device of the present invention are described, and other steps can be included in the manufacture of the complete semiconductor device, which is not described in detail herein, and it is worth mentioning that the sequence of the steps can be adjusted on the premise of no conflict.

In summary, in the method for manufacturing a semiconductor device according to the embodiment of the invention, after ion implantation, an annealing process is performed in an oxygen-containing atmosphere to oxidize a partial region adjacent to a trench in an ion implantation region into an oxide, the oxide is symmetrically located at two sides of the unoxidized ion implantation region, that is, the unoxidized ion implantation region is located in the middle of an adjacent deep trench, and the unoxidized ion implantation region is etched in a self-aligned manner by taking the oxide as a mask to form a contact hole, so that the formed contact hole is not deviated, the problem of deviation of the contact hole is solved, and the product yield is improved.

Example two

The embodiment of the invention also provides a semiconductor device, which is prepared by the method in the first embodiment. Specifically, as shown in fig. 3D, the semiconductor device includes a substrate 300, a gate material layer 302, an ion implantation region 304, an oxide 305, and a contact hole 309, wherein: the gate material layer 302 is located in the deep trench 301 and fills the deep trench 301 at least partially deep; an interlayer dielectric layer 306 is covered on the substrate 300 and the gate material layer 302, a first contact hole 307 is formed in the interlayer dielectric layer 306, a second contact hole 308 is formed in the ion implantation region 304 at the bottom of the first contact hole 307, and the oxide 305 is located at two sides of the second contact hole 308.

Illustratively, the semiconductor device of the embodiments of the present invention includes an IGBT device (insulated Gate bipolar Transistor), which may also be any suitable device known to those skilled in the art.

The description of the structure of the semiconductor device according to the embodiment of the present invention is completed, and the complete device may further include other constituent structures, which are not described herein in detail. Since the semiconductor device is manufactured by the method described above, the same advantages as those of the method described above are obtained.

Example III

In another embodiment of the present invention, an electronic apparatus is provided, including the semiconductor device described above.

The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.

Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

2. The method of claim 1, wherein the oxide thickness decreases gradually in a direction away from the deep trench.

3. The method of claim 1, wherein the oxide is symmetrically distributed on both sides of the ion implantation region.

4. The method of manufacturing according to claim 1, wherein the contact hole includes a first contact hole in the interlayer dielectric layer and a second contact hole in the ion implantation region;

5. The method of claim 4, wherein etching the interlayer dielectric layer and the ion implantation region that is not oxidized in order to form a contact hole comprises:

6. The method of claim 1, wherein the ion implantation implant is performed with N-type dopant ions.

7. The method of manufacturing according to claim 1, wherein the etching comprises dry etching.

8. A semiconductor device, characterized in that it is manufactured by the method according to any one of claims 1 to 7.

9. The semiconductor device of claim 8, wherein the semiconductor device comprises an insulated gate bipolar transistor.

10. An electronic device, characterized in that the electronic device comprises the semiconductor device according to claim 8 or 9.