CN112216743A - Trench power semiconductor device and manufacturing method - Google Patents

Trench power semiconductor device and manufacturing method Download PDF

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CN112216743A
CN112216743A CN202011171440.5A CN202011171440A CN112216743A CN 112216743 A CN112216743 A CN 112216743A CN 202011171440 A CN202011171440 A CN 202011171440A CN 112216743 A CN112216743 A CN 112216743A
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layer
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朱袁正
周锦程
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Wuxi NCE Power Co Ltd
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Wuxi NCE Power Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention relates to a trench power semiconductor device and a manufacturing method thereof, wherein the trench power semiconductor device comprises drain metal, a first conductive type substrate, a first conductive type epitaxial layer, a first type trench, a second type trench, a third type trench, a first type oxide layer, a second type oxide layer, a third type oxide layer, first type conductive polycrystalline silicon, second type conductive polycrystalline silicon, third type conductive polycrystalline silicon, a second conductive type body region, a first conductive type source region, an insulating medium layer, source metal, an active region, a first transition region and a second transition region; the thickness of the first type oxide layer is smaller than that of the second type oxide layer and that of the third type oxide layer, and the thicknesses of the second type oxide layer and the third type oxide layer are equal. According to the invention, because the thickness of the first-class oxide layer is smaller than that of the second-class oxide layer, the third-class oxide layer and the fourth-class oxide layer, the terminal breakdown voltage can be ensured to be higher than the cellular breakdown voltage, and the reliability of the device is improved.

Description

Trench power semiconductor device and manufacturing method
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a trench power semiconductor device and a manufacturing method thereof.
Background
At present, a plurality of field limiting rings are mostly adopted by a terminal of a common trench MOSFET product to form a terminal structure, so that at least 6 photoetching plates are required: the method comprises the steps of etching a groove, etching a terminal oxide layer, injecting a first conductive type source region, etching a contact hole, etching a metal and etching a passivation layer. In order to further reduce the cost and improve the competitiveness of the product, a product with only 5 photolithography masks needs to be developed.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a trench power semiconductor device and a manufacturing method thereof, which can reduce the production cost of products and can ensure that the manufacturing method of the device is compatible with the prior semiconductor process.
According to the technical scheme provided by the invention, the trench power semiconductor device comprises drain metal, a first conductive type substrate, a first conductive type epitaxial layer, a first type trench, a second type trench, a third type trench, a first type oxide layer, a second type oxide layer, a third type oxide layer, first type conductive polycrystalline silicon, second type conductive polycrystalline silicon, third type conductive polycrystalline silicon, a second conductive type body region, a first conductive type source region, an insulating medium layer, source metal, an active region, a first transition region and a second transition region;
a first conduction type substrate is arranged on the drain metal, a first conduction type epitaxial layer is arranged on the first conduction type substrate, a second conduction type body region is arranged on the first conduction type epitaxial layer, the central region of the trench power semiconductor device is set as an active region, the periphery of the active region is set as a first transition region, and the periphery of the first transition region is set as a second transition region;
in the active area, a first conduction type source area is arranged on a second conduction type body area, a first groove penetrates through the second conduction type body area from the upper surface of the first conduction type source area to enter a first conduction type epitaxial layer, a first oxide layer is arranged on the side wall and the bottom surface of the first groove, first conductive polycrystalline silicon is arranged in the first oxide layer, the first conductive polycrystalline silicon is insulated from the first conduction type epitaxial layer, the second conduction type body area and the first conduction type source area through the first oxide layer, and an insulating medium layer is arranged on the first oxide layer, the first conductive polycrystalline silicon and the first conduction type source area;
in the first transition region, the second type groove penetrates through the second conductive type body region from the upper surface of the second conductive type body region to enter the first conductive type epitaxial layer, a second type oxide layer is arranged on the side wall and the bottom surface of the second type groove, second type conductive polycrystalline silicon is arranged in the second type oxide layer, the second type conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer and the second conductive type body region through the second type oxide layer, and insulating medium layers are arranged on the second type oxide layer, the second type conductive polycrystalline silicon and the second conductive type body region;
in the second transition region, the third type of groove penetrates through the second conductive type body region from the upper surface of the second conductive type body region to enter the first conductive type epitaxial layer, a third type of oxide layer is arranged on the side wall and the bottom surface of the third type of groove, third type of conductive polycrystalline silicon is arranged in the third type of oxide layer, the third type of conductive polycrystalline silicon is insulated from the first conductive type epitaxial layer and the second conductive type body region through the third type of oxide layer, and insulating medium layers are arranged on the third type of oxide layer, the third type of conductive polycrystalline silicon and the second conductive type body region;
in the active region, a source electrode metal is arranged on the insulating medium layer and is in ohmic contact with the first conduction type source region and the second conduction type body region through a through hole arranged in the insulating medium layer; in the first transition region, the source metal is in ohmic contact with the second conductive type body region through a through hole arranged in the insulating medium layer; in the second transition region, the source metal is in ohmic contact with the third conductive polysilicon through a through hole arranged in the insulating medium layer;
the thickness of the first type oxide layer is smaller than that of the second type oxide layer and that of the third type oxide layer, and the thicknesses of the second type oxide layer and the third type oxide layer are equal.
Preferably, the terminal area is further provided, and a fourth type trench, a fourth type oxide layer, a fourth type conductive polysilicon and a metal bridge are arranged in the terminal area;
the terminal region is arranged at the periphery of the second transition region, the fourth type of groove penetrates through the second conduction type body region from the upper surface of the second conduction type body region to the lower part and enters the first conduction type epitaxial layer, a fourth type oxide layer is arranged on the side wall and the bottom surface of the fourth type groove, a fourth type conductive polycrystalline silicon is arranged in the fourth type oxide layer, the fourth type conductive polycrystalline silicon is insulated with the first conductive type epitaxial layer and the second conductive type body region through the fourth type oxide layer, an insulating medium layer is arranged on the fourth type oxide layer, the fourth type conductive polycrystalline silicon and the second conductive type body region, in the terminal area, a metal bridge is arranged on the insulating medium layer, one end of the metal bridge is in ohmic contact with the fourth type conductive polycrystalline silicon through a through hole in the insulating medium layer, and the other end of the metal bridge is in ohmic contact with a second conductive type body area on one side adjacent to the fourth type groove through a through hole in the insulating medium layer;
the thickness of the first type oxide layer is smaller than that of the second type oxide layer, that of the third type oxide layer and that of the fourth type oxide layer, and the thicknesses of the second type oxide layer, that of the third type oxide layer and that of the fourth type oxide layer are equal.
Preferably, the semiconductor device further comprises a first well region of the second conductivity type, a second well region of the second conductivity type, and a third well region of the second conductivity type;
and a first well region of the second conduction type is arranged below the second type of groove, a second well region of the second conduction type is arranged below the third type of groove, and a third well region of the second conduction type is arranged below the fourth type of groove.
Preferably, a first conductivity type well region is further provided; and arranging a first conductive type well region below the first-type groove.
Preferably, a terminal area is further arranged, and a fourth type groove, a second conductive type third well region, a fourth type oxide layer and a fourth type conductive polysilicon are arranged in the terminal area;
the terminal region is arranged at the periphery of the second transition region, the fourth type groove penetrates through the second conductive type body region from the upper surface of the second conductive type body region to enter the first conductive type epitaxial layer, a fourth type oxide layer is arranged on the side wall and the bottom surface of the fourth type groove, fourth type conductive polycrystalline silicon is arranged in the fourth type oxide layer, the fourth type conductive polycrystalline silicon is insulated with the first conductive type epitaxial layer and the second conductive type body region through the fourth type oxide layer, and insulating medium layers are arranged on the fourth type oxide layer, the fourth type conductive polycrystalline silicon and the second conductive type body region;
a first conductive type well region is arranged below the first type groove, a second conductive type first well region is arranged below the second type groove, a second conductive type second well region is arranged below the third type groove, and a second conductive type third well region is arranged below the fourth type groove.
Preferably, the thickness of the second type oxide layer and the thickness of the third type oxide layer are both 1000A-10000A.
Preferably, the thicknesses of the second type oxide layer, the third type oxide layer and the fourth type oxide layer are all 1000A-10000A.
Preferably, the fourth type of conductive polysilicon in the termination region is arranged in a floating manner.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, forming a first conductive type first epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities, and annealing to form a second conductive type body region;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove, a second type groove and a third type groove;
step three: depositing an isolation oxidation barrier layer, and selectively etching and removing the isolation oxidation barrier layer in the first transition region and the second transition region by using a second photoetching plate;
step four: carrying out thermal growth on an oxide layer on the chip, and forming a second oxide layer in the first transition region; forming a third type oxide layer in the second transition region;
step five: removing the isolation oxidation barrier layer in the active region;
step six: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer in the active region;
step seven: depositing conductive polycrystalline silicon, then etching the conductive polycrystalline silicon, only reserving the conductive polycrystalline silicon in the first type groove, the second type groove and the third type groove, and forming the first type conductive polycrystalline silicon, the second type conductive polycrystalline silicon and the third type conductive polycrystalline silicon;
step eight: generally injecting first conductive type impurities, and forming a first conductive type source region after activation;
step nine: depositing an insulating medium layer;
step ten: selectively etching the insulating medium layer and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form source metal; and depositing a passivation layer on the back surface of the first conductive type substrate, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, forming a first conductive type first epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities, and annealing to form a second conductive type body region;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove, a second type groove, a third type groove and a fourth type groove;
step three: depositing an isolation oxidation barrier layer, and selectively etching and removing the isolation oxidation barrier layer in the first transition region, the second transition region and the terminal region by using a second photoetching plate;
step four: carrying out thermal growth on an oxide layer on the chip, and forming a second oxide layer in the first transition region; forming a third type oxide layer in the second transition region; forming a fourth type oxide layer in the terminal area;
step five: removing the isolation oxidation barrier layer in the active region;
step six: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer in the active region;
step seven: depositing conductive polycrystalline silicon, then etching the conductive polycrystalline silicon, only reserving the conductive polycrystalline silicon in the first type groove, the second type groove, the third type groove and the fourth type groove to form the first type conductive polycrystalline silicon, the second type conductive polycrystalline silicon, the third type conductive polycrystalline silicon and the fourth type conductive polycrystalline silicon;
step eight: generally injecting first conductive type impurities, and forming a first conductive type source region after activation;
step nine: depositing an insulating medium layer;
step ten: selectively etching the insulating medium layer and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal and a metal bridge; and depositing a passivation layer on the back surface of the first conductive type substrate, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, forming a first conductive type first epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities, and annealing to form a second conductive type body region;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove, a second type groove, a third type groove and a fourth type groove;
step three: depositing an isolation oxidation barrier layer, and selectively etching and removing the isolation oxidation barrier layer in the first transition region, the second transition region and the terminal region by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region, a second conductive type second well region and a second conductive type third well region;
step five: carrying out thermal growth on an oxide layer on the chip, and forming a second oxide layer in the first transition region; forming a third type oxide layer in the second transition region; forming a fourth type oxide layer in the terminal area;
step six: removing the isolation oxidation barrier layer in the active region;
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer in the active region;
step eight: depositing conductive polycrystalline silicon, then etching the conductive polycrystalline silicon, only reserving the conductive polycrystalline silicon in the first type groove, the second type groove, the third type groove and the fourth type groove to form the first type conductive polycrystalline silicon, the second type conductive polycrystalline silicon, the third type conductive polycrystalline silicon and the fourth type conductive polycrystalline silicon;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region after activation;
step ten: depositing an insulating medium layer;
step eleven: selectively etching the insulating medium layer and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal and a metal bridge; and depositing a passivation layer on the back surface of the first conductive type substrate, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, forming a first conductive type first epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities, and annealing to form a second conductive type body region;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove, a second type groove, a third type groove and a fourth type groove;
step three: depositing an isolation oxidation barrier layer, and selectively etching and removing the isolation oxidation barrier layer in the first transition region, the second transition region and the terminal region by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region, a second conductive type second well region and a second conductive type third well region;
step five: carrying out thermal growth on an oxide layer on the chip, and forming a second oxide layer in the first transition region; forming a third type oxide layer in the second transition region; forming a fourth type oxide layer in the terminal area;
step six: removing the isolation oxidation barrier layer in the active region, generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region;
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer in the active region;
step eight: depositing conductive polycrystalline silicon, then etching the conductive polycrystalline silicon, only reserving the conductive polycrystalline silicon in the first type groove, the second type groove, the third type groove and the fourth type groove to form the first type conductive polycrystalline silicon, the second type conductive polycrystalline silicon, the third type conductive polycrystalline silicon and the fourth type conductive polycrystalline silicon;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region after activation;
step ten: depositing an insulating medium layer;
step eleven: selectively etching the insulating medium layer and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: and forming a metal layer on the surface of the chip, selectively etching the metal layer by using a fourth photoetching plate to form a source metal and metal bridge, depositing a passivation layer, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming a drain metal.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, forming a first conductive type first epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities, and annealing to form a second conductive type body region;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove, a second type groove, a third type groove and a fourth type groove;
step three: depositing an isolation oxidation barrier layer, and selectively etching and removing the isolation oxidation barrier layer in the first transition region, the second transition region and the terminal region by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region, a second conductive type second well region and a second conductive type third well region;
step five: carrying out thermal growth on an oxide layer on the chip, and forming a second oxide layer in the first transition region; forming a third type oxide layer in the second transition region; forming a fourth type oxide layer in the terminal area;
step six: removing the isolation oxidation barrier layer in the active region, generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region;
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer in the active region;
step eight: depositing conductive polycrystalline silicon, then etching the conductive polycrystalline silicon, only reserving the conductive polycrystalline silicon in the first type groove, the second type groove, the third type groove and the fourth type groove to form the first type conductive polycrystalline silicon, the second type conductive polycrystalline silicon, the third type conductive polycrystalline silicon and the fourth type conductive polycrystalline silicon;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region after activation;
step ten: depositing an insulating medium layer;
step eleven: selectively etching the insulating medium layer and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form source metal; and depositing a passivation layer on the back surface of the first conductive type substrate, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal.
According to the invention, because the thickness of the first-class oxide layer is smaller than that of the second-class oxide layer, the third-class oxide layer and the fourth-class oxide layer, the terminal breakdown voltage can be ensured to be higher than the cellular breakdown voltage, and the reliability of the device is improved. The invention reduces the production cost of the product, the device manufacturing method is compatible with the existing semiconductor process, and the invention can finish the production of the common groove MOSFET product only by 5 photoetching plates.
Drawings
Fig. 1 is a schematic structural view of embodiment 1 of the present invention.
Fig. 2 is a schematic structural diagram of embodiment 2 of the present invention.
Fig. 3 is a schematic structural diagram of embodiment 3 of the present invention.
Fig. 4 is a schematic structural diagram of embodiment 4 of the present invention.
Fig. 5 is a schematic structural diagram of embodiment 5 of the present invention.
Fig. 6 is a schematic cross-sectional view illustrating the formation of a second conductivity type body region in embodiment 4 of the present invention.
Fig. 7 is a schematic cross-sectional structural diagram of forming a first type trench, a second type trench, a third type trench, and a fourth type trench in embodiment 4 of the present invention.
Fig. 8 is a schematic cross-sectional structure diagram of depositing an isolation oxidation barrier layer and etching to remove the isolation oxidation barrier layer in the first transition region, the second transition region and the termination region in embodiment 4 of the present invention.
Fig. 9 is a schematic cross-sectional view of a second conductive type first well region, a second conductive type second well region, and a second conductive type third well region formed in embodiment 4 of the present invention.
Fig. 10 is a schematic cross-sectional structure view of forming a second type oxide layer, a third type oxide layer, and a fourth type oxide layer in embodiment 4 of the present invention.
Fig. 11 is a schematic cross-sectional structure diagram of removing the isolation oxidation barrier layer in the active region according to embodiment 4 of the present invention.
Fig. 12 is a schematic cross-sectional structure diagram of forming a first type oxide layer in an active region according to embodiment 4 of the present invention.
Fig. 13 is a schematic cross-sectional structure diagram of forming the first type of conductive polysilicon, the second type of conductive polysilicon, the third type of conductive polysilicon, and the fourth type of conductive polysilicon in embodiment 4 of the present invention.
Fig. 14 is a schematic cross-sectional structure diagram of forming a first conductivity type source region in embodiment 4 of the present invention.
FIG. 15 is a schematic cross-sectional view of an insulating dielectric layer deposited according to embodiment 4 of the present invention.
Fig. 16 is a schematic cross-sectional view of a through-hole formed in embodiment 4 of the present invention.
Fig. 17 is a schematic cross-sectional view illustrating the formation of source metal, metal bridge and drain metal in embodiment 4 of the present invention.
Detailed Description
The present invention will be further described with reference to the following specific examples.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.
The present invention includes several embodiments, it should be explained that for an N-type power semiconductor device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity; for a P-type power semiconductor device, the first conductivity type described herein is P-type conductivity and the second conductivity type is N-type conductivity.
Example 1
A trench power semiconductor device comprises a drain metal 1, a first conductive type substrate 2, a first conductive type epitaxial layer 3, a first type trench 4, a second type trench 5, a third type trench 6, a first type oxide layer 12, a second type oxide layer 13, a third type oxide layer 14, a first type conductive polysilicon 16, a second type conductive polysilicon 17, a third type conductive polysilicon 18, a second conductive type body region 20, a first conductive type source region 21, an insulating medium layer 22 and a source metal 23;
a first conductive type substrate 2 is arranged on the drain metal 1, a first conductive type epitaxial layer 3 is arranged on the first conductive type substrate 2, a second conductive type body region 20 is arranged on the first conductive type epitaxial layer 3, the central region of the trench power semiconductor device is set as an active region 001, the periphery of the active region 001 is set as a first transition region 002, and the periphery of the first transition region 002 is set as a second transition region 003;
in the active region 001, a first conductive type source region 21 is arranged on the second conductive type body region 20, the first type groove 4 penetrates the second conductive type body region 20 from the upper surface of the first conductive type source region 21 to enter the first conductive type epitaxial layer 3, a first type oxide layer 12 is arranged on the side wall and the bottom surface of the first type groove 4, a first type conductive polysilicon 16 is arranged in the first type oxide layer 12, the first type conductive polysilicon 16 is connected with a grid potential, the first type conductive polysilicon 16 is insulated from the first conductive type epitaxial layer 3, the second conductive type body region 20 and the first conductive type source region 21 through the first type oxide layer 12, and an insulating medium layer 22 is arranged on the first type oxide layer 12, the first type conductive polysilicon 16 and the first conductive type source region 21;
in the first transition region 002, two second-type trenches 5 are arranged in the second conductive type body region 20, the second-type trenches 5 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 downwards to enter the first conductive type epitaxial layer 3, a second-type oxide layer 13 is arranged on the side wall and the bottom surface of each second-type trench 5, second-type conductive polysilicon 17 is arranged in each second-type oxide layer 13, the second-type conductive polysilicon 17 is connected with a grid potential or a source potential, the second-type conductive polysilicon 17 is insulated with the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the second-type oxide layer 13, and an insulating medium layer 22 is arranged on each second-type oxide layer 13, each second-type conductive polysilicon 17 and each second conductive type body region 20;
in the second transition region 003, two strip-shaped third trenches 6 are arranged in the second conductivity type body region 20, the third trenches 6 penetrate through the second conductivity type body region 20 from the upper surface of the second conductivity type body region 20 to enter the first conductivity type epitaxial layer 3, third oxide layers 14 are arranged on the side walls and the bottom of the third trenches 6, third conductive polysilicon 18 is arranged in the third oxide layers 14, the third conductive polysilicon 18 is connected with a gate potential or a source potential, the third conductive polysilicon 18 is insulated from the first conductivity type epitaxial layer 3 and the second conductivity type body region 20 by the third oxide layers 14, and insulating medium layers 22 are arranged on the third oxide layers 14, the third conductive polysilicon 18 and the second conductivity type body region 20;
in the active region 001, a source metal 23 is provided on the insulating dielectric layer 22, and the source metal 23 is in ohmic contact with the first conductivity type source region 21 and the second conductivity type body region 20 through a through hole provided in the insulating dielectric layer 22; in the first transition region 002, the source metal 23 is in ohmic contact with the second conductivity-type body region 20 through a via hole provided in the insulating dielectric layer 22; in the second transition region 003, the source metal 23 is in ohmic contact with the third type of conductive polysilicon 18 through a via provided in the insulating dielectric layer 22.
The thickness of the first type oxide layer 12 is smaller than the thickness of the second type oxide layer 13 and the thickness of the third type oxide layer 14, the thickness of the second type oxide layer 13 is equal to the thickness of the third type oxide layer 14, and the thickness of the second type oxide layer 13 is 1000A-10000A than the thickness of the third type oxide layer 14.
The width of the first type of trench 4 is smaller than the width of the second type of trench 5 and the third type of trench 6.
The method for manufacturing a trench power semiconductor device according to embodiment 1 includes the steps of:
the method comprises the following steps: providing a first conductive type substrate 2, forming a first conductive type first epitaxial layer 3 on the first conductive type substrate 2, then injecting second conductive type impurities, and forming a second conductive type body region 20 after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove 4, a second type groove 5 and a third type groove 6;
step three: depositing an isolation oxidation barrier layer 25, and selectively etching and removing the isolation oxidation barrier layer 25 in the first transition region 002 and the second transition region 003 by using a second photoetching plate;
step four: thermally growing an oxide layer on the chip to form a second oxide layer 13 in the first transition region 002; forming a third-type oxide layer 14 in the second transition region 003;
step five: removing the isolation oxidation barrier layer 25 in the active region 001;
step six: carrying out thermal growth of an oxide layer on the chip, and forming a first type oxide layer 12 in the active region 001;
step seven: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first-type groove 4, the second-type groove 5 and the third-type groove 6 to form first-type conductive polysilicon 16, second-type conductive polysilicon 17 and third-type conductive polysilicon 18;
step eight: generally injecting first conductive type impurities, and forming a first conductive type source region 21 after activation;
step nine: depositing an insulating dielectric layer 22;
step ten: selectively etching the insulating medium layer 22 and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal 23; a passivation layer is deposited on the back surface of the first conductive type substrate 2, and then the passivation layer is selectively etched using a fifth photolithography plate, and finally the drain metal 1 is formed.
In this embodiment, since the thickness of the first type oxide layer 12 is smaller than the thicknesses of the second type oxide layer 13 and the third type oxide layer 14, the breakdown voltage of the terminal can be ensured to be much higher than the breakdown voltage of the cell, and the reliability of the device is improved.
This embodiment can be used in low voltage common trench MOSFET products.
Example 2
A trench power semiconductor device comprises a drain metal 1, a first conduction type substrate 2, a first conduction type epitaxial layer 3, a first type trench 4, a second type trench 5, a third type trench 6, a fourth type trench 7, a first type oxide layer 12, a second type oxide layer 13, a third type oxide layer 14, a fourth type oxide layer 15, a first type conduction polysilicon 16, a second type conduction polysilicon 17, a third type conduction polysilicon 18, a fourth type conduction polysilicon 19, a second conduction type body region 20, a first conduction type source region 21, an insulating medium layer 22, a source metal 23 and a metal bridge 24;
a first conductivity type substrate 2 is provided on the drain metal 1, a first conductivity type epitaxial layer 3 is provided on the first conductivity type substrate 2, a second conductivity type body region 20 is provided on the first conductivity type epitaxial layer 3, the central region of the trench power semiconductor device is set as an active region 001, the periphery of the active region 001 is set as a first transition region 002, the periphery of the first transition region 002 is set as a second transition region 003, and the periphery of the second transition region 003 is set as a terminal region 004;
in the active region 001, a first conductive type source region 21 is arranged on the second conductive type body region 20, the first type groove 4 penetrates the second conductive type body region 20 from the upper surface of the first conductive type source region 21 to enter the first conductive type epitaxial layer 3, a first type oxide layer 12 is arranged on the side wall and the bottom surface of the first type groove 4, a first type conductive polysilicon 16 is arranged in the first type oxide layer 12, the first type conductive polysilicon 16 is connected with a grid potential, the first type conductive polysilicon 16 is insulated from the first conductive type epitaxial layer 3, the second conductive type body region 20 and the first conductive type source region 21 through the first type oxide layer 12, and an insulating medium layer 22 is arranged on the first type oxide layer 12, the first type conductive polysilicon 16 and the first conductive type source region 21;
in the first transition region 002, two second-type trenches 5 are arranged in the second conductive type body region 20, the second-type trenches 5 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 downwards to enter the first conductive type epitaxial layer 3, a second-type oxide layer 13 is arranged on the side wall and the bottom surface of each second-type trench 5, second-type conductive polysilicon 17 is arranged in each second-type oxide layer 13, the second-type conductive polysilicon 17 is connected with a grid potential or a source potential, the second-type conductive polysilicon 17 is insulated with the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the second-type oxide layer 13, and an insulating medium layer 22 is arranged on each second-type oxide layer 13, each second-type conductive polysilicon 17 and each second conductive type body region 20;
in the second transition region 003, two strip-shaped third trenches 6 are arranged in the second conductivity type body region 20, the third trenches 6 penetrate through the second conductivity type body region 20 from the upper surface of the second conductivity type body region 20 to enter the first conductivity type epitaxial layer 3, third oxide layers 14 are arranged on the side walls and the bottom of the third trenches 6, third conductive polysilicon 18 is arranged in the third oxide layers 14, the third conductive polysilicon 18 is connected with a gate potential or a source potential, the third conductive polysilicon 18 is insulated from the first conductivity type epitaxial layer 3 and the second conductivity type body region 20 by the third oxide layers 14, and insulating medium layers 22 are arranged on the third oxide layers 14, the third conductive polysilicon 18 and the second conductivity type body region 20;
in the termination region 004, two strip-shaped fourth grooves 7 are arranged in the second conductive type body region 20, the fourth grooves 7 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 to enter the first conductive type epitaxial layer 3, fourth oxide layers 15 are arranged on the side wall and the bottom surface of each fourth groove 7, fourth conductive polycrystalline silicon 19 is arranged in each fourth oxide layer 15, the fourth conductive polycrystalline silicon 19 is insulated from the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the fourth oxide layers 15, and insulating medium layers 22 are arranged on the fourth oxide layers 15, the fourth conductive polycrystalline silicon 19 and the second conductive type body region 20;
in the active region 001, a source metal 23 is provided on the insulating dielectric layer 22, and the source metal 23 is in ohmic contact with the first conductivity type source region 21 and the second conductivity type body region 20 through a through hole provided in the insulating dielectric layer 22; in the first transition region 002, the source metal 23 is in ohmic contact with the second conductivity-type body region 20 through a via hole provided in the insulating dielectric layer 22; in the second transition region 003, the source metal 23 is in ohmic contact with the third type of conductive polysilicon 18 through a through hole arranged in the insulating dielectric layer 22; in the terminal region 004, the insulating medium layer 22 is provided with a metal bridge 24, one end of the metal bridge 24 is in ohmic contact with the fourth type conductive polysilicon 19 through a through hole on the insulating medium layer 22, and the other end of the metal bridge 24 is in ohmic contact with the second conductive type body region 20 on the adjacent side of the fourth type groove 7 through a through hole on the insulating medium layer 22.
The thickness of the first type oxide layer 12 is smaller than the thickness of the second type oxide layer 13, the third type oxide layer 14 and the fourth type oxide layer 15.
The second type oxide layer 13 and the third type oxide layer 14 are the same as the fourth type oxide layer 15 in thickness, and the thicknesses of the second type oxide layer and the fourth type oxide layer are both 1000A-10000A.
The groove widths of the second type groove 5, the third type groove 6 and the fourth type groove 7 are all larger than the groove width of the first type groove 4.
The fourth type of conductive polysilicon 19 in the termination region 004 is in a floating arrangement.
The method for manufacturing a trench power semiconductor device according to embodiment 2 includes the steps of:
the method comprises the following steps: providing a first conductive type substrate 2, forming a first conductive type first epitaxial layer 3 on the first conductive type substrate 2, then injecting second conductive type impurities, and forming a second conductive type body region 20 after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove 4, a second type groove 5, a third type groove 6 and a fourth type groove 7;
step three: depositing an isolation oxidation barrier layer 25, and selectively etching and removing the isolation oxidation barrier layer 25 in the first transition region 002, the second transition region 003 and the terminal region 004 by using a second photoetching plate;
step four: thermally growing an oxide layer on the chip to form a second oxide layer 13 in the first transition region 002; forming a third-type oxide layer 14 in the second transition region 003; forming a fourth type oxide layer 15 in the termination region 004;
step five: removing the isolation oxidation barrier layer 25 in the active region 001;
step six: carrying out thermal growth of an oxide layer on the chip, and forming a first type oxide layer 12 in the active region 001;
step seven: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first-type groove 4, the second-type groove 5, the third-type groove 6 and the fourth-type groove 7 to form first-type conductive polysilicon 16, second-type conductive polysilicon 17, third-type conductive polysilicon 18 and fourth-type conductive polysilicon 19;
step eight: generally injecting first conductive type impurities, and forming a first conductive type source region 21 after activation;
step nine: depositing an insulating dielectric layer 22;
step ten: selectively etching the insulating medium layer 22 and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal 23 and a metal bridge 24; a passivation layer is deposited on the back surface of the first conductive type substrate 2, and then the passivation layer is selectively etched using a fifth photolithography plate, and finally the drain metal 1 is formed.
In this embodiment, since the thickness of the first type oxide layer 12 is smaller than the thicknesses of the second type oxide layer 13, the third type oxide layer 14, and the fourth type oxide layer 15, the breakdown voltage of the terminal can be ensured to be much higher than the breakdown voltage of the cell, and the reliability of the device is improved.
This embodiment can be used in low voltage common trench MOSFET products.
Example 3
A trench power semiconductor device comprises drain metal 1, a first conduction type substrate 2, a first conduction type epitaxial layer 3, a first type trench 4, a second type trench 5, a third type trench 6, a fourth type trench 7, a second conduction type first well region 9, a second conduction type second well region 10, a second conduction type third well region 11, a first type oxide layer 12, a second type oxide layer 13, a third type oxide layer 14, a fourth type oxide layer 15, first type conductive polysilicon 16, second type conductive polysilicon 17, third type conductive polysilicon 18, fourth type conductive polysilicon 19, a second conduction type body region 20, a first conduction type source region 21, an insulating medium layer 22, source metal 23 and a metal bridge 24;
a first conductivity type substrate 2 is provided on the drain metal 1, a first conductivity type epitaxial layer 3 is provided on the first conductivity type substrate 2, a second conductivity type body region 20 is provided on the first conductivity type epitaxial layer 3, the central region of the trench power semiconductor device is set as an active region 001, the periphery of the active region 001 is set as a first transition region 002, the periphery of the first transition region 002 is set as a second transition region 003, and the periphery of the second transition region 003 is set as a terminal region 004;
in the active region 001, a first conductive type source region 21 is arranged on the second conductive type body region 20, the first type groove 4 penetrates the second conductive type body region 20 from the upper surface of the first conductive type source region 21 to enter the first conductive type epitaxial layer 3, a first type oxide layer 12 is arranged on the side wall and the bottom surface of the first type groove 4, a first type conductive polysilicon 16 is arranged in the first type oxide layer 12, the first type conductive polysilicon 16 is connected with a grid potential, the first type conductive polysilicon 16 is insulated from the first conductive type epitaxial layer 3, the second conductive type body region 20 and the first conductive type source region 21 through the first type oxide layer 12, and an insulating medium layer 22 is arranged on the first type oxide layer 12, the first type conductive polysilicon 16 and the first conductive type source region 21;
in the first transition region 002, two second-type trenches 5 are arranged in the second conductive type body region 20, the second-type trenches 5 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 downwards to enter the first conductive type epitaxial layer 3, a second-type oxide layer 13 is arranged on the side wall and the bottom surface of each second-type trench 5, second-type conductive polysilicon 17 is arranged in each second-type oxide layer 13, the second-type conductive polysilicon 17 is connected with a grid potential or a source potential, the second-type conductive polysilicon 17 is insulated with the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the second-type oxide layer 13, and an insulating medium layer 22 is arranged on each second-type oxide layer 13, each second-type conductive polysilicon 17 and each second conductive type body region 20;
in the second transition region 003, two strip-shaped third trenches 6 are arranged in the second conductivity type body region 20, the third trenches 6 penetrate through the second conductivity type body region 20 from the upper surface of the second conductivity type body region 20 to enter the first conductivity type epitaxial layer 3, third oxide layers 14 are arranged on the side walls and the bottom of the third trenches 6, third conductive polysilicon 18 is arranged in the third oxide layers 14, the third conductive polysilicon 18 is connected with a gate potential or a source potential, the third conductive polysilicon 18 is insulated from the first conductivity type epitaxial layer 3 and the second conductivity type body region 20 by the third oxide layers 14, and insulating medium layers 22 are arranged on the third oxide layers 14, the third conductive polysilicon 18 and the second conductivity type body region 20;
in the termination region 004, two strip-shaped fourth grooves 7 are arranged in the second conductive type body region 20, the fourth grooves 7 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 to enter the first conductive type epitaxial layer 3, fourth oxide layers 15 are arranged on the side wall and the bottom surface of each fourth groove 7, fourth conductive polycrystalline silicon 19 is arranged in each fourth oxide layer 15, the fourth conductive polycrystalline silicon 19 is insulated from the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the fourth oxide layers 15, and insulating medium layers 22 are arranged on the fourth oxide layers 15, the fourth conductive polycrystalline silicon 19 and the second conductive type body region 20;
in the active region 001, a source metal 23 is provided on the insulating dielectric layer 22, and the source metal 23 is in ohmic contact with the first conductivity type source region 21 and the second conductivity type body region 20 through a through hole provided in the insulating dielectric layer 22; in the first transition region 002, the source metal 23 is in ohmic contact with the second conductivity-type body region 20 through a via hole provided in the insulating dielectric layer 22; in the second transition region 003, the source metal 23 is in ohmic contact with the third type of conductive polysilicon 18 through a through hole arranged in the insulating dielectric layer 22; in the terminal region 004, a metal bridge 24 is arranged on the insulating medium layer 22, one end of the metal bridge 24 is in ohmic contact with the fourth type conductive polysilicon 19 through a through hole on the insulating medium layer 22, and the other end of the metal bridge 24 is in ohmic contact with the second conductive type body region 20 on the adjacent side of the fourth type groove 7 through a through hole on the insulating medium layer 22;
a first well region 9 of the second conductivity type is disposed below the second-type trench 5, a second well region 10 of the second conductivity type is disposed below the third-type trench 6, and a third well region 11 of the second conductivity type is disposed below the fourth-type trench 7.
The thickness of the first type oxide layer 12 is smaller than the thickness of the second type oxide layer 13, the third type oxide layer 14 and the fourth type oxide layer 15.
The second type oxide layer 13 and the third type oxide layer 14 are the same as the fourth type oxide layer 15 in thickness, and the thicknesses of the second type oxide layer and the fourth type oxide layer are both 1000A-10000A.
The groove widths of the second type groove 5, the third type groove 6 and the fourth type groove 7 are all larger than the groove width of the first type groove 4.
The fourth type of conductive polysilicon 19 in the termination region 004 is in a floating arrangement.
The method for manufacturing a trench power semiconductor device according to embodiment 3 includes the steps of:
the method comprises the following steps: providing a first conductive type substrate 2, forming a first conductive type first epitaxial layer 3 on the first conductive type substrate 2, then injecting second conductive type impurities, and forming a second conductive type body region 20 after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove 4, a second type groove 5, a third type groove 6 and a fourth type groove 7;
step three: depositing an isolation oxidation barrier layer 25, and selectively etching and removing the isolation oxidation barrier layer 25 in the first transition region 002, the second transition region 003 and the terminal region 004 by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region 9, a second conductive type second well region 10 and a second conductive type third well region 11;
step five: thermally growing an oxide layer on the chip to form a second oxide layer 13 in the first transition region 002; forming a third-type oxide layer 14 in the second transition region 003; forming a fourth type oxide layer 15 in the termination region 004;
step six: removing the isolation oxidation barrier layer 25 in the active region 001;
step seven: carrying out thermal growth of an oxide layer on the chip, and forming a first type oxide layer 12 in the active region 001;
step eight: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first-type groove 4, the second-type groove 5, the third-type groove 6 and the fourth-type groove 7 to form first-type conductive polysilicon 16, second-type conductive polysilicon 17, third-type conductive polysilicon 18 and fourth-type conductive polysilicon 19;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region 21 after activation;
step ten: depositing an insulating dielectric layer 22;
step eleven: selectively etching the insulating medium layer 22 and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal 23 and a metal bridge 24; a passivation layer is deposited on the back surface of the first conductive type substrate 2, and then the passivation layer is selectively etched using a fifth photolithography plate, and finally the drain metal 1 is formed.
In this embodiment, since the thickness of the first type oxide layer 12 is smaller than the thicknesses of the second type oxide layer 13, the third type oxide layer 14, and the fourth type oxide layer 15, the breakdown voltage of the terminal can be ensured to be much higher than the breakdown voltage of the cell, and the reliability of the device is improved.
This embodiment can be used in low voltage common trench MOSFET products.
Example 4
A trench power semiconductor device comprises a drain metal 1, a first conduction type substrate 2, a first conduction type epitaxial layer 3, a first type trench 4, a second type trench 5, a third type trench 6, a fourth type trench 7, a first conduction type well region 8, a second conduction type first well region 9, a second conduction type second well region 10, a second conduction type third well region 11, a first type oxide layer 12, a second type oxide layer 13, a third type oxide layer 14, a fourth type oxide layer 15, a first type conductive polysilicon 16, a second type conductive polysilicon 17, a third type conductive polysilicon 18, a fourth type conductive polysilicon 19, a second conduction type body region 20, a first conduction type source region 21, an insulating medium layer 22, a source metal 23 and a metal bridge 24;
a first conductivity type substrate 2 is provided on the drain metal 1, a first conductivity type epitaxial layer 3 is provided on the first conductivity type substrate 2, a second conductivity type body region 20 is provided on the first conductivity type epitaxial layer 3, the central region of the trench power semiconductor device is set as an active region 001, the periphery of the active region 001 is set as a first transition region 002, the periphery of the first transition region 002 is set as a second transition region 003, and the periphery of the second transition region 003 is set as a terminal region 004;
in the active region 001, a first conductive type source region 21 is arranged on the second conductive type body region 20, the first type groove 4 penetrates the second conductive type body region 20 from the upper surface of the first conductive type source region 21 to enter the first conductive type epitaxial layer 3, a first type oxide layer 12 is arranged on the side wall and the bottom surface of the first type groove 4, a first type conductive polysilicon 16 is arranged in the first type oxide layer 12, the first type conductive polysilicon 16 is connected with a grid potential, the first type conductive polysilicon 16 is insulated from the first conductive type epitaxial layer 3, the second conductive type body region 20 and the first conductive type source region 21 through the first type oxide layer 12, and an insulating medium layer 22 is arranged on the first type oxide layer 12, the first type conductive polysilicon 16 and the first conductive type source region 21;
in the first transition region 002, two second-type trenches 5 are arranged in the second conductive type body region 20, the second-type trenches 5 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 downwards to enter the first conductive type epitaxial layer 3, a second-type oxide layer 13 is arranged on the side wall and the bottom surface of each second-type trench 5, second-type conductive polysilicon 17 is arranged in each second-type oxide layer 13, the second-type conductive polysilicon 17 is connected with a grid potential or a source potential, the second-type conductive polysilicon 17 is insulated with the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the second-type oxide layer 13, and an insulating medium layer 22 is arranged on each second-type oxide layer 13, each second-type conductive polysilicon 17 and each second conductive type body region 20;
in the second transition region 003, two strip-shaped third trenches 6 are arranged in the second conductivity type body region 20, the third trenches 6 penetrate through the second conductivity type body region 20 from the upper surface of the second conductivity type body region 20 to enter the first conductivity type epitaxial layer 3, third oxide layers 14 are arranged on the side walls and the bottom of the third trenches 6, third conductive polysilicon 18 is arranged in the third oxide layers 14, the third conductive polysilicon 18 is connected with a gate potential or a source potential, the third conductive polysilicon 18 is insulated from the first conductivity type epitaxial layer 3 and the second conductivity type body region 20 by the third oxide layers 14, and insulating medium layers 22 are arranged on the third oxide layers 14, the third conductive polysilicon 18 and the second conductivity type body region 20;
in the termination region 004, two strip-shaped fourth grooves 7 are arranged in the second conductive type body region 20, the fourth grooves 7 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 to enter the first conductive type epitaxial layer 3, fourth oxide layers 15 are arranged on the side wall and the bottom surface of each fourth groove 7, fourth conductive polycrystalline silicon 19 is arranged in each fourth oxide layer 15, the fourth conductive polycrystalline silicon 19 is insulated from the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the fourth oxide layers 15, and insulating medium layers 22 are arranged on the fourth oxide layers 15, the fourth conductive polycrystalline silicon 19 and the second conductive type body region 20;
in the active region 001, a source metal 23 is provided on the insulating dielectric layer 22, and the source metal 23 is in ohmic contact with the first conductivity type source region 21 and the second conductivity type body region 20 through a through hole provided in the insulating dielectric layer 22; in the first transition region 002, the source metal 23 is in ohmic contact with the second conductivity-type body region 20 through a via hole provided in the insulating dielectric layer 22; in the second transition region 003, the source metal 23 is in ohmic contact with the third type of conductive polysilicon 18 through a through hole arranged in the insulating dielectric layer 22; in the terminal region 004, the insulating medium layer 22 is provided with a metal bridge 24, one end of the metal bridge 24 is in ohmic contact with the fourth type conductive polysilicon 19 through a through hole on the insulating medium layer 22, and the other end of the metal bridge 24 is in ohmic contact with the second conductive type body region 20 on the adjacent side of the fourth type groove 7 through a through hole on the insulating medium layer 22.
A first well region 9 of the second conductivity type is disposed below the second-type trench 5, a second well region 10 of the second conductivity type is disposed below the third-type trench 6, and a third well region 11 of the second conductivity type is disposed below the fourth-type trench 7.
The thickness of the first type oxide layer 12 is smaller than the thickness of the second type oxide layer 13, the third type oxide layer 14 and the fourth type oxide layer 15.
The second type oxide layer 13 and the third type oxide layer 14 are the same as the fourth type oxide layer 15 in thickness, and the thicknesses of the second type oxide layer and the fourth type oxide layer are both 1000A-10000A.
The groove widths of the second type groove 5, the third type groove 6 and the fourth type groove 7 are all larger than the groove width of the first type groove 4.
The fourth type of conductive polysilicon 19 in the termination region 004 is in a floating arrangement.
The method for manufacturing a trench power semiconductor device according to embodiment 4 includes the steps of:
the method comprises the following steps: providing a first conductive type substrate 2, forming a first conductive type first epitaxial layer 3 on the first conductive type substrate 2, then injecting second conductive type impurities, and forming a second conductive type body region 20 after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove 4, a second type groove 5, a third type groove 6 and a fourth type groove 7;
step three: depositing an isolation oxidation barrier layer 25, and selectively etching and removing the isolation oxidation barrier layer 25 in the first transition region 002, the second transition region 003 and the terminal region 004 by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region 9, a second conductive type second well region 10 and a second conductive type third well region 11;
step five: thermally growing an oxide layer on the chip to form a second oxide layer 13 in the first transition region 002; forming a third-type oxide layer 14 in the second transition region 003; forming a fourth type oxide layer 15 in the termination region 004;
step six: removing the isolation oxidation barrier layer 25 in the active region 001, generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region 8;
step seven: carrying out thermal growth of an oxide layer on the chip, and forming a first type oxide layer 12 in the active region 001;
step eight: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first-type groove 4, the second-type groove 5, the third-type groove 6 and the fourth-type groove 7 to form first-type conductive polysilicon 16, second-type conductive polysilicon 17, third-type conductive polysilicon 18 and fourth-type conductive polysilicon 19;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region 21 after activation;
step ten: depositing an insulating dielectric layer 22;
step eleven: selectively etching the insulating medium layer 22 and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: and forming a metal layer on the surface of the chip, selectively etching the metal layer by using a fourth photoetching plate to form a source metal 23 and a metal bridge 24, depositing a passivation layer, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming a drain metal 1.
In this embodiment, since the thickness of the first type oxide layer 12 is smaller than the thicknesses of the second type oxide layer 13, the third type oxide layer 14, and the fourth type oxide layer 15, the breakdown voltage of the terminal can be ensured to be much higher than the breakdown voltage of the cell, and the reliability of the device is improved. The invention can also freely adjust the breakdown voltage in the unit cell by adjusting the doping concentration of the first conductive type well region 8.
This embodiment can be used in low voltage common trench MOSFET products.
Example 5
A trench power semiconductor device comprises a drain metal 1, a first conduction type substrate 2, a first conduction type epitaxial layer 3, a first type trench 4, a second type trench 5, a third type trench 6, a fourth type trench 7, a first conduction type well region 8, a second conduction type first well region 9, a second conduction type second well region 10, a second conduction type third well region 11, a first type oxide layer 12, a second type oxide layer 13, a third type oxide layer 14, a fourth type oxide layer 15, a first type conductive polysilicon 16, a second type conductive polysilicon 17, a third type conductive polysilicon 18, a fourth type conductive polysilicon 19, a second conduction type body region 20, a first conduction type source region 21, an insulating medium layer 22 and a source metal 23;
a first conductivity type substrate 2 is provided on the drain metal 1, a first conductivity type epitaxial layer 3 is provided on the first conductivity type substrate 2, a second conductivity type body region 20 is provided on the first conductivity type epitaxial layer 3, the central region of the trench power semiconductor device is set as an active region 001, the periphery of the active region 001 is set as a first transition region 002, the periphery of the first transition region 002 is set as a second transition region 003, and the periphery of the second transition region 003 is set as a terminal region 004;
in the active region 001, a first conductive type source region 21 is arranged on the second conductive type body region 20, the first type groove 4 penetrates the second conductive type body region 20 from the upper surface of the first conductive type source region 21 to enter the first conductive type epitaxial layer 3, a first type oxide layer 12 is arranged on the side wall and the bottom surface of the first type groove 4, a first type conductive polysilicon 16 is arranged in the first type oxide layer 12, the first type conductive polysilicon 16 is connected with a grid potential, the first type conductive polysilicon 16 is insulated from the first conductive type epitaxial layer 3, the second conductive type body region 20 and the first conductive type source region 21 through the first type oxide layer 12, and an insulating medium layer 22 is arranged on the first type oxide layer 12, the first type conductive polysilicon 16 and the first conductive type source region 21;
in the first transition region 002, two second-type trenches 5 are arranged in the second conductive type body region 20, the second-type trenches 5 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 downwards to enter the first conductive type epitaxial layer 3, a second-type oxide layer 13 is arranged on the side wall and the bottom surface of each second-type trench 5, second-type conductive polysilicon 17 is arranged in each second-type oxide layer 13, the second-type conductive polysilicon 17 is connected with a grid potential or a source potential, the second-type conductive polysilicon 17 is insulated with the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the second-type oxide layer 13, and an insulating medium layer 22 is arranged on each second-type oxide layer 13, each second-type conductive polysilicon 17 and each second conductive type body region 20;
in the second transition region 003, two strip-shaped third trenches 6 are arranged in the second conductivity type body region 20, the third trenches 6 penetrate through the second conductivity type body region 20 from the upper surface of the second conductivity type body region 20 to enter the first conductivity type epitaxial layer 3, third oxide layers 14 are arranged on the side walls and the bottom of the third trenches 6, third conductive polysilicon 18 is arranged in the third oxide layers 14, the third conductive polysilicon 18 is connected with a gate potential or a source potential, the third conductive polysilicon 18 is insulated from the first conductivity type epitaxial layer 3 and the second conductivity type body region 20 by the third oxide layers 14, and insulating medium layers 22 are arranged on the third oxide layers 14, the third conductive polysilicon 18 and the second conductivity type body region 20;
in the termination region 004, two strip-shaped fourth grooves 7 are arranged in the second conductive type body region 20, the fourth grooves 7 penetrate through the second conductive type body region 20 from the upper surface of the second conductive type body region 20 to enter the first conductive type epitaxial layer 3, fourth oxide layers 15 are arranged on the side wall and the bottom surface of each fourth groove 7, fourth conductive polycrystalline silicon 19 is arranged in each fourth oxide layer 15, the fourth conductive polycrystalline silicon 19 is insulated from the first conductive type epitaxial layer 3 and the second conductive type body region 20 through the fourth oxide layers 15, and insulating medium layers 22 are arranged on the fourth oxide layers 15, the fourth conductive polycrystalline silicon 19 and the second conductive type body region 20;
in the active region 001, a source metal 23 is provided on the insulating dielectric layer 22, and the source metal 23 is in ohmic contact with the first conductivity type source region 21 and the second conductivity type body region 20 through a through hole provided in the insulating dielectric layer 22; in the first transition region 002, the source metal 23 is in ohmic contact with the second conductivity-type body region 20 through a via hole provided in the insulating dielectric layer 22; in the second transition region 003, the source metal 23 is in ohmic contact with the third type of conductive polysilicon 18 through a through hole arranged in the insulating dielectric layer 22; a first conductive type well region 8 is arranged below the first type trench 4, a second conductive type first well region 9 is arranged below the second type trench 5, a second conductive type second well region 10 is arranged below the third type trench 6, and a second conductive type third well region 11 is arranged below the fourth type trench 7.
The thickness of the first type oxide layer 12 is smaller than the thickness of the second type oxide layer 13, the third type oxide layer 14 and the fourth type oxide layer 15.
The second type oxide layer 13 and the third type oxide layer 14 are the same as the fourth type oxide layer 15 in thickness, and the thicknesses of the second type oxide layer and the fourth type oxide layer are both 1000A-10000A.
The groove widths of the second type groove 5, the third type groove 6 and the fourth type groove 7 are all larger than the groove width of the first type groove 4.
The fourth type of conductive polysilicon 19 in the termination region 004 is in a floating arrangement.
The method for manufacturing a trench power semiconductor device according to embodiment 5 includes the steps of:
the method comprises the following steps: providing a first conductive type substrate 2, forming a first conductive type first epitaxial layer 3 on the first conductive type substrate 2, then injecting second conductive type impurities, and forming a second conductive type body region 20 after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove 4, a second type groove 5, a third type groove 6 and a fourth type groove 7;
step three: depositing an isolation oxidation barrier layer 25, and selectively etching and removing the isolation oxidation barrier layer 25 in the first transition region 002, the second transition region 003 and the terminal region 004 by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region 9, a second conductive type second well region 10 and a second conductive type third well region 11;
step five: thermally growing an oxide layer on the chip to form a second oxide layer 13 in the first transition region 002; forming a third-type oxide layer 14 in the second transition region 003; forming a fourth type oxide layer 15 in the termination region 004;
step six: removing the isolation oxidation barrier layer 25 in the active region 001, generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region 8;
step seven: carrying out thermal growth of an oxide layer on the chip, and forming a first type oxide layer 12 in the active region 001;
step eight: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first-type groove 4, the second-type groove 5, the third-type groove 6 and the fourth-type groove 7 to form first-type conductive polysilicon 16, second-type conductive polysilicon 17, third-type conductive polysilicon 18 and fourth-type conductive polysilicon 19;
step nine: generally injecting first conductive type impurities, and forming a first conductive type source region 21 after activation;
step ten: depositing an insulating dielectric layer 22;
step eleven: selectively etching the insulating medium layer 22 and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal 23; a passivation layer is deposited on the back surface of the first conductive type substrate 2, and then the passivation layer is selectively etched using a fifth photolithography plate, and finally the drain metal 1 is formed.
In this embodiment, since the thickness of the first type oxide layer 12 is smaller than the thicknesses of the second type oxide layer 13, the third type oxide layer 14, and the fourth type oxide layer 15, the breakdown voltage of the terminal can be ensured to be much higher than the breakdown voltage of the cell, and the reliability of the device is improved. The invention can also freely adjust the breakdown voltage in the unit cell by adjusting the doping concentration of the first conductive type well region 8.
This embodiment can be used in low voltage common trench MOSFET products.
In the manufacturing method, in addition to using the isolation oxide barrier layer 25, the invention may also be configured to thermally grow a thick oxide layer in all trenches (including the first-type trench 4, the second-type trench 5, the third-type trench 6, and the fourth-type trench 7), and then selectively etch the thick oxide layer in the active region using a photolithography plate, so that the thickness of the first-type oxide layer 12 is smaller than the thicknesses of the second-type oxide layer 13, the third-type oxide layer 14, and the fourth-type oxide layer 15.
Those of ordinary skill in the art will understand that: the above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit of the present invention should be included in the scope of the present invention.

Claims (13)

1. A trench power semiconductor device comprises a drain metal (1), a first conductive type substrate (2), a first conductive type epitaxial layer (3), a first type trench (4), a second type trench (5), a third type trench (6), a first type oxide layer (12), a second type oxide layer (13), a third type oxide layer (14), a first type conductive polycrystalline silicon (16), a second type conductive polycrystalline silicon (17), a third type conductive polycrystalline silicon (18), a second conductive type body region (20), a first conductive type source region (21), an insulating dielectric layer (22), a source metal (23), an active region (001), a first transition region (002) and a second transition region (003);
a first conduction type substrate (2) is arranged on the drain metal (1), a first conduction type epitaxial layer (3) is arranged on the first conduction type substrate (2), a second conduction type body region (20) is arranged on the first conduction type epitaxial layer (3), the central region of the trench power semiconductor device is set to be an active region (001), the periphery of the active region (001) is set to be a first transition region (002), and the periphery of the first transition region (002) is set to be a second transition region (003);
in the active region (001), a first conductivity type source region (21) is provided on the second conductivity type body region (20), the first type trenches (4) penetrate the second conductivity type body region (20) from the upper surface of the first conductivity type source region (21) downwards into the first conductivity type epitaxial layer (3), a first-class oxide layer (12) is arranged on the side wall and the bottom surface of the first-class groove (4), a first type of conductive polysilicon (16) is arranged in the first type of oxide layer (12), the first type of conductive polysilicon (16) is insulated from the first conductive type epitaxial layer (3), the second conductive type body region (20) and the first conductive type source region (21) through the first type of oxide layer (12), an insulating medium layer (22) is arranged on the first type oxide layer (12), the first type conductive polycrystalline silicon (16) and the first conductive type source region (21);
in the first transition region (002), the second type groove (5) penetrates through the second conductive type body region (20) from the upper surface of the second conductive type body region (20) to enter the first conductive type epitaxial layer (3) downwards, a second type oxide layer (13) is arranged on the side wall and the bottom surface of the second type groove (5), second type conductive polycrystalline silicon (17) is arranged in the second type oxide layer (13), the second type conductive polycrystalline silicon (17) is insulated with the first conductive type epitaxial layer (3) and the second conductive type body region (20) through the second type oxide layer (13), and an insulating medium layer (22) is arranged on the second type oxide layer (13), the second type conductive polycrystalline silicon (17) and the second conductive type body region (20);
in the second transition region (003), the third type trench (6) penetrates through the second conductive type body region (20) from the upper surface of the second conductive type body region (20) to the lower part and enters the first conductive type epitaxial layer (3), a third type oxide layer (14) is arranged on the side wall and the bottom surface of the third type trench (6), third type conductive polycrystalline silicon (18) is arranged in the third type oxide layer (14), the third type conductive polycrystalline silicon (18) is insulated from the first conductive type epitaxial layer (3) and the second conductive type body region (20) through the third type oxide layer (14), and an insulating medium layer (22) is arranged on the third type oxide layer (14), the third type conductive polycrystalline silicon (18) and the second conductive type body region (20);
in the active region (001), a source metal (23) is arranged on the insulating medium layer (22), and the source metal (23) is in ohmic contact with the first conduction type source region (21) and the second conduction type body region (20) through a through hole arranged in the insulating medium layer (22); in the first transition region (002), the source metal (23) is in ohmic contact with the second conductivity type body region (20) through a via hole provided in the insulating dielectric layer (22); in the second transition region (003), the source metal (23) is in ohmic contact with the third type of conductive polysilicon (18) through a through hole arranged in the insulating dielectric layer (22);
the method is characterized in that: the thickness of the first type oxide layer (12) is smaller than the thickness of the second type oxide layer (13) and the thickness of the third type oxide layer (14), and the thickness of the second type oxide layer (13) is equal to that of the third type oxide layer (14).
2. The trench power semiconductor device of claim 1 wherein: a terminal area (004) is further arranged, and a fourth type groove (7), a fourth type oxide layer (15), a fourth type conductive polycrystalline silicon (19) and a metal bridge (24) are arranged in the terminal area (004);
the termination region (004) is arranged at the periphery of the second transition region (003), the fourth groove (7) penetrates through the second conductive type body region (20) from the upper surface of the second conductive type body region (20) to enter the first conductive type epitaxial layer (3) downwards, a fourth oxide layer (15) is arranged on the side wall and the bottom surface of the fourth groove (7), a fourth conductive polycrystalline silicon (19) is arranged in the fourth oxide layer (15), the fourth conductive polycrystalline silicon (19) is insulated with the first conductive type epitaxial layer (3) and the second conductive type body region (20) through the fourth oxide layer (15), an insulating medium layer (22) is arranged on the fourth oxide layer (15), the fourth conductive polycrystalline silicon (19) and the second conductive type body region (20), a metal bridge (24) is arranged on the insulating medium layer (22) in the termination region (004), one end of the metal bridge (24) is connected with the fourth conductive polycrystalline silicon (22) through a through hole in the insulating medium layer (22), and the metal bridge (24) is connected with the fourth conductive polycrystalline silicon (19) Ohmic contact is carried out, and the other end of the metal bridge (24) is in ohmic contact with the second conductive type body region (20) on one side adjacent to the fourth type groove (7) through a through hole in the insulating medium layer (22);
the thickness of the first type oxide layer (12) is smaller than the thickness of the second type oxide layer (13), the thickness of the third type oxide layer (14) and the thickness of the fourth type oxide layer (15), and the thickness of the second type oxide layer (13), the thickness of the third type oxide layer (14) and the thickness of the fourth type oxide layer (15) are equal.
3. The trench power semiconductor device of claim 2 wherein: the semiconductor device further comprises a first well region (9) of the second conduction type, a second well region (10) of the second conduction type and a third well region (11) of the second conduction type;
and a first well region (9) of the second conduction type is arranged below the second type of groove (5), a second well region (10) of the second conduction type is arranged below the third type of groove (6), and a third well region (11) of the second conduction type is arranged below the fourth type of groove (7).
4. The trench power semiconductor device of claim 3 wherein: a first conductivity type well region (8) is also provided; a first conductivity type well region (8) is arranged below the first type trench (4).
5. The trench power semiconductor device of claim 1 wherein: a terminal region (004) is further arranged, and a fourth type groove (7), a second conductive type third well region (11), a fourth type oxide layer (15) and a fourth type conductive polycrystalline silicon (19) are arranged in the terminal region (004);
the terminal region (004) is arranged at the periphery of the second transition region (003), the fourth groove (7) penetrates through the second conductive type body region (20) from the upper surface of the second conductive type body region (20) to enter the first conductive type epitaxial layer (3) downwards, a fourth oxide layer (15) is arranged on the side wall and the bottom surface of the fourth groove (7), a fourth conductive polycrystalline silicon (19) is arranged in the fourth oxide layer (15), the fourth conductive polycrystalline silicon (19) is insulated from the first conductive type epitaxial layer (3) and the second conductive type body region (20) through the fourth oxide layer (15), and an insulating medium layer (22) is arranged on the fourth oxide layer (15), the fourth conductive polycrystalline silicon (19) and the second conductive type body region (20);
a first conductive type well region (8) is arranged below the first type trench (4), a second conductive type first well region (9) is arranged below the second type trench (5), a second conductive type second well region (10) is arranged below the third type trench (6), and a second conductive type third well region (11) is arranged below the fourth type trench (7).
6. The trench power semiconductor device of claim 1 wherein: the thickness of the second type oxide layer (13) and the thickness of the third type oxide layer (14) are both 1000A-10000A.
7. The trench power semiconductor device according to any of claims 2 to 5, characterized by: the thicknesses of the second type oxide layer (13), the third type oxide layer (14) and the fourth type oxide layer (15) are both 1000A-10000A.
8. The trench power semiconductor device of claim 5 wherein: the fourth type of conductive polysilicon (19) in the terminal area (004) is arranged in a floating mode.
9. A method of manufacturing a trench power semiconductor device as claimed in claim 1, comprising the steps of:
the method comprises the following steps: providing a first conductive type substrate (2), forming a first conductive type first epitaxial layer (3) on the first conductive type substrate (2), then injecting second conductive type impurities, and forming a second conductive type body region (20) after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove (4), a second type groove (5) and a third type groove (6);
step three: depositing an isolation oxidation barrier layer (25), and selectively etching and removing the isolation oxidation barrier layer (25) in the first transition region (002) and the second transition region (003) by using a second photoetching plate;
step four: thermally growing an oxide layer on the chip, and forming a second oxide layer (13) in the first transition region (002); forming a third type oxide layer (14) in the second transition region (003);
step five: removing the isolation oxidation barrier layer (25) in the active region (001);
step six: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer (12) in the active region (001);
step seven: depositing conductive polysilicon, etching the conductive polysilicon, and only reserving the conductive polysilicon in the first type groove (4), the second type groove (5) and the third type groove (6) to form first type conductive polysilicon (16), second type conductive polysilicon (17) and third type conductive polysilicon (18);
step eight: generally implanting first conductive type impurities, and forming a first conductive type source region (21) after activation;
step nine: depositing an insulating dielectric layer (22);
step ten: selectively etching the insulating medium layer (22) and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal (23); and depositing a passivation layer on the back surface of the first conductive type substrate (2), then selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal (1).
10. A method of manufacturing a trench power semiconductor device as claimed in claim 2, comprising the steps of:
the method comprises the following steps: providing a first conductive type substrate (2), forming a first conductive type first epitaxial layer (3) on the first conductive type substrate (2), then injecting second conductive type impurities, and forming a second conductive type body region (20) after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove (4), a second type groove (5), a third type groove (6) and a fourth type groove (7);
step three: depositing an isolation oxidation barrier layer (25), and selectively etching and removing the isolation oxidation barrier layer (25) in the first transition region (002), the second transition region (003) and the terminal region (004) by using a second photoetching plate;
step four: thermally growing an oxide layer on the chip, and forming a second oxide layer (13) in the first transition region (002); forming a third type oxide layer (14) in the second transition region (003); forming a fourth type oxide layer (15) in the termination region (004);
step five: removing the isolation oxidation barrier layer (25) in the active region (001);
step six: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer (12) in the active region (001);
step seven: depositing conductive polysilicon, and then etching the conductive polysilicon, only reserving the conductive polysilicon in the first type groove (4), the second type groove (5), the third type groove (6) and the fourth type groove (7), and forming first type conductive polysilicon (16), second type conductive polysilicon (17), third type conductive polysilicon (18) and fourth type conductive polysilicon (19);
step eight: generally implanting first conductive type impurities, and forming a first conductive type source region (21) after activation;
step nine: depositing an insulating dielectric layer (22);
step ten: selectively etching the insulating medium layer (22) and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step eleven: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal (23) and a metal bridge (24); and depositing a passivation layer on the back surface of the first conductive type substrate (2), then selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal (1).
11. A method of manufacturing a trench power semiconductor device as claimed in claim 3, comprising the steps of:
the method comprises the following steps: providing a first conductive type substrate (2), forming a first conductive type first epitaxial layer (3) on the first conductive type substrate (2), then injecting second conductive type impurities, and forming a second conductive type body region (20) after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove (4), a second type groove (5), a third type groove (6) and a fourth type groove (7);
step three: depositing an isolation oxidation barrier layer (25), and selectively etching and removing the isolation oxidation barrier layer (25) in the first transition region (002), the second transition region (003) and the terminal region (004) by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region (9), a second conductive type second well region (10) and a second conductive type third well region (11);
step five: thermally growing an oxide layer on the chip, and forming a second oxide layer (13) in the first transition region (002); forming a third type oxide layer (14) in the second transition region (003); forming a fourth type oxide layer (15) in the termination region (004);
step six: removing the isolation oxidation barrier layer (25) in the active region (001);
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer (12) in the active region (001);
step eight: depositing conductive polysilicon, and then etching the conductive polysilicon, only reserving the conductive polysilicon in the first type groove (4), the second type groove (5), the third type groove (6) and the fourth type groove (7), and forming first type conductive polysilicon (16), second type conductive polysilicon (17), third type conductive polysilicon (18) and fourth type conductive polysilicon (19);
step nine: generally implanting first conductive type impurities, and forming a first conductive type source region (21) after activation;
step ten: depositing an insulating dielectric layer (22);
step eleven: selectively etching the insulating medium layer (22) and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal (23) and a metal bridge (24); and depositing a passivation layer on the back surface of the first conductive type substrate (2), then selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal (1).
12. A method of manufacturing a trench power semiconductor device as claimed in claim 4, comprising the steps of:
the method comprises the following steps: providing a first conductive type substrate (2), forming a first conductive type first epitaxial layer (3) on the first conductive type substrate (2), then injecting second conductive type impurities, and forming a second conductive type body region (20) after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove (4), a second type groove (5), a third type groove (6) and a fourth type groove (7);
step three: depositing an isolation oxidation barrier layer (25), and selectively etching and removing the isolation oxidation barrier layer (25) in the first transition region (002), the second transition region (003) and the terminal region (004) by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region (9), a second conductive type second well region (10) and a second conductive type third well region (11);
step five: thermally growing an oxide layer on the chip, and forming a second oxide layer (13) in the first transition region (002); forming a third type oxide layer (14) in the second transition region (003); forming a fourth type oxide layer (15) in the termination region (004);
step six: removing the isolation oxidation barrier layer (25) in the active region (001), generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region (8);
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer (12) in the active region (001);
step eight: depositing conductive polysilicon, and then etching the conductive polysilicon, only reserving the conductive polysilicon in the first type groove (4), the second type groove (5), the third type groove (6) and the fourth type groove (7), and forming first type conductive polysilicon (16), second type conductive polysilicon (17), third type conductive polysilicon (18) and fourth type conductive polysilicon (19);
step nine: generally implanting first conductive type impurities, and forming a first conductive type source region (21) after activation;
step ten: depositing an insulating dielectric layer (22);
step eleven: selectively etching the insulating medium layer (22) and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: and forming a metal layer on the surface of the chip, selectively etching the metal layer by using a fourth photoetching plate to form a source metal (23) and a metal bridge (24), depositing a passivation layer, selectively etching the passivation layer by using a fifth photoetching plate, and finally forming a drain metal (1).
13. A method of manufacturing a trench power semiconductor device as claimed in claim 5, comprising the steps of:
the method comprises the following steps: providing a first conductive type substrate (2), forming a first conductive type first epitaxial layer (3) on the first conductive type substrate (2), then injecting second conductive type impurities, and forming a second conductive type body region (20) after annealing;
step two: selectively etching grooves by using a first photoetching plate to form a first type groove (4), a second type groove (5), a third type groove (6) and a fourth type groove (7);
step three: depositing an isolation oxidation barrier layer (25), and selectively etching and removing the isolation oxidation barrier layer (25) in the first transition region (002), the second transition region (003) and the terminal region (004) by using a second photoetching plate;
step four: generally injecting second conductive type impurities into the upper surface of the chip, and annealing to form a second conductive type first well region (9), a second conductive type second well region (10) and a second conductive type third well region (11);
step five: thermally growing an oxide layer on the chip, and forming a second oxide layer (13) in the first transition region (002); forming a third type oxide layer (14) in the second transition region (003); forming a fourth type oxide layer (15) in the termination region (004);
step six: removing the isolation oxidation barrier layer (25) in the active region (001), generally injecting first conductive type impurities into the upper surface of the chip, and annealing to form a first conductive type well region (8);
step seven: carrying out thermal growth on an oxide layer on the chip, and forming a first type oxide layer (12) in the active region (001);
step eight: depositing conductive polysilicon, and then etching the conductive polysilicon, only reserving the conductive polysilicon in the first type groove (4), the second type groove (5), the third type groove (6) and the fourth type groove (7), and forming first type conductive polysilicon (16), second type conductive polysilicon (17), third type conductive polysilicon (18) and fourth type conductive polysilicon (19);
step nine: generally implanting first conductive type impurities, and forming a first conductive type source region (21) after activation;
step ten: depositing an insulating dielectric layer (22);
step eleven: selectively etching the insulating medium layer (22) and the semiconductor epitaxial layer by using a third photoetching plate to form a through hole;
step twelve: forming a metal layer on the surface of the chip, and selectively etching the metal layer by using a fourth photoetching plate to form a source metal (23); and depositing a passivation layer on the back surface of the first conductive type substrate (2), then selectively etching the passivation layer by using a fifth photoetching plate, and finally forming the drain metal (1).
CN202011171440.5A 2020-10-28 2020-10-28 Trench power semiconductor device and manufacturing method Pending CN112216743A (en)

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CN113948577A (en) * 2021-10-15 2022-01-18 捷捷微电(无锡)科技有限公司 High-reliability MOSFET integrated circuit chip and preparation method thereof
CN115274840A (en) * 2022-09-29 2022-11-01 深圳芯能半导体技术有限公司 RC-IGBT device structure and preparation method thereof
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113948577A (en) * 2021-10-15 2022-01-18 捷捷微电(无锡)科技有限公司 High-reliability MOSFET integrated circuit chip and preparation method thereof
CN115274840A (en) * 2022-09-29 2022-11-01 深圳芯能半导体技术有限公司 RC-IGBT device structure and preparation method thereof
CN116525448A (en) * 2023-05-22 2023-08-01 上海晶岳电子有限公司 Voltage-adjustable semiconductor device and manufacturing method thereof
CN116525448B (en) * 2023-05-22 2024-08-06 上海晶岳电子有限公司 Voltage-adjustable semiconductor device and manufacturing method thereof

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