CN106920752A - Low pressure super node MOSFET grid source aoxidizes Rotating fields and manufacture method - Google Patents
Low pressure super node MOSFET grid source aoxidizes Rotating fields and manufacture method Download PDFInfo
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- CN106920752A CN106920752A CN201710153059.8A CN201710153059A CN106920752A CN 106920752 A CN106920752 A CN 106920752A CN 201710153059 A CN201710153059 A CN 201710153059A CN 106920752 A CN106920752 A CN 106920752A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 230000002159 abnormal effect Effects 0.000 claims abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 238000001312 dry etching Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to the oxidation of low pressure super node MOSFET grid source Rotating fields and manufacture method, oxidated layer thickness between gate-source is adjusted by nitride process twice, it is to avoid root oxide layer is uneven between grid source, causes component failure or abnormal parameters.The present invention fills polysilicon by deep trouth, two mutual charge balances of deep trouth complete superjunction function, shallow slot is formed by the way of wet etching above deep trouth again, low pressure super node MOSFET is made in shallow slot, low pressure superjunction devices is collectively formed, can be realized with traditional semiconductor fabrication process, improve quality of oxide layer between the first polysilicon and grid polycrystalline silicon in the case of technology difficulty is not increased, optimize the parameter of product, improve yield rate and reliability, be finally reached reduction chip cost.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of low pressure super node MOSFET grid source oxide layer
Structure and manufacture method.
Background technology
For traditional power MOSFET device, device on-resistance（Ron）There is certain folding with source and drain breakdown voltage
Middle relation（Ron∝BV2.5）, the development of power MOSFET device is limited for a long time.Low pressure super node MOSFET utilizes electric charge
Equilibrium principle so that even if N-type drift region can also realize device breakdown voltage higher in the case of higher-doped concentration, from
And low conducting resistance is obtained, break the silicon limit of conventional power MOSFET.Such as Figure 21, the highly doped polycrystalline of standard process flow
Silicon forms that quality of oxide layer is not high and the oxidated layer thickness between grid source polarity is uneven, and device parameters and reliability are brought
Greater risk.
The content of the invention
It is an object of the invention to provide a kind of oxidation of low pressure super node MOSFET grid source Rotating fields and manufacture method, do not increasing
Generate that consistency of thickness is good and the adjustable grid source electrode oxide layer of thickness on the premise of technology difficulty.
The technical solution adopted in the present invention is：
Low pressure super node MOSFET grid source aoxidizes the manufacture method of Rotating fields, it is characterised in that：
Oxidated layer thickness between gate-source is adjusted by nitride process twice, it is to avoid root oxide layer is uneven between grid source
It is even, cause component failure or abnormal parameters.
Comprise the following steps：
Step one：The n+ substrates of n type heavy doping are provided, and N-shaped epitaxial layer is formed on n+ substrates；
Step 2：In N-shaped extension generate ground floor silicon nitride and by photoetching, dry etching formed active area deep trench and
The deep trench of termination environment, termination environment deep trench surrounds active area deep trench；
Step 3：Using wet thermal oxidation process in the zanjon trench bottom and sidewall growth field oxide；
Step 4：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 5：Polysilicon is carried out by dry corrosion process and returns quarter, be etched to polysilicon and epitaxial layer upper surface flush；
Step 6：Using dry method plus wet processing removal surface field oxide, while field oxide to deep trench inner recess not
1000A can be more than；
Step 7：By photoetching, etching polysilicon and wet corrosion technique to the first polysilicon in active area deep trench and field
Oxide layer successively carries out back carving, and active area deep trench top is obtained a shallow trench, the first polycrystalline in the deep trench of termination environment
Silicon and field oxide do not return quarter under the protection of photoresist；
Step 8：Deposit second layer silicon nitride, and horizontal plane silicon nitride and further dry etching first are fallen by dry etching
Layer polysilicon；
Step 9：The gate oxide of ground floor polysilicon surface is grown by dry method thermal oxidation technology, is formed in uniform thickness
The grid oxic horizon of the polysilicon surface of MOSFET element first；
Step 10：Second polycrystalline silicon deposit, and second polysilicon dry back is carved, form shallow slot MOSFET element grid；
Step 11：P-BODY injects, and forms p-well；
Step 12：By injection, making devices active area；
Step 13：Dielectric layer deposited, contact hole etching；
Step 14：Contact hole etching injects to form Ohmic contact, is finally completed structure.
Ground floor silicon nitride etch and deep trouth align, and second layer silicon nitride is concordant with ground floor silicon nitride superposition side, the
Two layers of silicon nitride and ground floor silicon nitride superposition thickness can effectively protect epitaxial planar further to be etched in ground floor polysilicon
Process is not etched together.
As mentioned low pressure super node MOSFET grid source oxidation Rotating fields manufacture method obtained in low pressure super node MOSFET grid
Source aoxidizes Rotating fields.
The present invention has advantages below：
The present invention can form oxide layer between high-quality gate-source after nitride process twice is improved, and can use tradition
Semiconductor fabrication process realize, improve oxygen between the first polysilicon and grid polycrystalline silicon in the case of technology difficulty is not increased
Change layer quality, optimize the parameter of product, improve yield rate and reliability, be finally reached reduction chip cost.
Brief description of the drawings
Fig. 1 is the schematic diagram of step one of the present invention；
Fig. 2 is the schematic diagram of step 2 of the present invention；
Fig. 3 is the schematic diagram of step 3 of the present invention；
Fig. 4 is the schematic diagram of step 4 of the present invention；
Fig. 5 is the schematic diagram of step 5 of the present invention；
Fig. 6 is the schematic diagram of step 6 of the present invention；
Fig. 7 is the schematic diagram of step 7 of the present invention；
Fig. 8 is the schematic diagram of step 8 of the present invention；
Fig. 9 is the schematic diagram of step 9 of the present invention；
Figure 10 is the schematic diagram of step 10 of the present invention；
Figure 11 is the schematic diagram of step 11 of the present invention；
Figure 12 is the schematic diagram of step 12 of the present invention；
Figure 13 is the schematic diagram of step 13 of the present invention；
Figure 14 is the schematic diagram of step 14 of the present invention；
Figure 15 is the schematic diagram of step 15 of the present invention；
Figure 16 is the schematic diagram of step 10 of the present invention six；
Figure 17 is the schematic diagram of step 10 of the present invention seven；
Figure 18 is the schematic diagram of step 10 of the present invention eight；
Figure 19 is the schematic diagram of step 10 of the present invention nine；
Figure 20 is the schematic diagram of step 2 of the present invention ten；
Figure 21 is the sectional view of existing process resulting devices.
Figure 22 is the sectional view of device of the present invention.
Specific embodiment
With reference to specific embodiment, the present invention will be described in detail.
Low pressure super node MOSFET grid source of the present invention aoxidizes the manufacture method of Rotating fields, and polycrystalline is filled by deep trouth
Silicon, two mutual charge balances of deep trouth complete superjunction function, then shallow slot is formed by the way of wet etching above deep trouth,
Low pressure super node MOSFET is made in shallow slot, low pressure superjunction devices is collectively formed.Nitride process between gate-source aoxidizing twice
Thickness degree is adjusted, it is to avoid root oxide layer is uneven between old-fashioned scheme grid source in Figure 21, causes component failure or parameter different
Often.Specifically include following steps：
Step one：The n+ substrates of n type heavy doping are provided, and N-shaped epitaxial layer is formed on n+ substrates；
Step 2：In N-shaped extension generate ground floor silicon nitride and by photoetching, dry etching formed active area deep trench and
The deep trench of termination environment, termination environment deep trench surrounds active area deep trench；
Step 3：Using wet thermal oxidation process in the zanjon trench bottom and sidewall growth field oxide；
Step 4：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 5：Polysilicon is carried out by dry corrosion process and returns quarter, be etched to polysilicon and epitaxial layer upper surface flush；
Step 6：Using dry method plus wet processing removal surface field oxide, while field oxide to deep trench inner recess not
1000A can be more than；
Step 7：By photoetching, etching polysilicon and wet corrosion technique to the first polysilicon in active area deep trench and field
Oxide layer successively carries out back carving, and active area deep trench top is obtained a shallow trench, the first polycrystalline in the deep trench of termination environment
Silicon and field oxide do not return quarter under the protection of photoresist；
Step 8：Deposit second layer silicon nitride, and horizontal plane silicon nitride and further dry etching first are fallen by dry etching
Layer polysilicon；
Step 9：The gate oxide of ground floor polysilicon surface is grown by dry method thermal oxidation technology, is formed in uniform thickness
The grid oxic horizon of the polysilicon surface of MOSFET element first；
Step 10：Second polycrystalline silicon deposit, and second polysilicon dry back is carved, form shallow slot MOSFET element grid；
Step 11：P-BODY injects, and forms p-well；
Step 12：By injection, making devices active area；
Step 13：Dielectric layer deposited, contact hole etching；
Step 14：Contact hole etching injects to form Ohmic contact, is finally completed structure.
Ground floor silicon nitride etch and deep trouth align, and second layer silicon nitride is concordant with ground floor silicon nitride superposition side, the
Two layers of silicon nitride and ground floor silicon nitride superposition thickness can effectively protect epitaxial planar further to be etched in ground floor polysilicon
Process is not etched together.
Illustrate by the following examples：
Step one：The n+ substrates of n type heavy doping are provided, and N-shaped epitaxial layer is formed on n+ substrates, such as Fig. 1 shows；
Step 2：Ground floor silicon nitride is deposited in N-shaped extension, the bar shaped of multiple array types is formed by photoetching, dry etching
Deep trouth, such as Fig. 2 show；
Step 3：Using thermal oxidation technology in the deep trouth bottom and sidewall growth field oxide, such as Fig. 3 shows；
Step 4：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out, such as Fig. 4 shows；
Step 5：Polysilicon is carried out using photoetching process and polysilicon dry etching and return quarter, remove the unwanted polysilicon in surface
Structure such as Fig. 5 shows；
Step 6：The wet etching of field oxide, obtains a shallow slot above each deep trouth, and such as Fig. 6 shows；
Step 7：Deposit second layer silicon nitride, as shown in Figure 7；
Step 8：Silicon nitride plane dry etching, forms the protection of side wall, as shown in Figure 8；
Step 9：The further dry etching of ground floor polysilicon is extremely less than oxidation layer height, as shown in Figure 9；
Step 10：Dry method thermal oxide ground floor polysilicon surface, forms oxide layer in uniform thickness, i.e. oxidation between grid source
Layer, as shown in Figure 10；
Step 11：Wet etching removes all silicon nitride layers, as shown in figure 11；
Step 12：Aoxidized by sacrificing oxidation, grid oxygen, form MOSFET element grid oxygen, such as Figure 12 shows；
Step 13：Second polycrystalline silicon deposit, such as Figure 13 shows；
Step 14：Second polysilicon dry back is carved, and forms shallow slot MOSFET element grid, and such as Figure 14 shows；
Step 15：P-well is injected, as shown in figure 15；
Step 10 six：Source injects, and forms device source electrode, and such as Figure 16 shows；
Step 10 seven：Dielectric deposition, such as Figure 17 show；
Step 10 eight：Separation is done by dielectric layer and epitaxial layer etching process to form contact hole, such as Figure 18；
Step 10 nine：The filling of hole tungsten is completed, and surface metal technique forms device Facad structure, such as Figure 19 shows.
Step 2 ten：Back metal technique is finally completed, device drain terminal is formed, resulting devices structure is completed, such as Figure 20 shows.
Present disclosure is not limited to cited by embodiment, and those of ordinary skill in the art are by reading description of the invention
And any equivalent conversion taken technical solution of the present invention, it is claim of the invention and is covered.
Claims (4)
1. low pressure super node MOSFET grid source aoxidizes the manufacture method of Rotating fields, it is characterised in that：
Oxidated layer thickness between gate-source is adjusted by nitride process twice, it is to avoid root oxide layer is uneven between grid source
It is even, cause component failure or abnormal parameters.
2. low pressure super node MOSFET grid source according to claim 1 aoxidizes the manufacture method of Rotating fields, it is characterised in that：
Comprise the following steps：
Step one：The n+ substrates of n type heavy doping are provided, and N-shaped epitaxial layer is formed on n+ substrates；
Step 2：In N-shaped extension generate ground floor silicon nitride and by photoetching, dry etching formed active area deep trench and
The deep trench of termination environment, termination environment deep trench surrounds active area deep trench；
Step 3：Using wet thermal oxidation process in the zanjon trench bottom and sidewall growth field oxide；
Step 4：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 5：Polysilicon is carried out by dry corrosion process and returns quarter, be etched to polysilicon and epitaxial layer upper surface flush；
Step 6：Using dry method plus wet processing removal surface field oxide, while field oxide to deep trench inner recess not
1000A can be more than；
Step 7：By photoetching, etching polysilicon and wet corrosion technique to the first polysilicon in active area deep trench and field
Oxide layer successively carries out back carving, and active area deep trench top is obtained a shallow trench, the first polycrystalline in the deep trench of termination environment
Silicon and field oxide do not return quarter under the protection of photoresist；
Step 8：Deposit second layer silicon nitride, and horizontal plane silicon nitride and further dry etching first are fallen by dry etching
Layer polysilicon；
Step 9：The gate oxide of ground floor polysilicon surface is grown by dry method thermal oxidation technology, is formed in uniform thickness
The grid oxic horizon of the polysilicon surface of MOSFET element first；
Step 10：Second polycrystalline silicon deposit, and second polysilicon dry back is carved, form shallow slot MOSFET element grid；
Step 11：P-BODY injects, and forms p-well；
Step 12：By injection, making devices active area；
Step 13：Dielectric layer deposited, contact hole etching；
Step 14：Contact hole etching injects to form Ohmic contact, is finally completed structure.
3. low pressure super node MOSFET grid source according to claim 2 aoxidizes the manufacture method of Rotating fields, it is characterised in that：
Ground floor silicon nitride etch and deep trouth align, and second layer silicon nitride is concordant with ground floor silicon nitride superposition side, the second layer
Silicon nitride and ground floor silicon nitride superposition thickness can effectively protect epitaxial planar in the further etching process of ground floor polysilicon
Do not etched together.
4. low pressure superjunction obtained in the manufacture method of low pressure super node MOSFET grid source as claimed in claim 3 oxidation Rotating fields
MOSFET grid source aoxidizes Rotating fields.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108091573A (en) * | 2017-12-20 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Shield grid groove MOSFET ESD structures and its manufacturing method |
| CN111508830A (en) * | 2020-04-23 | 2020-08-07 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of low-voltage high-density trench DMOS device |
| CN112382572A (en) * | 2021-01-15 | 2021-02-19 | 龙腾半导体股份有限公司 | SGT structure of ONO shielded gate and manufacturing method thereof |
| CN113299599A (en) * | 2021-04-07 | 2021-08-24 | 上海芯导电子科技股份有限公司 | Self-aligned field effect transistor and preparation method thereof |
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| US20140084363A1 (en) * | 2012-09-26 | 2014-03-27 | Jeffrey Pearse | Mos transistor structure |
| CN106206322A (en) * | 2016-08-30 | 2016-12-07 | 西安龙腾新能源科技发展有限公司 | The manufacture method of autoregistration low pressure superjunction MOFET |
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| CN108091573A (en) * | 2017-12-20 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Shield grid groove MOSFET ESD structures and its manufacturing method |
| CN108091573B (en) * | 2017-12-20 | 2020-12-18 | 西安龙腾新能源科技发展有限公司 | Manufacturing method of shielded gate trench MOSFET ESD structure |
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| CN112382572A (en) * | 2021-01-15 | 2021-02-19 | 龙腾半导体股份有限公司 | SGT structure of ONO shielded gate and manufacturing method thereof |
| CN112382572B (en) * | 2021-01-15 | 2021-11-02 | 龙腾半导体股份有限公司 | SGT structure of ONO shielded gate and manufacturing method thereof |
| CN113299599A (en) * | 2021-04-07 | 2021-08-24 | 上海芯导电子科技股份有限公司 | Self-aligned field effect transistor and preparation method thereof |
| CN113299599B (en) * | 2021-04-07 | 2024-07-05 | 上海芯导电子科技股份有限公司 | Self-aligned field effect transistor and preparation method thereof |
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Application publication date: 20170704 |