CN111755525A - Trench MOS power device and preparation method - Google Patents
Trench MOS power device and preparation method Download PDFInfo
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- CN111755525A CN111755525A CN202010727312.8A CN202010727312A CN111755525A CN 111755525 A CN111755525 A CN 111755525A CN 202010727312 A CN202010727312 A CN 202010727312A CN 111755525 A CN111755525 A CN 111755525A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 23
- 239000007924 injection Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
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- 150000004706 metal oxides Chemical class 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention discloses a Trench MOS power device and a preparation method thereof, and relates to the technical field of semiconductor power devices. The breakdown voltage can be effectively guaranteed while the on-resistance of the device is reduced. The method comprises the following steps: the epitaxial layer, the grid groove and the injection buried layer; the grid groove is arranged on the epitaxial layer; the injection buried layer is located under the grid groove and is in contact with the bottom and the side wall of the grid groove, and the injection buried layer comprises an N-type buried layer and a P-type buried layer.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a Trench MOS power device and a preparation method thereof.
Background
Trench MOS (Trench Metal Oxide Semiconductor field effect transistor) is developed on the basis of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor field effect transistor).
In the prior art, in order to reduce the power loss of a chip device, the on-resistance of the device is reduced, and meanwhile, in order to improve the utilization rate of the power device, the cell density of other power device products on the market is higher and higher at present.
Disclosure of Invention
The embodiment of the invention provides a Trench MOS power device and a preparation method thereof, which are used for reducing the on-resistance of the device and effectively guaranteeing the breakdown voltage.
The embodiment of the invention provides a Trench MOS power device, which comprises: the epitaxial layer, the grid groove and the injection buried layer;
the grid groove is arranged on the epitaxial layer;
the injection buried layer is located under the grid groove and is in contact with the bottom and the side wall of the grid groove, and the injection buried layer comprises an N-type buried layer and a P-type buried layer.
Preferably, the implanted buried layer comprises an N-type buried layer and a P-type buried layer from bottom to top, the N-type buried layer wraps the P-type buried layer, and the upper surface of the N-type buried layer is not in contact with the lower surface of the P-type well region in the epitaxial layer.
Preferably, the implanted buried layer comprises a P-type buried layer and an N-type buried layer from bottom to top, the N-type buried layer is wrapped by the P-type buried layer, and the upper surface of the P-type buried layer is not in contact with the lower surface of the N-type well region in the epitaxial layer.
Preferably, the thickness of the gate oxide layer on the gate trench is 265A to 500A.
The embodiment of the invention also provides a preparation method of the Trench MOS power device, which comprises the following steps:
depositing a hard mask plate and photoresist on the upper surface of the epitaxial layer, and forming a gate trench in the epitaxial layer by an etching method;
removing the photoresist on the upper layer of the hard mask plate, and generating a silicon dioxide layer in the grid groove and on the upper surface of the hard mask plate in a chemical vapor deposition mode;
forming an implanted buried layer on the epitaxial layer at the bottom of the grid groove in an ion implantation and high-temperature propulsion mode;
removing the silicon dioxide in the grid groove, the hard mask plate on the upper surface of the epitaxial layer and the silicon dioxide, and growing a grid oxide layer on the upper surface of the epitaxial layer and in the grid groove;
and depositing a polysilicon layer in the grid groove, forming a well region layer and a source electrode layer between the grid grooves in an ion injection mode, forming a contact hole metal layer on the well region layer, and forming a source electrode region metal layer through the contact hole metal layer.
Preferably, the thickness of the hard mask plate is 2000A, and the thickness of the silicon dioxide layer is 200A-400A.
Preferably, the forming of the implanted buried layer on the epitaxial layer at the bottom of the gate trench by ion implantation and high temperature drive includes:
forming a first injection buried layer at the bottom of the grid groove and around the side wall of the grid groove in a first ion injection and high-temperature propulsion mode;
forming a second high-temperature implanted buried layer in the first implanted buried layer by a second ion implantation and high-temperature propulsion mode; wherein the high-temperature propulsion temperature is 950 ℃, and the high-temperature propulsion time is 30 min.
Preferably, when the first implanted buried layer is a P-type buried layer, the second implanted buried layer is an N-type buried layer; or
And when the first implanted buried layer is an N-type buried layer, the second implanted buried layer is a P-type buried layer.
Preferably, the thickness of the gate oxide layer is 265A to 500A.
Preferably, the forming a well region layer and a source region layer between the gate trenches by ion implantation, forming a contact hole metal layer on the well region layer, and forming a source region metal layer through the contact hole metal layer specifically includes:
forming the well region layer between the grid grooves through third ion implantation, and forming a source electrode layer on the well region layer through fourth ion implantation;
forming a silicon dioxide layer and a dielectric layer on the grid groove through a deposition process, forming a contact hole metal layer on the silicon dioxide layer and the dielectric layer through a photoetching process, forming a metal layer on the dielectric layer, and enabling the metal layer to be in contact with the well region layer through the contact hole metal layer to form a source region metal layer.
The embodiment of the invention provides a Trench MOS power device and a preparation method thereof, wherein the power device comprises an epitaxial layer, a grid groove and an injection buried layer; the grid groove is arranged on the epitaxial layer; the injection buried layer is located under the grid groove and is in contact with the bottom and the side wall of the grid groove, and the injection buried layer comprises an N-type buried layer and a P-type buried layer. When traditional trench MOSFET switches on, can form the electric field at the ditch groove bottom electric field line is intensive and concentrate and lead to breakdown voltage lower easily, and the concentration and the thickness of epitaxial layer are the root cause that influences device on resistance and breakdown voltage, and the concentration and the thickness of epitaxial layer appear undulantly, can lead to trench MOSFET product parameter unstable, neglects high neglecting low. According to the Trench MOS power device provided by the embodiment of the invention, the ion implantation is carried out at the bottom of the Trench, namely in the epitaxial layer to form the implanted buried layer, so that the breakdown voltage and the on-resistance can be adjusted, and the product parameters are in a relatively stable state; furthermore, the implanted buried layer comprises an N-type buried layer and a P-type buried layer, and the buried layer formed for the first time has the same ions as the epitaxial layer, so that the ion concentration of the epitaxial layer can be improved, the drift resistance of the epitaxial layer is reduced, and the integral on-resistance of the device is reduced; moreover, the ions injected for the second time and the epitaxial layer have opposite ions, so that the phenomenon of dense electric field lines at the bottom of the groove can be reduced, and the breakdown voltage is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a Trench MOS power device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a preparation process of a Trench MOS power device according to an embodiment of the present invention;
fig. 3A is a schematic diagram illustrating a gate trench preparation according to an embodiment of the present invention;
FIG. 3B is a schematic diagram illustrating the preparation of a sacrificial oxide layer according to an embodiment of the present invention;
fig. 3C is a schematic diagram illustrating the fabrication of an implanted buried layer according to an embodiment of the present invention;
FIG. 3D is a schematic diagram illustrating the fabrication of a gate oxide layer according to an embodiment of the present invention;
the structure comprises a substrate layer-101, an epitaxial layer-102, a mask plate-103, photoresist-104, a gate trench-105, a sacrificial oxide layer-106, a first injection buried layer-107-1, a second injection buried layer-107-2, a gate oxide layer-108, polysilicon-109, a well region layer-110, a source region layer-111 and a metal layer contact hole-112.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 schematically illustrates a structural diagram of a Trench MOS power device according to an embodiment of the present invention, as shown in fig. 1, the Trench MOS power device mainly includes an epitaxial layer 102, a gate Trench 105, and an implanted buried layer.
As shown in fig. 1, the gate Trench 105 and the implantation buried layer of the Trench MOS power device according to the embodiment of the present invention are both disposed in the epitaxial layer 102, and the implantation buried layer is located right below the gate Trench 105 and around the sidewall of the gate Trench 105.
Specifically, as shown in fig. 1, the implanted buried layer provided by the embodiment of the present invention includes an N-type buried layer and a P-type buried layer. One situation is: when the implanted buried layer comprises an N-type buried layer and a P-type buried layer from bottom to top and wraps the P-type buried layer, the upper surface of the N-type buried layer is not in contact with the lower surface of the P-type well region in the epitaxial layer 102; the other situation is as follows: when the implanted buried layer includes a P-type buried layer and an N-type buried layer from bottom to top and the N-type buried layer is wrapped by the P-type buried layer, the upper surface of the P-type buried layer is not in contact with the lower surface of the N-type well region in the epitaxial layer 102.
As shown in fig. 1, the gate oxide layer 108 is located in the gate trench 105 and on the upper surface of the epitaxial layer 102, wherein the thickness of the gate oxide layer 108 is 265A-500A.
Further, a well region layer 110 is disposed in the epitaxial layer 102, and the well region layer 110 is located at two sides of the gate trench 105, it should be noted that the lower surface of the source region on the upper surface of the well region layer 110 coincides, and the upper surface of the source region coincides with the upper surface of the epitaxial layer 102. It should be noted that, in practical applications, when the well region layer 110 is a P-type well region layer 110, the source region is an N-type source region, and accordingly, the implanted buried layer includes an N-type buried layer and a P-type buried layer from bottom to top; when the well region layer 110 is an N-type well region layer 110, the source region is a P-type source region, and accordingly, the implanted buried layer includes a P-type buried layer and an N-type buried layer from bottom to top.
As shown in fig. 1, a gate oxide layer 108 and a polysilicon 109 layer are sequentially deposited in the gate trench 105 from outside to inside, an upper surface of the polysilicon 109 layer is in contact with a silicon dioxide layer, and a dielectric layer is disposed on the upper surface of the silicon dioxide layer.
After the Trench MOS power device is vertically placed, the source metal layer is in contact with the device through the source region metal layer contact hole 112, and specifically, the source region metal layer contact hole 112 is provided in the well region layer 110 between the gate trenches 105, through which the source region metal layer contact hole 112 may be in contact with the source metal layer.
In summary, the embodiment of the present invention provides a Trench MOS power device and a manufacturing method thereof, where the power device includes an epitaxial layer, a gate Trench and an implanted buried layer; the grid groove is arranged on the epitaxial layer; the injection buried layer is located under the grid groove and is in contact with the bottom and the side wall of the grid groove, and the injection buried layer comprises an N-type buried layer and a P-type buried layer. When traditional trench MOSFET switches on, can form the electric field at the ditch groove bottom electric field line is intensive and concentrate and lead to breakdown voltage lower easily, and the concentration and the thickness of epitaxial layer are the root cause that influences device on resistance and breakdown voltage, and the concentration and the thickness of epitaxial layer appear undulantly, can lead to trench MOSFET product parameter unstable, neglects high neglecting low. According to the Trench MOS power device provided by the embodiment of the invention, the ion implantation is carried out at the bottom of the Trench, namely in the epitaxial layer to form the implanted buried layer, so that the breakdown voltage and the on-resistance can be adjusted, and the product parameters are in a relatively stable state; furthermore, the implanted buried layer comprises an N-type buried layer and a P-type buried layer, and the buried layer formed for the first time has the same ions as the epitaxial layer, so that the ion concentration of the epitaxial layer can be improved, the drift resistance of the epitaxial layer is reduced, and the integral on-resistance of the device is reduced; moreover, the ions injected for the second time and the epitaxial layer have opposite ions, so that the phenomenon of dense electric field lines at the bottom of the groove can be reduced, and the breakdown voltage is improved.
In order to more clearly introduce the Trench MOS power device provided in the embodiment of the present invention, a method for manufacturing the Trench MOS power device is described below.
Fig. 2 is a schematic diagram of a preparation process of a Trench MOS power device according to an embodiment of the present invention;
fig. 3A is a schematic diagram illustrating a gate trench preparation according to an embodiment of the present invention; FIG. 3B is a schematic diagram illustrating the preparation of a sacrificial oxide layer according to an embodiment of the present invention; fig. 3C is a schematic diagram illustrating the fabrication of an implanted buried layer according to an embodiment of the present invention; fig. 3D is a schematic diagram illustrating a gate oxide layer according to an embodiment of the invention.
The following method for manufacturing a Trench MOS power device is described in detail with reference to the schematic flow diagram of the manufacturing method provided in fig. 2 and the schematic manufacturing diagrams provided in fig. 3A to 3D, and specifically, as shown in fig. 2, the method mainly includes the following steps:
and 25, depositing a polysilicon layer in the grid groove, forming a well region layer and a source electrode layer between the grid grooves in an ion injection mode, forming a contact hole metal layer on the well region layer, and forming a source electrode region metal layer through the contact hole metal layer.
In step 21, as shown in fig. 3A, a substrate layer 101 is provided, and then an epitaxial layer 102 is grown on the substrate layer 101. A hard mask plate 103 is generated on the surface of the epitaxial layer 102, the mask plate 103 is used as an etching barrier layer of the gate trench 105, further, the position of the gate trench 105 is determined through the photoresist 104 and the mask plate 103 of the photoresist 104, the exposed hard mask plate is etched, the photoresist 104 is removed, the hard mask plate 103 is used as an etching barrier layer, and the gate trench 105 is formed on the epitaxial layer 102.
In step 22, as shown in fig. 3B, the photoresist 104 on the upper surface of the epitaxial layer 102 is removed, including the hard mask 103, and a silicon dioxide layer is formed on the gate trench 105 and the upper surface of the epitaxial layer 102 by chemical vapor deposition, wherein the silicon dioxide layer is used as a barrier layer for the ion implantation at the bottom of the gate trench 105, which is the wafer surface and the sidewall of the gate trench 105. For the traditional Trench MOSFET device, the manufacturing process of the traditional Trench MOSFET device is provided with a layer of photomask for etching the trench, and the embodiment of the invention utilizes the layer of photomask to carry out ion implantation on the bottom of the trench, thereby not increasing the cost of the photomask.
In the embodiment of the present invention, the silicon dioxide layer is also referred to as a sacrificial oxide layer 106, and the thickness of the sacrificial oxide layer 106 is between 200A and 400A.
In step 23, as shown in fig. 3C, impurity ions are first implanted into the epitaxial layer 102 at the bottom of the gate trench 105 by using the silicon dioxide layer and the hard mask 103 as the surface of the epitaxial layer 102 and the barrier layer on the sidewall of the gate trench 105, a doped region is formed in the epitaxial layer 102 at the bottom of the gate trench 105, and the impurity ions are activated by high temperature drive, so that a first implanted buried layer 107-1 is formed in the epitaxial layer 102 at the bottom of the gate trench 105; further, impurity ions are implanted into the first implanted buried layer 107-1 at the bottom of the gate trench 105 by means of a second ion implantation, and the second implanted buried layer 107-2 is formed within the first implanted buried layer 107-1 by activating the impurity ions by high temperature drive. In practical applications, since the ion implantation is performed on the wafer surface, when only the implantation is performed at the bottom of the trench, a barrier layer is required to block the region where the implantation is not needed. In the embodiment of the present invention, the surface of the wafer is provided with a thick hard mask 103, which can block the ion implantation, and furthermore, the sacrificial oxide layer 106 in the gate trench 105 can block the ion implantation on the sidewall of the trench. Since the hard mask 103 and the sacrificial oxide 106 are also process steps of the conventional trench MOSFET process, in the embodiment of the present invention, the hard mask 103 and the sacrificial oxide 106 can be used as barrier layers for implantation during two ion implantations, thereby saving the process cost.
It should be noted that the high temperature propulsion temperature is 950 ℃, and correspondingly, the high temperature propulsion time is 30 min.
In practical application, if the first implanted buried layer 107-1 formed in the epitaxial layer 102 at the bottom of the gate trench 105 by the first ion implantation is a P-type buried layer, the second ion implantation forms an N-type buried layer in the second implanted buried layer 107-2; accordingly, if the first buried implant 107-1 formed in the epitaxial layer 102 at the bottom of the gate trench 105 by the first implantation is an N-type buried layer, the second ion implantation forms a P-type buried layer in the second buried implant 107-2.
In step 24, as shown in fig. 3D, the silicon dioxide layer in the gate trench 105 and the hard mask 103 and the silicon dioxide layer on the upper surface of the epitaxial layer 102 are removed, and a gate oxide layer 108 is formed on the upper surface of the epitaxial layer 102 and in the gate trench 105, wherein the thickness of the gate oxide layer 108 is 265A to 500A.
In step 25, a layer of polysilicon 109 is deposited within gate trench 105, where polysilicon 109 fills gate trench 105 to a level that does not extend above the top surface of gate oxide layer 108 on the surface of epitaxial layer 102. Then, a well region layer 110 is formed in the epitaxial layer 102 on both sides of the gate trench 105 by a third implantation, and a source region is formed in the well region layer 110 on both sides of the gate trench 105 by a fourth implantation.
Further, a silicon dioxide layer and an insulating medium layer are deposited on the upper surface of the epitaxial layer 102, and contact holes are formed in the silicon dioxide layer and the insulating medium layer in an etching and filling mode. Further, a metal layer is sputtered on the upper surface of the insulating dielectric layer, one end of the contact hole is in contact with the metal layer, and the other end of the contact hole is in contact with the well region layer 110, so that a source metal layer is formed. Further, a metal layer is evaporated on the lower surface of the substrate layer 101 to form a drain region metal layer.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A Trench MOS power device, comprising: the epitaxial layer, the grid groove and the injection buried layer;
the grid groove is arranged on the epitaxial layer;
the injection buried layer is located under the grid groove and is in contact with the bottom and the side wall of the grid groove, and the injection buried layer comprises an N-type buried layer and a P-type buried layer.
2. The device of claim 1, wherein the implanted buried layer comprises an N-type buried layer and a P-type buried layer from bottom to top, the N-type buried layer wraps the P-type buried layer, and an upper surface of the N-type buried layer is not in contact with a lower surface of a P-type well region located in the epitaxial layer.
3. The device of claim 1, wherein the implanted buried layer comprises a P-type buried layer and an N-type buried layer from bottom to top, the P-type buried layer wraps the N-type buried layer, and an upper surface of the P-type buried layer is not in contact with a lower surface of an N-type well region located in the epitaxial layer.
4. The device of claim 1, wherein a thickness of the gate oxide layer over the gate trench is 265A to 500A.
5. A preparation method of a Trench MOS power device is characterized by comprising the following steps:
depositing a hard mask plate and photoresist on the upper surface of the epitaxial layer, and forming a gate trench in the epitaxial layer by an etching method;
removing the photoresist on the upper layer of the hard mask plate, and generating a silicon dioxide layer in the grid groove and on the upper surface of the hard mask plate in a chemical vapor deposition mode;
forming an implanted buried layer on the epitaxial layer at the bottom of the grid groove in an ion implantation and high-temperature propulsion mode;
removing the silicon dioxide in the grid groove, the hard mask plate on the upper surface of the epitaxial layer and the silicon dioxide, and growing a grid oxide layer on the upper surface of the epitaxial layer and in the grid groove;
and depositing a polysilicon layer in the grid groove, forming a well region layer and a source electrode layer between the grid grooves in an ion injection mode, forming a contact hole metal layer on the well region layer, and forming a source electrode region metal layer through the contact hole metal layer.
6. The method according to claim 5, wherein the hard mask has a thickness of 2000A, and the silicon dioxide layer has a thickness of 200A-400A.
7. The method according to claim 5, wherein the forming of the buried implant layer on the epitaxial layer at the bottom of the gate trench by ion implantation and high temperature drive comprises:
forming a first injection buried layer at the bottom of the grid groove and around the side wall of the grid groove in a first ion injection and high-temperature propulsion mode;
forming a second high-temperature implanted buried layer in the first implanted buried layer by a second ion implantation and high-temperature propulsion mode; wherein the high-temperature propulsion temperature is 950 ℃, and the high-temperature propulsion time is 30 min.
8. The method according to claim 7, wherein when the first buried implant layer is a P-type buried layer, the second buried implant layer is an N-type buried layer; or
And when the first implanted buried layer is an N-type buried layer, the second implanted buried layer is a P-type buried layer.
9. The method of claim 5, wherein the gate oxide layer has a thickness of 265A to 500A.
10. The method of claim 5, wherein the forming a well region layer and a source region layer between the gate trenches by ion implantation, forming a contact hole metal layer on the well region layer, and forming a source region metal layer through the contact hole metal layer comprises:
forming the well region layer between the grid grooves through third ion implantation, and forming a source electrode layer on the well region layer through fourth ion implantation;
forming a silicon dioxide layer and a dielectric layer on the grid groove through a deposition process, forming a contact hole metal layer on the silicon dioxide layer and the dielectric layer through a photoetching process, forming a metal layer on the dielectric layer, and enabling the metal layer to be in contact with the well region layer through the contact hole metal layer to form a source region metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN112838010A (en) * | 2021-01-11 | 2021-05-25 | 江苏东海半导体科技有限公司 | Preparation method of low-on-resistance groove type power semiconductor device |
| CN113690321A (en) * | 2021-10-25 | 2021-11-23 | 浙江大学杭州国际科创中心 | Silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN115020211A (en) * | 2022-08-08 | 2022-09-06 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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2020
- 2020-07-24 CN CN202010727312.8A patent/CN111755525A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN112838010A (en) * | 2021-01-11 | 2021-05-25 | 江苏东海半导体科技有限公司 | Preparation method of low-on-resistance groove type power semiconductor device |
| CN113690321A (en) * | 2021-10-25 | 2021-11-23 | 浙江大学杭州国际科创中心 | Silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN115020211A (en) * | 2022-08-08 | 2022-09-06 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN115020211B (en) * | 2022-08-08 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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