CN112802753A - Method for manufacturing semiconductor device - Google Patents
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- CN112802753A CN112802753A CN202011643726.9A CN202011643726A CN112802753A CN 112802753 A CN112802753 A CN 112802753A CN 202011643726 A CN202011643726 A CN 202011643726A CN 112802753 A CN112802753 A CN 112802753A
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000005468 ion implantation Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 28
- 210000000746 body region Anatomy 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, wherein a first conduction type epitaxial layer is formed on the substrate, a groove is formed in the first conduction type epitaxial layer, and a hard mask layer is formed on the first conduction type epitaxial layer; performing a first ion implantation process, and forming a second conductive type ion implantation layer in the first conductive type epitaxial layer below the groove; and carrying out a thermal annealing process to activate the ions implanted in the first ion implantation process. According to the invention, the second conductive type ion injection layer is formed in the first conductive type epitaxial layer at the bottom of the groove and the annealing process is carried out, so that the electric field intensity at the bottom of the groove is reduced, the breakdown voltage at the bottom of the groove is improved, and the on-resistance of the semiconductor device is reduced by improving the doping concentration of the first conductive type epitaxial layer or reducing the thickness of the first conductive type epitaxial layer on the basis.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
The structural design of the deep trench MOSFET device determines the parameter performance of the device to different degrees, and the on-resistance Ron as one of the key parameters determines the on-current and power loss of the device, so that the reduction of the on-resistance Ron is one of the important methods for improving the device performance. The on-resistance Ron of a single device is mainly composed of the source region resistance RN+Channel resistance RCHSurface charge accumulation layer resistance RAEpitaxial layer resistance RDAnd a substrate resistance RSUBAnd (4) forming. Wherein the source region resistor RN+And surface charge accumulation layer resistance RASmall, and generally negligible. Meanwhile, for the device with the specification of 70V and above, the channel resistance RCHThe ratio in the on-resistance Ron is small, and the epitaxial layer resistance RDThe percentage of the on-resistance Ron is usually 80% or more. Thus, the epitaxial layer resistance R is reducedDThe on-resistance Ron of the device can be effectively reduced, and the performance of the device is improved.
Conventional reduction of epitaxial layer resistance RDThe method has three types: the first method reduces the epitaxial layer resistance R by increasing the doping concentration of the epitaxial layerD(ii) a The second method reduces the epitaxial layer resistance R by reducing the thickness of the epitaxial layerD(ii) a The third method increases the number of resistors in the parallel unit by increasing the chip area to achieve the purpose of reducing the chip resistance. However, increasing the chip area results in a significant reduction in the number of chips produced from a single wafer, and thus this approach is not generally used where the process is tunable. The two methods of reducing the resistivity and the thickness of the epitaxial layer can reduce the breakdown voltage BV of the device while reducing the on-resistance, and the two methods cannot be balanced, so that the performance of the device is affected.
Therefore, there is a need for a method to reduce the on-resistance Ron of deep trench MOSFET devices without reducing the breakdown voltage BV.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can effectively reduce the electric field intensity at the bottom of a groove and improve the breakdown voltage at the bottom of the groove so as to improve the doping concentration of a first conductive type epitaxial layer or reduce the thickness of the first conductive type epitaxial layer on the basis of the electric field intensity and the breakdown voltage, and further reduce the on-resistance of the semiconductor device on the premise of not influencing other performances of the semiconductor device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a first conductive type epitaxial layer is formed on the substrate, a groove is formed in the first conductive type epitaxial layer, and a hard mask layer is formed on the first conductive type epitaxial layer;
performing a first ion implantation process, and forming a second conductive type ion implantation layer in the first conductive type epitaxial layer below the groove;
and carrying out a thermal annealing process to activate the ions implanted in the first ion implantation process.
Optionally, the method for manufacturing a semiconductor device further includes: and removing the hard mask layer, and forming a gate in the groove.
Optionally, the process of forming a gate in the trench includes:
performing a thermal oxidation growth process to form a gate oxide layer on the bottom and the side wall of the trench;
filling a grid material layer in the groove, wherein the grid material layer extends to cover the surfaces of the first conductive type epitaxial layers on the two sides of the groove;
and carrying out a planarization process on the grid material layer so as to form a grid in the groove.
Optionally, the material of the gate oxide layer includes silicon oxide, and the material of the gate material layer includes polysilicon.
Optionally, after forming the gate, the method further includes:
and performing a second ion implantation process to form a second conductive type body region in the first conductive type epitaxial layer, and performing a third ion implantation process to form a first conductive type source region on the surface of the second conductive type body region.
Optionally, the trench passes through the first conductivity type source region and the second conductivity type body region, and the second conductivity type ion implantation layer is within the first conductivity type epitaxial layer.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type.
Optionally, the resistivity of the first conductivity type epitaxial layer includes 0.1m Ω to 1m Ω.
Optionally, the thickness of the first conductivity type epitaxial layer includes 3 μm to 11 μm.
Optionally, the material of the hard mask layer includes silicon oxide.
In summary, the present invention provides a method for manufacturing a semiconductor device, in which a second conductive type ion implantation layer is formed in a first conductive type epitaxial layer at the bottom of a trench and an annealing process is performed to form a thin PN junction at a boundary between the second conductive type ion implantation layer and the first conductive type epitaxial layer, so as to effectively reduce an electric field strength at the bottom of the trench and improve a breakdown voltage at the bottom of the trench, so as to improve a doping concentration of the first conductive type epitaxial layer or reduce a thickness of the first conductive type epitaxial layer on this basis, thereby reducing an on-resistance of the semiconductor device without affecting other performances of the semiconductor device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2-6 are flow charts illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 is a simulation result of electric field distribution at the bottom of a trench in the method for manufacturing a semiconductor device according to an embodiment of the present invention;
wherein the reference numbers are as follows:
100-a substrate; 110-a first conductivity type epitaxial layer; 120-a second conductivity type body region; 130-a first conductivity type source region; 140-a hard mask layer; 150-a second conductivity type ion implantation layer;
200-a trench; 210-a gate oxide layer; 220-gate.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 1, the method for manufacturing a semiconductor device according to the present embodiment includes:
step S01: providing a substrate, wherein a first conductive type epitaxial layer is formed on the substrate, a groove is formed in the first conductive type epitaxial layer, and a hard mask layer is formed on the first conductive type epitaxial layer;
step S02: performing a first ion implantation process, and forming a second conductive type ion implantation layer in the first conductive type epitaxial layer below the groove;
step S03: and carrying out a thermal annealing process to activate the ions implanted in the first ion implantation process.
The method for manufacturing the semiconductor device provided in this embodiment is described in detail below with reference to fig. 2 to 6.
First, referring to fig. 2, step S01 is performed to provide a substrate 100, wherein a first conductive type epitaxial layer 110 is formed on the substrate 100, a trench 200 is formed in the first conductive type epitaxial layer 110, and a hard mask layer 140 is formed on the first conductive type epitaxial layer 110. Illustratively, the first conductive type epitaxial layer 110 is formed within the substrate 100 by a fourth ion implantation process; forming a hard mask layer 140 on the first conductive type epitaxial layer 110; a patterned photoresist layer (not shown) is formed on the hard mask layer 140, and the hard mask layer 140 and the first conductive type epitaxial layer 110 are etched by the patterned photoresist layer to form the trench 200. In other embodiments of the present invention, the specific process of forming the trench 200 may be adjusted according to actual needs, and the present invention is not limited thereto. In this embodiment, the first conductive type epitaxial layer 110 is an N-type epitaxial layer, and the type of the implanted ions in the fourth ion implantation process is N-type.
In this embodiment, the material of the hard mask layer 140 is silicon oxide, and in other embodiments of the present invention, the material of the hard mask layer 140 may be adjusted according to actual needs, and the silicon oxide is replaced by undoped silicate glass, silicon oxide, or other materials (such as spin-on dielectric material, fluid silicon oxide, or a combination thereof), which is not limited in this disclosure. The material selected for the substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and the substrate 100 may be a multi-layer structure of these semiconductor materials or a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeO), etc., which are well known to those skilled in the art and are not exemplified. The cross-sectional shape of the groove 200 may be a rectangle or an inverted trapezoid, and the bottom corner of the groove may be a circular arc or a right-angle.
Next, referring to fig. 3, in step S02, a first ion implantation process is performed to form a second conductive type ion implantation layer 150 in the first conductive type epitaxial layer 110 under the trench 200. Specifically, in the first ion implantation process, the type of implanted ions is different from the type of implanted ions in the fourth ion implantation process, in this embodiment, the type of implanted ions in the first ion implantation process is P-type, the implantation energy is 40-60 keV, and the implantation dose is 1012ions/cm2～1013ions/cm2The implantation angle is 0 ° so that the second conductive type ion implantation layer 150 is formed only in the first conductive type epitaxial layer 110 at the bottom of the trench 200. It should be noted that the presence of the hard mask layer 140 in the first ion implantation process helps to ensure that no ions are implanted into the first conductive type epitaxial layer 110 under the hard mask layer 140, and the first ion implantation processThe parameter setting of the process can be adjusted according to the actual situation, and the invention is not limited to this.
Subsequently, referring to fig. 4, a thermal annealing process is performed to activate the ions implanted in the first ion implantation process in step S03. Since the second conductive type ion implantation layer 150 and the first conductive type epitaxial layer 110 have different conductive types, a thin PN junction is formed at the boundary between the first conductive type epitaxial layer 110 and the second conductive type ion implantation layer 150 after the thermal annealing process is performed.
Referring to fig. 5, in the present embodiment, the method for manufacturing a semiconductor device further includes: the hard mask layer 140 is removed and a gate 220 is formed within the trench 200. Specifically, the process of forming the gate 220 in the trench 200 includes: performing a thermal oxidation growth process to form a gate oxide layer 210 on the bottom and the sidewall of the trench 200; filling a gate material layer (not shown) in the trench 200 by using a Chemical Vapor Deposition (CVD) process, wherein the gate material layer extends to cover the surface of the first conductive type epitaxial layer 110 on both sides of the trench 200; the gate material layer is subjected to a planarization process to form a gate 220 within the trench 200. In other embodiments of the present invention, the gate 220 may be formed by other methods, which are well known to those skilled in the art, and are not illustrated. Optionally, the material of the gate oxide layer 210 includes silicon oxide, and the material of the gate material layer includes polysilicon, in other embodiments of the present invention, the materials of the gate oxide layer 210 and the gate material layer may be adjusted according to actual needs, which is not limited in the present invention.
Next, referring to fig. 6, after the gate electrode 220 is formed, the method for manufacturing a semiconductor device further includes: a second ion implantation process is performed to form a second conductive type body region 120 within the first conductive type epitaxial layer 110, and a third ion implantation process is performed to form a first conductive type source region 130 on the surface of the second conductive type body region 120. The trench 200 passes through the first conductive-type source region 130 and the second conductive-type body region 120, and the first conductive-type ion implantation layer 150 is within the epitaxial layer 110. Optionally, the first conductivity type is an N type, and the second conductivity type is a P type. In this embodiment, the second conductive type ion implantation layer 150 is a P-type ion implantation layer, the second conductive type body region 120 is a P-type body region, and the first conductive type source region 130 is an N-type source region.
Fig. 7 is a simulation result of electric field distribution at the bottom of the trench in the method for manufacturing a semiconductor device according to this embodiment, in which a solid line represents the simulation result of electric field distribution at the bottom of the trench in this embodiment, a dotted line represents the simulation result of electric field distribution at the bottom of the trench in the conventional deep trench MOSFET device, and a region indicated by a circle is the electric field intensity at a corner of the bottom of the trench (i.e., a region most prone to breakdown in the semiconductor device). As can be seen from fig. 7, the manufacturing method of the semiconductor device according to the present embodiment effectively reduces the electric field strength at the bottom of the trench, thereby increasing the breakdown voltage at the bottom of the trench.
Further, the invention improves the breakdown voltage of the semiconductor device, so that the manufacturing method of the semiconductor device can be combined with the method for reducing the resistance of the epitaxial layer, and the balance of the breakdown voltage and the on-resistance is realized. In a conventional manufacturing method of a semiconductor device, a thickness of the first conductive type epitaxial layer is usually 6 μm, and a resistivity is usually 0.8m Ω, in this embodiment, the thickness of the first conductive type epitaxial layer may be reduced to 3 μm to 5 μm, or the resistivity of the first conductive type epitaxial layer may be reduced to 0.4m Ω to 0.6m Ω, so as to reduce the resistance of the first conductive type epitaxial layer, and further reduce the on-resistance of the semiconductor device on the premise of not affecting other performances of the semiconductor device.
In this embodiment, the manufacturing method of the semiconductor device is used for manufacturing a deep trench MOSFET device, and in other embodiments of the present invention, the manufacturing method of the semiconductor device may be used for manufacturing other semiconductor devices having the same structure or for manufacturing different types of trench MOSFETs, which is not limited by the present invention.
In summary, the present invention provides a method for manufacturing a semiconductor device, in which a second conductive type ion implantation layer is formed in a first conductive type epitaxial layer at the bottom of a trench and an annealing process is performed to form a thin PN junction at a boundary between the second conductive type ion implantation layer and the first conductive type epitaxial layer, so as to effectively reduce an electric field strength at the bottom of the trench and improve a breakdown voltage at the bottom of the trench, so as to improve a doping concentration of the first conductive type epitaxial layer or reduce a thickness of the first conductive type epitaxial layer on this basis, thereby reducing an on-resistance of the semiconductor device without affecting other performances of the semiconductor device.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a first conductive type epitaxial layer is formed on the substrate, a groove is formed in the first conductive type epitaxial layer, and a hard mask layer is formed on the first conductive type epitaxial layer;
performing a first ion implantation process, and forming a second conductive type ion implantation layer in the first conductive type epitaxial layer below the groove;
and carrying out a thermal annealing process to activate the ions implanted in the first ion implantation process.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising: and removing the hard mask layer, and forming a gate in the groove.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the process of forming a gate in the trench includes:
performing a thermal oxidation growth process to form a gate oxide layer on the bottom and the side wall of the trench;
filling a grid material layer in the groove, wherein the grid material layer extends to cover the surfaces of the first conductive type epitaxial layers on the two sides of the groove;
and carrying out a planarization process on the grid material layer so as to form a grid in the groove.
4. A method of manufacturing a semiconductor device according to claim 3, wherein the material of the gate oxide layer comprises silicon oxide and the material of the gate material layer comprises polysilicon.
5. The method for manufacturing a semiconductor device according to claim 2, further comprising, after forming the gate electrode:
and performing a second ion implantation process to form a second conductive type body region in the first conductive type epitaxial layer, and performing a third ion implantation process to form a first conductive type source region on the surface of the second conductive type body region.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the trench penetrates the first conductivity type source region and the second conductivity type body region, and the second conductivity type ion implantation layer is within the first conductivity type epitaxial layer.
7. The method for manufacturing a semiconductor device according to claim 5, wherein the first conductivity type is an N-type, and wherein the second conductivity type is a P-type.
8. The manufacturing method of a semiconductor device according to claim 2, wherein a resistivity of the first conductivity type epitaxial layer includes 0.1m Ω to 1m Ω.
9. The manufacturing method of a semiconductor device according to claim 2, wherein a thickness of the first conductivity type epitaxial layer includes 3 μm to 11 μm.
10. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the hard mask layer comprises silicon oxide.
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| CN202011643726.9A CN112802753A (en) | 2020-12-31 | 2020-12-31 | Method for manufacturing semiconductor device |
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| CN202011643726.9A CN112802753A (en) | 2020-12-31 | 2020-12-31 | Method for manufacturing semiconductor device |
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2020
- 2020-12-31 CN CN202011643726.9A patent/CN112802753A/en active Pending
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| CN103579345A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | High voltage field balance metal oxide field effect transistor (FBM) |
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