CN111370486A - Groove type MOS field effect transistor, method and electronic equipment - Google Patents
Groove type MOS field effect transistor, method and electronic equipment Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a groove type MOS field effect transistor, a method and electronic equipment. The field effect transistor comprises a first electrode metal layer, a semiconductor substrate layer, an epitaxial layer, a well region and a contact region; the trench is provided with a protection region at the bottom, a second protection region extending to the bottom of the trench is arranged on one side wall of the trench, the second protection region is in contact with the protection region, the well region and the contact region, and the trench is also provided with a gate insulating layer and a gate electrode, wherein the gate insulating layer is arranged close to the protection region and partially surrounds the gate electrode so as to isolate the gate electrode from the second protection region, the well region and the contact region; an insulating dielectric layer; a second electrode metal layer.
Description
Technical Field
The invention relates to the field of electronics, in particular to a groove type MOS field effect transistor, a method and electronic equipment.
Background
Trench metal oxide thin film transistors have received much attention because they have a smaller on-resistance than planar gate structures. In addition, the trench gate field effect transistor can be provided with a protection region at the bottom of the trench, so that the electric field intensity at the bottom of the trench gate can be reduced, and the reliability of the product in application can be improved.
However, the trench type MOS field effect transistor, the method and the electronic device still need to be improved.
Disclosure of Invention
The present invention is based on the discovery and recognition by the inventors of the following facts and problems:
at present, the stability of the trench type field effect transistor still needs to be improved. Although the trench field effect transistor can improve the protection of the gate insulating layer by arranging the protection region at the bottom of the trench gate to prevent the dielectric layer from generating Time Dependent Dielectric Breakdown (TDDB), the current potential of the protection region at the bottom of the trench gate is floating, and therefore, when a high voltage is applied to the drain electrode, an induced potential is generated in the protection region. That is, a potential difference still exists between the protection region and the trench gate, and the insulating dielectric layer at the bottom of the trench gate still bears a certain electric field strength. Therefore, the device is in an accumulation state, and after a period of time, the dielectric layer at the position still has the risk of being broken down. Particularly, for the trench MOS field effect transistor made of SiC material, the SiC semiconductor device has the advantages of high voltage resistance, low on-state resistance, high current density, and the like, and thus is more commonly applied to high-temperature, high-frequency, and high-power applications, and therefore the stability of the trench MOS field effect transistor based on SiC material is more to be enhanced.
The present invention aims to alleviate or solve at least to some extent at least one of the above mentioned problems.
In one aspect of the invention, a trench type MOS field effect transistor is presented. The trench type MOS field effect transistor includes: the first electrode metal layer, the semiconductor substrate layer and the epitaxial layer are sequentially stacked; the semiconductor substrate layer is arranged on the epitaxial layer, and the well region and the contact region are sequentially stacked and arranged on one side, away from the semiconductor substrate layer, of the epitaxial layer; the trench extends into the contact region, the well region and the epitaxial layer, a protective region is arranged at the bottom of the trench, a second protective region extending to the bottom of the trench is arranged on one side wall of the trench, the second protective region is in contact with the protective region, the well region and the contact region, a gate insulating layer and a gate electrode are further arranged in the trench, the gate insulating layer is arranged close to the protective region and partially surrounds the gate electrode, and therefore the gate electrode is isolated from the second protective region, the well region and the contact region; the insulating medium layer is arranged on one side of the groove far away from the epitaxial layer and covers the grid and a part of the contact region; and the second electrode metal layer is arranged on one side of the insulating medium layer far away from the groove and covers the insulating medium layer and a part of the contact region. Therefore, the dielectric layer (the gate insulating layer) can be protected, and the device failure caused by breakdown due to the fact that the dielectric layer at the position bears an electric field with certain strength for a long time can be avoided. Further, the device stability of the trench type MOS field effect transistor can be improved.
In yet another aspect of the present invention, a method of fabricating a trench type MOS field effect transistor is presented. The method comprises the following steps: providing a semiconductor substrate; forming an epitaxial layer on the semiconductor substrate; doping one side of the epitaxial layer, which is far away from the semiconductor substrate, so as to form a well region; doping a partial region of the well region far away from the epitaxial layer to form a contact region; etching to form a groove extending to the epitaxial layer, wherein the side wall of the groove is contacted with the well region and the contact region; forming a protection region at the bottom of the trench by vertical implantation, and forming a second protection region at a sidewall of the trench by oblique implantation; sequentially forming a gate insulating layer and a gate electrode in the trench, wherein the gate insulating layer partially surrounds the gate electrode to isolate the gate electrode from the second protection region, the well region and the contact region; forming an insulating medium layer and a second electrode metal layer, wherein the insulating medium layer is arranged on one side of the groove far away from the epitaxial layer and covers the grid electrode and one part of the contact region, and the second electrode metal layer is arranged on one side of the insulating medium layer far away from the groove and covers the insulating medium layer and one part of the contact region; and forming a first electrode metal layer on one side of the semiconductor substrate far away from the epitaxial layer. Therefore, the groove type MOS field effect transistor with the two protection regions can be obtained simply and conveniently, a dielectric layer (a gate insulating layer) can be protected, and the failure of a device caused by breakdown due to the fact that the dielectric layer at the position bears an electric field with certain strength for a long time is avoided. Further, the device stability of the trench type MOS field effect transistor can be improved.
In another aspect of the invention, an electronic device is provided. According to an embodiment of the present invention, the electronic device comprises the field effect transistor as described above, whereby the electronic device has all the features and advantages of the field effect transistor as described above, which are not described in detail herein. Generally, the electronic equipment has good service performance and better stability.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a trench type MOS field effect transistor according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a trench type MOS field effect transistor according to a scheme before improvement;
FIG. 3 is a flow chart illustrating a method of forming a trench type MOS field effect transistor according to an embodiment of the invention;
FIG. 4 is a schematic flow chart of a portion of a method for fabricating a trench type MOS field effect transistor according to an embodiment of the invention;
FIG. 5 is a schematic flow chart of a portion of a method for fabricating a trench type MOS field effect transistor according to an embodiment of the invention;
FIG. 6 is a schematic flow chart of a portion of a method for fabricating a trench type MOS field effect transistor according to an embodiment of the invention; and
fig. 7 is a flow chart illustrating a portion of a method for fabricating a trench MOS field effect transistor according to an embodiment of the present invention.
Description of reference numerals:
100: a semiconductor substrate; 200: an epitaxial layer; 300: a well region; 400: a contact zone; 500: a source region; 10: a trench; 11: a protection zone; 12: a second protection zone; 20: a barrier layer; 610: a gate insulating layer; 620: a gate electrode; 710: an insulating dielectric layer; 720: a second electrode metal layer; 800: a first electrode metal layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In one aspect of the invention, a trench type MOS field effect transistor is presented. According to an embodiment of the present invention, referring to fig. 1, the field effect transistor includes: the semiconductor substrate layer 100 and the epitaxial layer 200, the semiconductor substrate layer 100 is provided with a first electrode metal layer 800 on the side away from the epitaxial layer 200. The epitaxial layer 200 has a well 300 and a contact 400 on a side thereof away from the semiconductor substrate 100. The field effect transistor further comprises a gate 620 and a gate insulator 610 disposed in a trench extending from the top of the contact region 400 into the epitaxial layer 200. The sidewalls of the trenches contact well region 300, contact region 400, and epitaxial layer 200. The gate insulating layer 610 is disposed near the bottom of the trench (near the side of the epitaxial layer 200) and partially surrounds the gate 620, the bottom of the trench has a guard region 11, a sidewall of the trench has a second guard region 12, and the second guard region 12 is in contact with the guard region 11, the well region 300 and the contact region 400, in other words, the second guard region 12 connects the guard region 11 with the well region 300 and the contact region 400. That is, the gate insulating layer 610 isolates the gate electrode 620 from the second protective region 12, the well region 300, and the contact region 400. The side of the trench and contact region 400 away from the semiconductor substrate 100 further has an insulating dielectric layer 710, and the insulating dielectric layer 710 covers the gate 620 and a portion of the contact region 400. The side of the insulating dielectric layer 710 remote from the contact region 400 is covered with a second electrode metal layer 720. Therefore, the dielectric layer (the gate insulating layer) can be protected, and the device failure caused by breakdown due to the fact that the dielectric layer at the position bears an electric field with certain strength for a long time can be avoided. Further, the device stability of the trench type MOS field effect transistor can be improved.
Note that, one of the first electrode metal layer 800 and the second metal electrode layer 720 is a source metal layer, and the other is a drain metal layer. The positions of the source and drain metal layers can be interchanged, and the positions of the source and drain metal layers are determined by the doping types of the epitaxial layer 200, the well region 300 and the contact region 400. It will be appreciated by those skilled in the art that in the field effect transistor there are also source/drain regions. Taking the first metal electrode layer 800 as a drain metal layer and the second metal electrode layer 720 as a source metal layer as an example, the field effect transistor further includes a source region 500.
For convenience of understanding, the following first briefly explains the principle of improving the stability of the trench type MOS field effect transistor:
as mentioned above, referring to fig. 2, in the trench field effect transistor of the present invention, in order to enhance the stability, a protection layer, i.e. the protection region 11, may be disposed at the bottom of the trench. However, when the field effect transistor is located in a strong field intensity environment, an induced potential is still generated at the bottom of the protection region 11, so that the insulating medium, i.e., the gate insulating layer 610, located thereon has a certain risk of breakdown. The second passivation layer 12 is disposed on the sidewall of the trench, so that the passivation region 11 can be connected to the well 300 and the contact region 400, and the contact region 400 contacts the source metal region (the second metal electrode layer 720). I.e. the potential of the guard region at the bottom of the trench, is interconnect dependent on the potential of the source metal region. When a high operating voltage is applied to the drain electrode (the first metal electrode layer 800), the protection region (the protection region 11) with a fixed potential can shield the trench gate from an electric field, so that the trench gate is protected from electric field stress, and the long-term reliability of the device application is improved. The other side of the trench may not be provided with a protection region, which in turn may serve as a channel region of the device, and the gate 620 controls the device to provide a switching function. That is, the bottom of the protection region 11 can be connected to the source/drain (the second metal electrode layer 720) through the second passivation layer 12, the well 300 and the contact region 400, so that the protection region 11 and the second passivation layer 12 can be under a relatively uniform electric field strength. That is, the bottom of the protection region 11 does not have a relatively large electric field strength, so that the gate insulating layer 610 can be better protected from a time-dependent breakdown event. This can improve the stability of the field effect transistor.
According to an embodiment of the present invention, the semiconductor substrate 100 and the epitaxial layer 200 may have the same doping type, and the guard region 11, the second guard region 12, the well region 300 and the contact region 400 may have the same doping type, which is opposite to the doping type of the semiconductor substrate 100 and the epitaxial layer 200. For example, the semiconductor substrate 100 and the epitaxial layer 200 may be N-type, and the guard region 11, the second guard region 12, the well region 300 and the contact region 400 may be P-type doped.
According to an embodiment of the present invention, the doping concentrations of the protection region 11 and the second protection region 12 may be similar, and the doping concentration of the contact region 400 may be greater than the doping concentrations of the protection region 11 and the second protection region 12. According to some embodiments of the invention, the doping concentration of the contact region may be 1018～1021cm-3. The doping concentrations of the protection region 11 and the second protection region 12 may be 10 independently16～1021cm-3。
According to an embodiment of the present invention, the size and formation manner of the trench may not be particularly limited as long as the protection region 11, the second protection region 12, the gate insulating layer 610, and the gate electrode 620 described above can be accommodated. For example, the trench may be formed at a predetermined position by providing a barrier layer in advance and then by photolithography. The depth of the trench may be not less than 0.5 microns and the width of the trench may be greater than 0.1 microns. Thereby, the structure described above can be accommodated well.
According to the embodiment of the present invention, the sizes of the protection region 11 and the second protection region 12 are not particularly limited, and those skilled in the art can design them according to the withstand voltage requirement of the device. For example, the thickness (in the direction perpendicular to the semiconductor substrate 100) of the protection region 11 may be not less than 0.1 μm. As mentioned above, the second protection region 12 is used to shield the electric field at the sidewall of the trench and thus protect the gate dielectric layer, and therefore, the size of the second protection region 12 can also be designed according to the requirement of the device. For example, according to an embodiment of the present invention, the thickness of the second protection region 12 in the direction perpendicular to the trench sidewall may be not less than 0.1 μm.
As described above, according to the field effect transistor of the embodiment of the present invention, since the second guard region is provided at one side wall of the trench and the second guard region is connected to the electrode (source or drain) through the well region, the contact region, no source region or drain region is provided at the side where the second guard region is provided. And forming a source/drain region which is contacted with the insulating medium layer and the second electrode metal layer on one side of the groove where the second protection region is not arranged. As will be understood by those skilled in the art, when the second electrode metal layer is a source electrode, a source region is disposed at the sidewall of the trench; when the second electrode metal layer is a drain electrode, a drain electrode region is arranged at the side wall of the groove. The doping type of the source region or the drain region is different from that of the well region. Namely: the doping type of the source region or the drain region may be the same as the doping type of the epitaxial layer. It should be particularly noted that although the field effect transistor according to the embodiment of the present invention cannot form source/drain regions on both sides of the trench due to the provision of the second protection region 11, the electrical performance of the field effect transistor can be ensured by designing the specific parameters of the source/drain regions on one side.
It should be noted that the trench MOS field effect transistor according to the embodiment of the present invention may also have a structure of a conventional trench MOS field effect transistor. For example, the specific material of the metal electrodes (the first metal electrode layer 800 and the second metal electrode layer 720) of the field effect transistor may be a source-drain metal commonly used in the art, for example, when the first metal electrode layer 800 is a drain and the second metal electrode layer 720 is a source, the first metal electrode layer 800 for forming the drain may be silver, and the second metal electrode layer 720 may be aluminum. In addition, the gate may be a polysilicon gate.
In another aspect of the invention, the invention provides a method for preparing a trench type MOS field effect transistor. According to the embodiment of the invention, the field effect transistor prepared by the method can be the trench type MOS field effect transistor described above. Specifically, referring to fig. 3, the method includes:
s100: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate
According to an embodiment of the present invention, referring to (1) in fig. 4, in this step, a semiconductor substrate 100 having an epitaxial layer 200 is provided. The detailed description of the semiconductor substrate and the epitaxial layer regarding the specific structure, material and doping thereof has been given above and will not be repeated herein. For example, according to some specific embodiments of the present invention, the semiconductor substrate may be a SiC substrate and the doping concentration of the epitaxial layer may be 1013cm-3～1017cm-3The thickness may be greater than 6 microns.
S200: doping one side of the epitaxial layer far away from the semiconductor substrate to form a well region
In this step, referring to (2) in fig. 4, a side of the epitaxial layer 200 away from the semiconductor substrate is doped to form a well region according to an embodiment of the present invention. Specifically, the doping may be performed by ion implantation into the epitaxial layer. According to some embodiments of the present invention, the epitaxial layer may be doped N-type, and the top of the epitaxial layer (away from the semiconductor) is ion implanted to form a P-type doped well region 300. The doping concentration of the P-well region can be 1016cm-3～1018cm-3The thickness may be greater than 0.5 microns.
S300: doping partial region of the well region far away from the epitaxial layer to form a contact region
According to an embodiment of the present invention, referring to (3) in fig. 4, in this step, a portion of the well region 300 away from the epitaxial layer 200 is doped to form a contact region 400. Specifically, ion implantation may be performed at positions on both sides of the trench to be formed at a later stage, so as to form the two contact regions 400. In this step, the type of ion implantation may be the same as that of the well region 300, for example, it may be a P-type implantation. The ion implantation concentration and thickness of the contact region 400 have been described in detail above, and will not be described herein.
As previously described, the method may further include the step of forming source/drain regions. Taking the case that the epitaxial layer is N-type and the well region and the contact region are P-type, the method may further include the step of forming a source region: referring to (4) of fig. 5, a heavily doped (N +) source region 500 may be formed by selective area ion implantation. Since the second guard region indirectly connected to the source (or drain) needs to be formed at one side of the trench in the subsequent step in the method according to the embodiment of the present invention, the source/drain region needs to be located at only one side of the subsequently formed trench in forming the source/drain region, so that the second guard region of the subsequent layer can be in direct contact with the well region 300 and the contact region 400. Therefore, when forming the source region, the position of the ion implantation needs to be controlled, so that the region implanted with the ion in this step cannot be connected to both contact regions 400. The ion implantation concentration and thickness of the source region have been described in detail above, and are not described in detail herein. Specifically, a heavily doped (N +) source region may be formed, and the concentration of the source region may be 1018cm-3～1021cm-3The thickness may be greater than 0.2 microns.
S400: etching to form a trench extending to the epitaxial layer
In this step, trenches extending to the epitaxial layer are formed by etching, according to an embodiment of the present invention. Specifically, referring to (5) in fig. 5, the trench may be obtained by: first, a barrier layer 20 is deposited on the surface of the contact region 400, wherein the barrier layer may be formed of silicon dioxide or silicon nitride and may have a thickness of 0.1-3 μm. Subsequently, trenches 10 are formed by photolithographic etching, the trenches extending into the epitaxial layer 200, one sidewall of the trenches 10 contacting the well region 300, the contact region 400, where a second guard region is formed in a subsequent step. The trench 10 and the sidewall opposite to the intended second guard region are in contact with the well region 300, the contact region 400 and the source region 500. The trenches may have a depth greater than 0.5 microns and a width greater than 0.1 microns.
S500: forming a protection region at the bottom of the trench by vertical implantation, and forming a second protection region at a sidewall of the trench by inclined implantation
According to an embodiment of the invention, in this step, the protection region and the second protection region are formed by ion implantation. The location and function of the protection zone and the second protection zone have been described in detail above, and are not described in detail here. For example, according to a specific embodiment of the present invention, referring to (6) in fig. 5 and (7) in fig. 6, the protection region 11 and the second protection region 12 may be formed by: first, a protection region 11 at the bottom of the trench is formed by vertical implantation. The doping type, doping concentration, thickness and other parameters of the protection region 11 have been described in detail above, and are not described in detail here. Subsequently, a second protective region 12 located at the side of the trench 10 may be formed by angled implantation. The protective region is formed first and then the second protective region is formed, and the protective region formed before is not affected by the later process step, so that the doping concentrations of the two protective regions (the protective region and the second protective region) can be the same or different, as long as the doping types are the same.
S600: sequentially forming a gate insulating layer and a gate electrode in the trench
According to an embodiment of the invention, in this step, a gate structure is formed in the trench, namely: a gate insulating layer is formed to separate the gate electrode from other structures (the guard region, the second guard region, the contact region, and the well region), as well as the gate electrode. The specific parameters of the gate insulating layer and the gate electrode have been described in detail above, and are not described in detail here.
According to some embodiments of the present invention, the gate structure formed in this step may also be a polysilicon gate. Specifically, referring to (8) in fig. 6, the barrier layer 20 may be removed first, and a gate insulating layer (insulating gate dielectric layer) 610 covering the surface of the previously formed semiconductor structure may be formed. The gate insulating layer 610 may be silicon dioxide. Subsequently, referring to (9) of fig. 6, polysilicon is deposited in the trench and the polysilicon at the surface (above the contact region 400 and the source region 500) is removed, leaving the polysilicon in the trench, forming a polysilicon gate electrode 620. The polysilicon may be heavily doped and its sheet resistance may be controlled to less than 100 ohms per sheet. Subsequently, referring to (10) in fig. 7, the gate insulating layer 610 covering over the contact region 400 and the source region 500 is removed.
S700: forming an insulating dielectric layer and a second electrode metal layer
According to an embodiment of the present invention, in this step, an insulating dielectric layer and a second electrode metal layer are formed. As described above, the second electrode metal layer may be used to form a source electrode or a drain electrode, and the type of the second electrode metal layer is determined by the type of carriers. According to an embodiment of the present invention, the second electrode metal layer may be a source electrode. Specifically, referring to (11) in fig. 7, an insulating layer is first formed on the surface of the structure obtained in (10) in fig. 7, and then a portion of the insulating layer is etched and removed by a patterning process such as photolithography, so as to obtain an insulating dielectric layer 710 (or referred to as an interlayer insulating layer ILD). The insulating dielectric layer 710 may be made of silicon dioxide or silicon nitride, and may have a thickness of 0.1-3 μm. The insulating dielectric layer 710 at least needs to cover the gate 620. Subsequently, an operation of depositing the second electrode metal layer 720, or depositing a front metal, may be performed. The front metal may be aluminum and may be about 4 microns thick.
S800: forming a first electrode metal layer on one side of the semiconductor substrate far away from the epitaxial layer
According to an embodiment of the present invention, a first electrode metal layer, or deposition back metal, is formed on the side of the semiconductor substrate 100 away from the epitaxial layer 200. Specifically, referring to (12) in fig. 7, the back metal may be silver, and the thickness may be about 1 μm.
Therefore, the groove type MOS field effect transistor with the two protection regions can be obtained simply and conveniently, a dielectric layer (a gate insulating layer) can be protected, and the failure of a device caused by breakdown due to the fact that the dielectric layer at the position bears an electric field with certain strength for a long time is avoided. Further, the device stability of the trench type MOS field effect transistor can be improved.
In yet another aspect of the present invention, an electronic device is presented. The electronic device comprises a trench type MOS field effect transistor as described above. Thus, the electronic device has all the features and advantages of the field effect transistor described above, which are not described in detail herein. Generally, the electronic equipment has the advantages of good stability and difficulty in generating insulation dielectric breakdown.
The present invention is illustrated below by way of specific examples, which are intended to be illustrative only and not to limit the scope of the present invention in any way, and unless otherwise specified, conditions or steps not specifically recited are generally conventional and reagents and materials used therein may be commercially available.
The first embodiment is as follows:
a schematic diagram of the fabricated field effect transistor may be as shown in fig. 1. The semiconductor substrate is SiC, and the doping concentration of the epitaxial layer can be 1016cm-3The thickness is about 10 microns. The concentration of the P well region formed by ion implantation is 1017cm-3And the thickness is about 0.9 micron. The concentration of the P + contact region is 1019cm-3About, the thickness is slightly larger than 0.2 micron. The concentration of N + source region is 1020cm-3Left and right. And then forming a P-type protection region at the bottom of the groove by vertical injection, and forming a second protection region at the side surface of the groove by inclined injection. And then, forming an insulated gate dielectric layer with the thickness of 0.01-0.3 microns. And depositing to form heavily doped polysilicon to form a polysilicon gate electrode. And then, forming an interlayer insulating layer, etching to form an insulating medium layer, and finally depositing front metal and back metal to obtain the groove type MOS field effect transistor.
Comparative example 1:
the remaining structure is the same as that of embodiment 1, except that only the protective region of the bottom layer is provided in the trench, and the protective region is not formed at the sidewall. Namely: the step of angled implantation is omitted.
Fitting tests were conducted on the field effect transistors prepared in example 1 and comparative example 1 and the results showed that the maximum electric field strength at the bottom of the trench (about 5MV/cm) in example 1 was much lower than the maximum electric field strength at the bottom of the trench (about 10MV/cm) in comparative example 1 at a certain voltage (1200V). Therefore, according to the field effect transistor provided by the embodiment of the invention, the field intensity born by the insulating medium is smaller, so that the field effect transistor has better device stability.
In the description of the present invention, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention but do not require that the present invention must be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction. In addition, it should be noted that the terms "first" and "second" in this specification are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (16)
1. A trench type MOS field effect transistor, comprising:
the first electrode metal layer, the semiconductor substrate layer and the epitaxial layer are sequentially stacked;
the semiconductor substrate layer is arranged on the epitaxial layer, and the well region and the contact region are sequentially stacked and arranged on one side, away from the semiconductor substrate layer, of the epitaxial layer;
the trench extends into the contact region, the well region and the epitaxial layer, a protective region is arranged at the bottom of the trench, a second protective region extending to the bottom of the trench is arranged on one side wall of the trench, the second protective region is in contact with the protective region, the well region and the contact region, a gate insulating layer and a gate electrode are further arranged in the trench, the gate insulating layer is arranged close to the protective region and partially surrounds the gate electrode, and therefore the gate electrode is isolated from the second protective region, the well region and the contact region;
the insulating medium layer is arranged on one side of the groove far away from the epitaxial layer and covers the grid and a part of the contact region;
and the second electrode metal layer is arranged on one side of the insulating medium layer far away from the groove.
2. The trench MOS field effect transistor of claim 1, wherein the semiconductor substrate layer is formed of SiC or Si.
3. The trench MOS field effect transistor of claim 1, wherein the guard region, the second guard region, the well region, and the contact region have the same doping type.
4. The trench MOS FET of claim 3, wherein the protection region and the second protection region have similar doping concentrations, and the contact region has a doping concentration greater than the doping concentrations of the protection region and the second protection region.
5. The trench MOS FET of claim 4, wherein the contact region has a doping concentration of 1018～1021cm-3The doping concentration of the protection region and the doping concentration of the second protection region are respectively 10 independently16～1021cm-3。
6. The trench MOS FET of claim 1, wherein the thickness of the protection region is not less than 0.1 μm.
7. The trench MOS FET of claim 1, wherein the second guard region has a thickness in a direction perpendicular to the trench sidewalls of not less than 0.1 μm.
8. The trench type MOS field effect transistor of claim 1, further comprising a source/drain region in contact with the insulating dielectric layer and the second electrode metal layer at a side of the trench where the second protection region is not disposed, wherein a doping type of the source/drain region is different from a doping type of the well region.
9. A method of fabricating a trench MOS field effect transistor, comprising:
providing a semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate;
doping one side of the epitaxial layer, which is far away from the semiconductor substrate, so as to form a well region;
doping a partial region of the well region far away from the epitaxial layer to form a contact region;
etching to form a groove extending to the epitaxial layer, wherein the side wall of the groove is contacted with the well region and the contact region;
forming a protection region at the bottom of the trench by vertical implantation, and forming a second protection region at a sidewall of the trench by oblique implantation;
sequentially forming a gate insulating layer and a gate electrode in the trench, wherein the gate insulating layer partially surrounds the gate electrode to isolate the gate electrode from the second protection region, the well region and the contact region;
forming an insulating medium layer and a second electrode metal layer, wherein the insulating medium layer is arranged on one side of the groove far away from the epitaxial layer and covers the grid electrode and one part of the contact region, and the second electrode metal layer is arranged on one side of the insulating medium layer far away from the groove and covers the insulating medium layer and one part of the contact region; and
and forming a first electrode metal layer on one side of the semiconductor substrate far away from the epitaxial layer.
10. The method of claim 9, wherein the semiconductor substrate is a SiC substrate, the epitaxial layer has a thickness greater than 6 microns,
optionally, the epitaxial layer has a doping concentration of 1013～1017cm-3；
Optionally, the doping concentration of the well region is 1016～1018cm-3；
Optionally, the doping concentration of the contact region is 1018～1021cm-3。
11. The method of claim 9, wherein the guard region, the second guard region, the well region and the contact region have the same doping type, the guard region and the second guard region have similar doping concentrations, and the well region has a doping concentration greater than the guard region and the second guard region.
12. The method of claim 11, wherein the step of removing the metal oxide layer comprises removing the metal oxide layer from the metal oxide layerIn that the doping concentration of the contact region is 1018～1021cm-3The doping concentration of the protection region and the doping concentration of the second protection region are respectively 10 independently16～1021cm-3。
13. The method of claim 9, wherein the vertical implant comprises: controlling the thickness of the protection region to be not less than 0.1 micrometer.
14. The method of claim 9, wherein the angled implant comprises: and controlling the thickness of the second protection region in a direction vertical to the side wall of the groove to be not less than 0.1 micrometer.
15. The method of claim 9, wherein after forming the contact region and before forming the trench, further comprising:
doping partial region of the well region and partial region of the contact region to form a source/drain region,
and the second protection region is formed on a side of the trench away from the side where the source/drain region is formed.
16. An electronic device comprising the trench type MOS field effect transistor according to any one of claims 1 to 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120261676A1 (en) * | 2009-12-24 | 2012-10-18 | Rohn Co., Ltd. | SiC FIELD EFFECT TRANSISTOR |
| CN102856382A (en) * | 2011-06-29 | 2013-01-02 | 株式会社电装 | Silicon carbide semiconductor device |
| CN104969357A (en) * | 2013-02-05 | 2015-10-07 | 三菱电机株式会社 | Insulating gate-type silicon carbide semiconductor device and method for manufacturing same |
| CN106206755A (en) * | 2015-05-27 | 2016-12-07 | 丰田自动车株式会社 | Schottky-barrier diode |
| WO2018225600A1 (en) * | 2017-06-06 | 2018-12-13 | 三菱電機株式会社 | Semiconductor device and power conversion apparatus |
| US20190181229A1 (en) * | 2017-12-11 | 2019-06-13 | Fuji Electric Co., Ltd. | Insulated-gate semiconductor device and method of manufacturing the same |
| CN110036461A (en) * | 2016-12-08 | 2019-07-19 | 克里公司 | Power semiconductor and correlation technique with the gate trench with injection side wall |
-
2018
- 2018-12-25 CN CN201811595136.6A patent/CN111370486A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120261676A1 (en) * | 2009-12-24 | 2012-10-18 | Rohn Co., Ltd. | SiC FIELD EFFECT TRANSISTOR |
| CN102856382A (en) * | 2011-06-29 | 2013-01-02 | 株式会社电装 | Silicon carbide semiconductor device |
| CN104969357A (en) * | 2013-02-05 | 2015-10-07 | 三菱电机株式会社 | Insulating gate-type silicon carbide semiconductor device and method for manufacturing same |
| CN106206755A (en) * | 2015-05-27 | 2016-12-07 | 丰田自动车株式会社 | Schottky-barrier diode |
| CN110036461A (en) * | 2016-12-08 | 2019-07-19 | 克里公司 | Power semiconductor and correlation technique with the gate trench with injection side wall |
| WO2018225600A1 (en) * | 2017-06-06 | 2018-12-13 | 三菱電機株式会社 | Semiconductor device and power conversion apparatus |
| US20190181229A1 (en) * | 2017-12-11 | 2019-06-13 | Fuji Electric Co., Ltd. | Insulated-gate semiconductor device and method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802753A (en) * | 2020-12-31 | 2021-05-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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