CN104701374B - Tunneling field-effect transistor and forming method thereof - Google Patents
Tunneling field-effect transistor and forming method thereof Download PDFInfo
- Publication number
- CN104701374B CN104701374B CN201310669773.4A CN201310669773A CN104701374B CN 104701374 B CN104701374 B CN 104701374B CN 201310669773 A CN201310669773 A CN 201310669773A CN 104701374 B CN104701374 B CN 104701374B
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- doped region
- effect transistor
- layer
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of tunneling field-effect transistor and forming method thereof, the tunneling field-effect transistor includes：Semiconductor substrate；The first semiconductor layer in the Semiconductor substrate, first semiconductor layer has the first doping type；Ring-shaped groove in first semiconductor layer；On first semiconductor layer and by the first circular doped region of the ring-shaped groove, first doped region has the first doping type；The first channel region on first doped region；The second doped region on first channel region, second doped region has the second doping type；Positioned at the second channel region of second doped region, the first channel region and the first doped region side and the ring-shaped groove bottom；Grid in the ring-shaped groove；Gate dielectric layer between second channel region and the grid.What the tunneling field-effect transistor tunneling path and tunnelling area all increased, therefore the performance of tunneling field-effect transistor is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of tunneling field-effect transistor and forming method thereof.
Background technology
In order to be able to which in ultralow pressure low-power consumption field, semiconductor device application is obtained into super steep Asia using new conduction mechanism
The device architecture and its preparation process of threshold slope have become everybody focus of attention under small size device.Ground in the last few years
The persons of studying carefully propose one kind and possible solution, are exactly using tunneling field-effect transistor（Tunnel Field Effect
Transistor, TFET）.Tunneling field-effect transistor is different from traditional metal oxide layer-semiconductor field effect transistor
（MOSFET）, the source and drain doping type of tunneling field-effect transistor is on the contrary, control the P-I-N knots of reverse bias using grid
Bandtoband realizes conducting, can break through conventional MOS FET sub-threshold slopes 60mV/dec limitation.
A kind of existing tunneling field-effect transistor is as shown in figure 1, it includes being located at Semiconductor substrate（It is not shown）On it is exhausted
Edge layer 101, positioned at insulating barrier（insulator）Semiconductor layer 103 on 101, the source region 102 positioned at the both sides of semiconductor layer 103
With drain region 104, the wherein doping type in source region 102 and drain region 104 on the contrary, grid stacked structure on semiconductor layer 103, institute
State gate dielectric layer 105 and grid 106 that grid stacked structure includes being located on semiconductor layer 103.
However, existing tunneling field-effect transistor is tied tunnelling probability by source and tunnel area is limited, it is faced with ON state
The problem of electric current is small and subthreshold swing declines.Although new tunneling field-effect transistor implementation has been suggested, such as
Green FET, still, due to suppressing edge tunnel component（lateral tunneling component）Or reduce off-state current
（off-state current）Difficulty, high driving current and the amplitude of oscillation less than 60mV/dec are never implemented.Always
It, is although the simulation result of tunneling field-effect transistor is very attractive, due to low driving current（drive
current）With degraded subthreshold swing（subthreshold swing）, the experimental result of tunneling field-effect transistor is simultaneously
Can not be with traditional mos field effect transistor（MOSFET）Competition.
For this reason, it may be necessary to a kind of new tunneling field-effect transistor and preparation method thereof, to solve tunneling field-effect transistor
The problem of ON state current is small and subthreshold swing is unsatisfactory for demand.
The content of the invention
The problem of present invention is solved is to provide a kind of tunneling field-effect transistor and forming method thereof, to improve tunnelling effect
The ON state current of transistor is answered, and subthreshold swing is reached corresponding demand, the performance of tunneling field-effect transistor is improved.
To solve the above problems, the present invention provides a kind of tunneling field-effect transistor, including：
Semiconductor substrate is provided；
The first semiconductor layer of the first doping type is formed on the semiconductor substrate；
The second semiconductor layer is formed on first semiconductor layer；
The 3rd semiconductor layer of the second doping type is formed on second semiconductor layer；
The 3rd semiconductor layer is etched until forming the second doped region；
Second semiconductor layer is etched until forming the first channel region；
First semiconductor layer described in etching part is until form the first doped region, and formed around the described first doping simultaneously
The ring-shaped groove in area；
In the bottom of the ring-shaped groove and the side shape of first doped region, the first channel region and the second doped region
Into the second channel region；
Gate dielectric layer is formed on the surface of second channel region；
Fill the ring-shaped groove formation grid.
Optionally, the thickness range of first channel region isThe thickness range of second channel region
For
Optionally, the doping concentration scope of first semiconductor layer is 1E19atom/cm3~1E21atom/cm3, it is described
The doping concentration scope of 3rd semiconductor layer is 1E19atom/cm3~1E21atom/cm3。
Optionally, the thickness range of first semiconductor layer isThe thickness of 3rd semiconductor layer
Spending scope is
Optionally, the material of first channel region includes silicon, germanium, SiGe or indium arsenide, second channel region
Material include silicon, germanium, SiGe or indium arsenide.
Optionally, the thickness range of the grid is
Optionally, the 3rd semiconductor layer is etched until forming the process of second doped region includes：
Pad oxide is formed on the 3rd semiconductor layer；
Cap layer is formed on the pad oxide；
Mask layer is formed on the cap layer；
Using the mask layer as mask, the cap layer, pad oxide and the 3rd semiconductor layer are etched.
Optionally, the process that the filling ring-shaped groove forms the grid includes：
The ring-shaped groove is filled using gate material layer and the cap layer is covered；
Planarization is carried out to the gate material layer until the exposure cap layer surface；
Etch-back is carried out to the gate material layer after planarization and forms the grid.
Optionally, the thickness range of the pad oxide isThe thickness range of the cap layer is
To solve the above problems, present invention also offers a kind of tunneling field-effect transistor, including：
Semiconductor substrate；
The first semiconductor layer in the Semiconductor substrate, first semiconductor layer has the first doping type；
Ring-shaped groove in first semiconductor layer；
On first semiconductor layer and by the first circular doped region of the ring-shaped groove, first doped region
With the first doping type；
The first channel region on first doped region；
The second doped region on first channel region, second doped region has the second doping type；
Positioned at second doped region, the first channel region and the first doped region side and the ring-shaped groove bottom second
Channel region；
Grid in the ring-shaped groove；
Gate dielectric layer between second channel region and the grid.
Optionally, the thickness range of first channel region isThe thickness range of second channel region
For
Optionally, the doping concentration scope of first doped region is 1E19atom/cm3~1E21atom/cm3, described
The doping concentration scope of two doped regions is 1E19atom/cm3~1E21atom/cm3。
Optionally, the thickness range of first doped region isThe thickness range of second doped region
For
Optionally, the material of first channel region includes silicon, germanium, SiGe or indium arsenide, second channel region
Material include silicon, germanium, SiGe or indium arsenide.
Optionally, the thickness range of the grid is
Compared with prior art, technical scheme has advantages below：
In technical scheme, the stacked structure of the first doped region, the first channel region and the second doped region, institute are formed
It is respectively one of source area and drain region to state the first doped region and the second doped region, and is formed around the stacked structure
The second channel region, then proceed to the second channel region surface formed gate dielectric layer, formed on gate dielectric layer surface around grid be situated between
The grid of matter layer, because the second channel region length is around the first doped region, the first channel region and the second doped region, its length is notable
Increase, therefore the tunneling path of transistor is added, and because the first doped region and the first ditch is completely covered in the second channel region
The side in road area, and the surface of the second doped region is at least covered, therefore, the area of the second channel region is larger, adds tunnel
Area is worn, in the case where tunneling path and tunnelling area all increase, the performance of tunneling field-effect transistor is improved.
Further, the thickness range of the second semiconductor layer isIf the second semiconductor layer is too thick, after
Far apart, i.e., channel length is too big, influences the performance of transistor for continuous the first doped region formed and the second doped region.Equally
, if the second semiconductor layer is too thin, the first doped region and the second doped region are too near apart, under the transistor performance being subsequently formed
Drop, therefore, be by the thickness range control of the second semiconductor layer
Further, the doping concentration scope of the first semiconductor layer is 1E19atom/cm3~1E21atom/cm3If, doping
Concentration is too low, then the first semiconductor layer resistance is too big, and the transistor performance of formation declines, if doping concentration is too high, and first
Foreign atom in semiconductor layer can be diffused into other structures layer, and the performance equally to transistor is adversely affected；3rd
The doping concentration scope of semiconductor layer is 1E19atom/cm3~1E21atom/cm3Led if doping concentration is too low, the 3rd half
Body layer resistance is too big, and the transistor performance of formation declines, if doping concentration is too high, the foreign atom in the 3rd semiconductor layer
It can be diffused into other structures layer, the performance equally to transistor is adversely affected.
Further, the thickness range of the 3rd semiconductor layer isBecause the 3rd semiconductor layer is subsequently used for shape
Into the second doped region, and the second doped region surface usually requires to form metal silicide, to reduce contact resistance, forms metallic silicon
Compound will consume certain silicon, therefore the thickness of the 3rd semiconductor layer is usually requiredMore than, still, lead when the 3rd half
The thickness of body layer is more thanWhen, the resistance of whole 3rd semiconductor layer can increase.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing tunneling field-effect transistor；
Each step of forming method for the tunneling field-effect transistor that Fig. 2 to Figure 11 is provided by the embodiment of the present invention is corresponding
Structural representation.
Embodiment
Existing tunneling field-effect transistor is unable to reach high ON state current and low sub-threshold slope, and tunneling path
（tunneling path）With tunnelling area（tunneling area）It is the most important of decision tunneling field-effect transistor performance
Factor, longer tunneling path and larger tunnelling area are favorably improved tunneling field-effect transistor performance.
Have together therefore, the present invention is provided in a kind of new tunneling field-effect transistor, the tunneling field-effect transistor
When around the first doped region, the first channel region and the second doped region the second channel region, because the second channel region length significantly increases
Plus, therefore the tunneling path of transistor is added, and because the first doped region and the first raceway groove is completely covered in the second channel region
The side in area, and the surface of the second doped region is at least covered, therefore, the area of the second channel region is larger, adds tunnelling
Area, in the case where tunneling path and tunnelling area all increase, the performance of tunneling field-effect transistor is improved.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of tunneling field-effect transistor, incorporated by reference to referring to figs. 2 to Figure 11.
Refer to Fig. 2, there is provided Semiconductor substrate 200.
In the present embodiment, Semiconductor substrate 200 can be any suitable semi-conducting material, be specifically as follows silicon, germanium, germanium
Silicon, carborundum, GaAs, indium arsenide or indium phosphide etc., Semiconductor substrate 200 can also include epitaxial layer, for example, can be exhausted
Silicon (SOI), germanium on insulator (GeOI) etc. on edge body.Semiconductor substrate 200 can also be lightly doped.If Semiconductor substrate
200 is are lightly doped Semiconductor substrate 200, and the doping type of Semiconductor substrate 200 is identical with drain region doping type.
Please continue to refer to Fig. 2, the first semiconductor layer 210a of the first doping type is formed on semiconductor substrate 200.
In the present embodiment, when the material of Semiconductor substrate 200 is silicon, the first semiconductor layer 210a material is preferably
Silicon, now, equally can form the first semiconductor layer 210a on semiconductor substrate 200, so that one from epitaxial growth method
Aspect make it that the interface between the first semiconductor layer 210a and Semiconductor substrate 200 is smooth, on the other hand makes the first semiconductor layer
The lattice of silicon is neatly intact in 210a.
First doped region 210b both can be source area or drain region, in order to ensure follow-up first doped region
210b can realize corresponding effect, particularly ensure follow-up first doped region 210b can by etch it is remaining after the first half
Conductor layer 210a is electrically connected with other structures, and the first semiconductor layer 210a of the present embodiment setting thickness range is
In the present embodiment, the first semiconductor layer 210a is adulterated, first doping type can for p-type or
N-type, for convenience of description, the follow-up all steps of the present embodiment will all be described by N-type of the first doping type, the first doping
Type is that the embodiment of p-type is considered as the equivalent substitution for the embodiment that the first doping type is N-type.
In the present embodiment, when carrying out n-type doping to the first semiconductor layer 210a, it can be adulterated by the trap in traditional handicraft
Realize, what is used can be phosphonium ion, arsenic ion or antimony ion, and it is possible to carry out high annealing after doping.
In the present embodiment, the first semiconductor layer 210a doping concentration scope is 1E19atom/cm3~1E21atom/cm3,
If doping concentration is too low, the first semiconductor layer 210a resistance is too big, and the transistor performance of formation declines, if doping concentration
Too high, then the foreign atom in the first semiconductor layer 210a can be diffused into other structures layer, and the performance equally to transistor is made
Into adverse effect.
Please continue to refer to Fig. 2, the second semiconductor layer 220a is formed on the first semiconductor layer 210a.
In the present embodiment, the second semiconductor layer 220a is intrinsic semiconductor layer, therefore, it is not doped.
In the present embodiment, the second semiconductor layer 220a thickness range isIf the second semiconductor layer
220a is too thick, then far apart, i.e., channel length is too big, shadow by the first doped region 210b and the second doped region 230b being subsequently formed
Ring the performance of transistor.Likewise, if the second semiconductor layer 220a were too thin, the first doped region 210b and the second doped region 230b
At a distance of too near, the transistor performance being subsequently formed declines, therefore, and the present embodiment is by the second semiconductor layer 220a thickness range control
It is made as
In the present embodiment, the second semiconductor layer 220a material can be silicon, germanium, SiGe or indium arsenide, can also
It is combinations thereof.When the first semiconductor layer 210a material is silicon, the second semiconductor layer 220a material is preferably silicon,
Now, equally the second semiconductor layer 220a can be formed on the first semiconductor layer 210a from epitaxial growth method, so that one
Aspect make it that the interface between the first semiconductor layer 210a and the second semiconductor layer 220a is smooth, on the other hand makes the second semiconductor
The lattice of silicon is neatly intact in layer 220a.
Please continue to refer to Fig. 2, the 3rd semiconductor layer 230a of the second doping type is formed on the second semiconductor layer 220a.
In the present embodiment, the 3rd semiconductor layer 230a material equally can be silicon, germanium, SiGe or indium arsenide,
It can be combinations thereof.When the second semiconductor layer 220a material is silicon, the 3rd semiconductor layer 230a material is preferable
For silicon, now, equally the 3rd semiconductor layer 230a can be formed on the second semiconductor layer 220a from epitaxial growth method, from
And on the one hand make it that the interface between the 3rd semiconductor layer 230a and the second semiconductor layer 220a is smooth, on the other hand makes the 3rd half
The lattice of silicon is neatly intact in conductor layer 230a.
In the present embodiment, when carrying out p-type doping to the 3rd semiconductor layer 230a, the trap in traditional handicraft again may be by
Doping realizes that what is used can be boron ion, fluorination boron ion or indium ion, be moved back and it is possible to carry out high temperature after doping
Fire.
In the present embodiment, the 3rd semiconductor layer 230a doping concentration scope is 1E19atom/cm3~1E21atom/cm3,
If doping concentration is too low, the 3rd semiconductor layer 230a resistance is too big, and the transistor performance of formation declines, if doping concentration
Too high, then the foreign atom in the 3rd semiconductor layer 230a can be diffused into other structures layer, and the performance equally to transistor is made
Into adverse effect.
In the present embodiment, because the 3rd semiconductor layer 230a is subsequently used for being formed the second doped region, and the second doped region table
Face is usually required to form metal silicide, to reduce contact resistance, and certain silicon, therefore the 3rd will be consumed by forming metal silicide
Semiconductor layer 230a thickness is usually requiredMore than, still, when the 3rd semiconductor layer 230a thickness is more than
When, whole 3rd semiconductor layer 230a resistance can increase, therefore the present embodiment controls the 3rd semiconductor layer 230a thickness model
Enclose for
Please continue to refer to Fig. 3, the 3rd semiconductor layer 230a shown in etch figures(s) 2 is until form the second doped region 230b.
In the present embodiment, four steps can be included by forming the second doped region 230b detailed process.
First step, forms pad oxide 240a on the 3rd semiconductor layer 230a.
In the present embodiment, pad oxide 240a can as the cap layer 250a and the 3rd semiconductor layer 230a being subsequently formed it
Between stress release layer, pad oxide 240a material can be silica, and ald can be used in pad oxide 240a
(ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering or other suitable methods
Formed.
In the present embodiment, pad oxide 240a thickness range isIf pad oxide 240a is too thin,
The effect of release stress is then unable to reach, if pad oxide 240a is too thick, increases follow-up removal difficulty.
Second step, forms cap layer 250a on pad oxide 240a.
In the present embodiment, cap layer 250a can protect the 3rd semiconductor layer 230a, and can be in follow-up gate material layer
In 290a planarization processes, stop-layer is served as.Cap layer 250a material can be nitride, such as SiN, same to can be used
Ald, chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering or other suitable methods are formed.
In the present embodiment, cap layer 250a thickness range isIf cap layer 250a is too thick, meeting
Cause cap layer 250a too big to the 3rd semiconductor layer 230a stress, and if cap layer 250a is too thin, just can not be follow-up
Stop-layer is served as in planarization process.
Third step, mask layer is formed on cap layer 250a（It is not shown）.
In the present embodiment, in order that mask pattern layers, can form photoresist layer on mask layer, patterning is then utilized
Photoresist layer be mask, mask layer is etched.It should be noted that can also directly layer be used as mask with photoresist
Layer.
Four steps, using mask layer as mask, enters to cap layer 250a, pad oxide 240a and the 3rd semiconductor layer 230a
Row etching.
In the present embodiment, after cap layer 250a and pad oxide 240a, form remaining cap layer 250b and pad is aoxidized
Layer 240b.
In the present embodiment, specifically usable dry etching or wet etching are etched to the 3rd semiconductor layer 230a,
Until forming the second doped region 230b, then, mask layer can remove.
In the present embodiment, the description in face of the 3rd semiconductor layer 230a in the past is understood, the second doped region 230b thickness model
Enclose for
Please continue to refer to Fig. 3, the second semiconductor layer 220a of etching until forming the first channel region 220b.
In the present embodiment, the description in face of the second semiconductor layer 220a in the past is understood, the first channel region 220b thickness model
Enclose forAnd the first channel region 220b material can include silicon, germanium, SiGe or indium arsenide.
Please continue to refer to Fig. 3, etching part the first semiconductor layer 210a until forming the first doped region 210b, and shape simultaneously
Ring-shaped groove 260 of the cyclization around the first doped region 210b.
In the present embodiment, the first doped region 210b thickness is original first semiconductor layer 210a（As shown in Figure 2）Thickness
A part.Specifically, because the first semiconductor layer 210a thickness ranges areTherefore the first doped region
210b thickness may be selected to be in some cases
In the present embodiment, after the first doped region 210b is formed, a part of first semiconductor layer 210c, this portion there remains
The tie point for dividing the first semiconductor layer 210c that follow-up first doped region 210b and external circuit can be used as to connect（First semiconductor layer
Separate to show differentiation with dotted line between 210c and the first doped region 210b）.
It should be noted that above to the first semiconductor layer 210a, the second semiconductor layer 220a and the 3rd semiconductor layer
230a etching can be carried out step by step, can also be carried out in same step, this is not limited by the present invention.
Fig. 4 is the schematic top plan view of structure shown in Fig. 3, therefrom it can furthermore be seen that by after above step, this
Embodiment forms the stacked structure formed by the first doped region 210b, the first channel region 220b and the second doped region 230b, and
And this stacked structure is surround by ring-shaped groove 260, the bottom of ring-shaped groove 260 is remaining first semiconductor layer 210c.It is described
In stacked structure, the follow-up source area and drain region respectively as transistor of the first doped region 210b and the second doped region 230b
One of them, i.e., when using the first doped region 210b as source area, the second doped region 230b mixes as drain region when by second
When miscellaneous area 230b is as drain region, the first doped region 210b is used as source area.
Fig. 5 is refer to, in the bottom of ring-shaped groove 260 and the first doped region 210b, the first channel region 220b and second
Doped region 230b side forms the second channel region 270.
In the present embodiment, the second channel region 270 is mixed around the first doped region 210b, the first channel region 220b and second simultaneously
Miscellaneous area 230b, from fig. 5, it is seen that the second channel region 270 be completely covered the first doped region 210b, the first channel region 220b and
Second doped region 230b side, still, in follow-up etch-back process, the second doped region 230b side may have part sudden and violent
Expose.
In the present embodiment, the material of the second channel region 270 includes silicon, germanium, SiGe or indium arsenide, when above-mentioned the first half
When conductor layer 210a, the second semiconductor layer 220a and the 3rd semiconductor layer 230a are silicon materials, the material of the second channel region 270
Selection uses silicon materials, and using epitaxial growth regime the second channel region 270 of formation, so as to ensure that the second channel region 270 has
There is good lattice structure.
In the present embodiment, the thickness range of the second channel region 270 isIn fact, the second channel region 270
It is that as the region of main channel region, therefore its thickness determines the size of channel region in the transistor that the present embodiment is formed, because
This, the thickness of the second channel region 270 it is too big or it is too small will all influence the performance of transistor, the present embodiment is disposed at
Fig. 6 is the schematic top plan view of structure shown in Fig. 5, therefrom it can furthermore be seen that the second channel region 270 is around described
Stacked structure, and cover the bottom of ring-shaped groove 260.
Fig. 7 is refer to, gate dielectric layer 280 is formed on the surface of the second channel region 270.
In the present embodiment, gate dielectric layer 280 can include SiO2, high K medium material or other suitable materials, or these
The combination of material, gate electrode can be formed by one or more layers structure, when for high-k gate dielectric material, be specifically as follows
Any of HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON and HfTiON or several.
Fig. 8 to Figure 11 is refer to, the present embodiment subsequently continuously forms the filling formation grid 290b of ring-shaped groove 260, specifically
, three steps can be included by forming grid 290b.
First step, refer to Fig. 8, fills ring-shaped groove 260 using gate material layer 290a and covers cap layer 250b.
In the present embodiment, gate material layer 290a material can for polysilicon, metal material, metal material compound or its
His suitable material, or its combinations thereof, for example can be TaAlN, TiAlN, MoAlN, AlNx, TaN, TiN, MoN, Mo and
Any of W or several.
Second step, refer to Fig. 9, carry out planarization to gate material layer 290a until exposure cap layer 250b surfaces.
In the present embodiment, cmp can be used（CMP）Method is planarized, and cap layer 250b mentioned above can
Stop-layer during as planarization, therefore, stops planarization when being planarized to exposed cap layer 250b surfaces.
Third step, please continue to refer to Fig. 9, etch-back formation grid is carried out to the gate material layer 290a after planarization
290b。
In the present embodiment, grid 290b filling ring-shaped grooves 260 are so as to around gate dielectric layer 280.Grid 290b thickness
Range-controllable system existsSo as to which the switching for the raceway groove for ensureing grid 290b is acted on.
Figure 10 is refer to, after etch-back formation grid 290b, the present embodiment carries out cap layer 250b and pad oxide
240b removal, so as to expose the second doped region 230b surface.
Figure 11 is the schematic top plan view of structure shown in Figure 10, therefrom it can furthermore be seen that grid 290b is around gate medium
Layer 280, gate dielectric layer 280 is around the second channel region 270, and the second channel region 270, can with reference to Figure 10 around the second doped region 230b
Know, the second channel region 270 is simultaneously also around the first doped region 210b and the first channel region 220b.
It can further be seen that in the present embodiment, the second doped region 230b vertical view figure is rectangle, still from Figure 11,
In other embodiments of the invention, the second doped region 230b vertical view figure can be square, five sides or hexagon etc.
Other polygons or circular or ellipse, can also be irregular figure, this is not limited by the present invention.
It should be noted that the present embodiment subsequently can form Ohmic contact on the second doped region 230b and grid 290b
Area, the ohmic contact regions can be made up of metal silicide layer.
It should be noted that the present embodiment can subsequently be etched to exposure remaining the first half and lead by etching technics
Body layer 210c, and fill corresponding conductive material and be connected to the first semiconductor layer 210c, so that the first doped region 210b passes through
First semiconductor layer 210c connection external circuits.
In the tunneling field-effect transistor of the forming method formation provided by the present embodiment, with the second channel region 270,
Because the second channel region 270 is simultaneously around the first doped region 210b, the first channel region 220b and the second doped region 230b, its length
Dramatically increase, therefore add the tunneling path of transistor, and the second channel region 270 be completely covered the first doped region 210b and
First channel region 220b side, and the second doped region 230b surface is at least covered, therefore, the second channel region 270
Area is larger, adds tunnelling area, in the case where tunneling path and tunnelling area all increase, tunneling field-effect transistor
Performance is improved.
The embodiment of the present invention additionally provides a kind of tunneling field-effect transistor, incorporated by reference to reference to Figure 10 and Figure 11.
The tunneling field-effect transistor includes Semiconductor substrate 200.The first semiconductor in Semiconductor substrate 200
Layer 210c, the first semiconductor layer 210c have the first doping type.Ring-shaped groove 260 in the first semiconductor layer 210c.
Have on the first semiconductor layer 210c and by the first circular doped region 210b of ring-shaped groove 260, the first doped region 210b
First doping type.The first channel region 220b on the first doped region 210b.
The second doped region 230b, the second doped region 230b on the first channel region 220b has the second doping type.
Positioned at the second doped region 230b, the first channel region 220b and the first doped region 210b side and the bottom of ring-shaped groove 260 second
Channel region 270.Grid 290b in ring-shaped groove 260.Gate medium between the second channel region 270 and grid 290b
Layer 280.
In the present embodiment, the first doped region 210b doping concentration may range from 1E19atom/cm3~1E21atom/
cm3, the second doped region 230b doping concentration may range from 1E19atom/cm3~1E21atom/cm3。
In the present embodiment, the first doped region 210b thickness range can beSecond doped region 230b's
Thickness range isIn the present embodiment, the first channel region 220b material can include silicon, germanium, SiGe or
Indium arsenide, the material of the second channel region 270 can include silicon, germanium, SiGe or indium arsenide.In the present embodiment, grid 290b
Thickness range can be
The tunneling field-effect transistor that the present embodiment is provided can be formed by the forming method of above-described embodiment, therefore,
The structure and property of tunneling field-effect transistor each several part refer to above example corresponding contents.
It should be noted that in other embodiments of the invention, it would however also be possible to employ other methods form the tunnelling
Effect transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (15)
1. a kind of forming method of tunneling field-effect transistor, it is characterised in that including：
Semiconductor substrate is provided；
The first semiconductor layer of the first doping type is formed on the semiconductor substrate；
The second semiconductor layer is formed on first semiconductor layer；
The 3rd semiconductor layer of the second doping type is formed on second semiconductor layer；
The 3rd semiconductor layer is etched until forming the second doped region；
Second semiconductor layer is etched until forming the first channel region；
First semiconductor layer described in etching part is until form the first doped region, and formed around first doped region simultaneously
Ring-shaped groove；
The is formed in the bottom of the ring-shaped groove and the side of first doped region, the first channel region and the second doped region
Two channel regions；
Gate dielectric layer is formed on the surface of second channel region；
Fill the ring-shaped groove formation grid.
2. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that first channel region
Thickness range isThe thickness range of second channel region is
3. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that first semiconductor layer
Doping concentration scope be 1E19atom/cm3~1E21atom/cm3, the doping concentration scope of the 3rd semiconductor layer is
1E19atom/cm3~1E21atom/cm3。
4. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that first semiconductor layer
Thickness range beThe thickness range of 3rd semiconductor layer is
5. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that first channel region
Material includes silicon, germanium, SiGe or indium arsenide, and the material of second channel region includes silicon, germanium, SiGe or arsenic
Indium.
6. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that the thickness model of the grid
Enclose for
7. the forming method of tunneling field-effect transistor as claimed in claim 1, it is characterised in that etching the described 3rd half is led
Body layer is until forming the process of second doped region includes：
Pad oxide is formed on the 3rd semiconductor layer；
Cap layer is formed on the pad oxide；
Mask layer is formed on the cap layer；
Using the mask layer as mask, the cap layer, pad oxide and the 3rd semiconductor layer are etched.
8. the forming method of tunneling field-effect transistor as claimed in claim 7, it is characterised in that the filling ring-shaped groove
Forming the process of the grid includes：
The ring-shaped groove is filled using gate material layer and the cap layer is covered；
Planarization is carried out to the gate material layer until the exposure cap layer surface；
Etch-back is carried out to the gate material layer after planarization and forms the grid.
9. the forming method of tunneling field-effect transistor as claimed in claim 7, it is characterised in that the thickness of the pad oxide
Spending scope isThe thickness range of the cap layer is
10. a kind of tunneling field-effect transistor, it is characterised in that including：
Semiconductor substrate；
The first semiconductor layer in the Semiconductor substrate, first semiconductor layer has the first doping type；
Ring-shaped groove in first semiconductor layer；
On first semiconductor layer and by the first circular doped region of the ring-shaped groove, first doped region has
First doping type；
The first channel region on first doped region；
The second doped region on first channel region, second doped region has the second doping type；
Positioned at the second raceway groove of second doped region, the first channel region and the first doped region side and the ring-shaped groove bottom
Area；
Grid in the ring-shaped groove；
Gate dielectric layer between second channel region and the grid.
11. tunneling field-effect transistor as claimed in claim 10, it is characterised in that the thickness range of first channel region
ForThe thickness range of second channel region is
12. tunneling field-effect transistor as claimed in claim 10, it is characterised in that the doping concentration of first doped region
Scope is 1E19atom/cm3~1E21atom/cm3, the doping concentration scope of second doped region is 1E19atom/cm3~
1E21atom/cm3。
13. tunneling field-effect transistor as claimed in claim 10, it is characterised in that the thickness range of first doped region
ForThe thickness range of second doped region is
14. tunneling field-effect transistor as claimed in claim 10, it is characterised in that the material of first channel region includes
Silicon, germanium, SiGe or indium arsenide, the material of second channel region include silicon, germanium, SiGe or indium arsenide.
15. tunneling field-effect transistor as claimed in claim 10, it is characterised in that the thickness range of the grid is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310669773.4A CN104701374B (en) | 2013-12-10 | 2013-12-10 | Tunneling field-effect transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310669773.4A CN104701374B (en) | 2013-12-10 | 2013-12-10 | Tunneling field-effect transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104701374A CN104701374A (en) | 2015-06-10 |
| CN104701374B true CN104701374B (en) | 2017-11-03 |
Family
ID=53348304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310669773.4A Active CN104701374B (en) | 2013-12-10 | 2013-12-10 | Tunneling field-effect transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104701374B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779418B (en) * | 2014-02-08 | 2016-08-31 | 华为技术有限公司 | A kind of tunneling field-effect transistor and preparation method thereof |
| WO2017088186A1 (en) * | 2015-11-27 | 2017-06-01 | 华为技术有限公司 | Tunneling field-effect transistor and manufacturing method therefor |
| US10008583B1 (en) * | 2017-05-08 | 2018-06-26 | Samsung Electronics Co., Ltd. | Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272933A (en) * | 2008-12-30 | 2011-12-07 | 英特尔公司 | Tunnel field effect transistor and method of manufacturing same |
| CN103151391A (en) * | 2013-03-18 | 2013-06-12 | 北京大学 | Short gate tunneling field effect transistor of vertical non-uniform doping channel and preparation method thereof |
| WO2013123287A1 (en) * | 2012-02-15 | 2013-08-22 | Steven May | Charge ordered vertical transistors |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070228491A1 (en) * | 2006-04-04 | 2007-10-04 | Micron Technology, Inc. | Tunneling transistor with sublithographic channel |
| EP2378557B1 (en) * | 2010-04-19 | 2015-12-23 | Imec | Method of manufacturing a vertical TFET |
-
2013
- 2013-12-10 CN CN201310669773.4A patent/CN104701374B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272933A (en) * | 2008-12-30 | 2011-12-07 | 英特尔公司 | Tunnel field effect transistor and method of manufacturing same |
| WO2013123287A1 (en) * | 2012-02-15 | 2013-08-22 | Steven May | Charge ordered vertical transistors |
| CN103151391A (en) * | 2013-03-18 | 2013-06-12 | 北京大学 | Short gate tunneling field effect transistor of vertical non-uniform doping channel and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104701374A (en) | 2015-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10164068B2 (en) | FinFET structure and method for fabricating the same | |
| US11894448B2 (en) | Structure and method for vertical tunneling field effect transistor with leveled source and drain | |
| US9397226B2 (en) | Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts | |
| US7288802B2 (en) | Virtual body-contacted trigate | |
| US9117907B2 (en) | Semiconductor device | |
| US9070714B1 (en) | Strapped dual-gate VDMOS device | |
| US9406669B2 (en) | Method and structure for vertical tunneling field effect transistor and planar devices | |
| TWI696242B (en) | Method for forming a thin semiconductor-on-insulator (soi) substrate | |
| US10090403B2 (en) | Power semiconductor device with semiconductor pillars | |
| CN103579004B (en) | Finfet and manufacturing method thereof | |
| CN111755512B (en) | Semiconductor device and preparation method thereof | |
| TW201729347A (en) | Semiconductor device | |
| JP2008028263A (en) | Semiconductor device | |
| US9812558B2 (en) | Three-dimensional transistor and methods of manufacturing thereof | |
| CN104701374B (en) | Tunneling field-effect transistor and forming method thereof | |
| CN104269438A (en) | Junction-free field effect transistor and method for manufacturing junction-free field effect transistor | |
| WO2016119682A1 (en) | Tunneling field effect transistor and preparation method thereof | |
| KR101868634B1 (en) | Method for manufacturing the semiconductor device | |
| US20180082885A1 (en) | Self-aligned airgaps with conductive lines and vias | |
| CN106548983B (en) | Semiconductor devices and forming method thereof | |
| TWI517406B (en) | Semiconductor device and method for manufacturing the same | |
| CN114068706B (en) | Semiconductor structure and forming method thereof | |
| US20230402520A1 (en) | Staircase stacked field effect transistor | |
| CN112802753A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |