WO2017088186A1 - Tunneling field-effect transistor and manufacturing method therefor - Google Patents

Tunneling field-effect transistor and manufacturing method therefor Download PDF

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Publication number
WO2017088186A1
WO2017088186A1 PCT/CN2015/095847 CN2015095847W WO2017088186A1 WO 2017088186 A1 WO2017088186 A1 WO 2017088186A1 CN 2015095847 W CN2015095847 W CN 2015095847W WO 2017088186 A1 WO2017088186 A1 WO 2017088186A1
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layer
source region
insulating layer
region
gate
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PCT/CN2015/095847
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French (fr)
Chinese (zh)
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赵静
张臣雄
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华为技术有限公司
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Priority to CN201580083855.8A priority Critical patent/CN108140673B/en
Priority to PCT/CN2015/095847 priority patent/WO2017088186A1/en
Publication of WO2017088186A1 publication Critical patent/WO2017088186A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • Embodiments of the present invention relate to communication technologies, and in particular, to a tunnel field effect transistor (TFET) and a method of fabricating the same.
  • TFET tunnel field effect transistor
  • the size of semiconductor devices will continue to shrink, and the manufacturing cost of devices will increase, especially in photolithography.
  • Another aspect is the power consumption problem.
  • the metal oxide semiconductor field effect transistor (English name: Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short) has been unable to meet the requirements of small-sized devices. It is required because it is limited by the carrier Boltzmann distribution at room temperature, ie kT/q. Therefore, at room temperature, the subthreshold swing (English full name: Subthreshold swing, referred to as: SS) can not be less than 60mV / decade, that is, in the case of small size devices, the power consumption is higher.
  • SS Subthreshold swing
  • TFET is an excellent choice for very low power applications because the SS value of the TFET is not limited to kT/q at room temperature, ie the SS value is less than 60mV/decade, and is compatible with CMOS processes and process scalability, but The device size is reduced to achieve high integration density, which causes a short channel effect (SCE), which increases the off current.
  • SCE short channel effect
  • FIG. 1 is a schematic view showing the structure of a TFET provided by the patent of the International Publication No. WO 2012/152762 A1, the disclosure of which is incorporated herein by reference.
  • Three electrodes of the pole and the gate, 12 indicates the source region of the TFET
  • 14 indicates the drain region of the TFET
  • 13 is the portion under the source region, is undoped silicon, and serves as a channel
  • 13a and 13 are integrated Formed, but 13a is a portion on both sides of the source region, also undoped silicon, as an epitaxial layer
  • 15 is a gate dielectric layer
  • 16 is a gate region material
  • 20 is an insulating layer
  • 42 is a sidewall of the TFET.
  • the above TFET structure belongs to a linear tunneling structure, and the source region 12 is inside the 13 region. Under the action of the gate electric field, a tunneling pn junction is formed with the 13a region as an epitaxial layer on both sides of the source region 12, when the gate 19 When the voltage is increased to a certain value, carriers are tunneled.
  • the channel region between the source region and the drain region must be sufficiently wide to serve as a barrier layer for tunneling generated by the non-gate control, but when the channel region is set wider, the resistance is increased. This results in a larger subthreshold swing of the TFET, higher power consumption, and increased device size.
  • Embodiments of the present invention provide a tunneling field effect transistor and a method of fabricating the same, which are used to solve the problem that the channel region is wider and the resistance is increased, so that the subthreshold swing of the TFET is larger, the power consumption is higher, and the device size is increased. The problem.
  • a first aspect of the present invention provides a tunneling field effect transistor, including:
  • a source region covering a portion of the surface of the substrate layer, the source region being in the shape of a cylinder;
  • drain region covering the surface of the first insulating layer away from the source region
  • a second insulating layer overlying the substrate layer, located around the source region, and the second insulating layer is in contact with the source region;
  • An epitaxial layer covering the side of the source region, and the epitaxial layer is in contact with a surface of the second insulating layer away from the substrate layer;
  • a gate region covering a surface of the epitaxial layer away from the source region, the gate region including a plurality of surfaces, wherein two surfaces are in contact with the epitaxial layer and the second insulating layer, respectively;
  • the second insulating layer is used to isolate the gate region from the substrate layer; the first insulating layer and the epitaxial layer are used to isolate the drain region from the source region.
  • the source region of the tunneling field effect transistor described above may also be a nanowire structure, that is, similar In a cylindrical or elliptical column structure, if the source region is a nanowire structure, the epitaxial layer is surrounded by the source region, and the gate region is similar.
  • the tunneling field effect transistor provided by the scheme has the effect of the gate electric field on the surface of the source region by the epitaxial layer surrounding the source region, and the surface of the source region is affected by the gate electric field, and the electric field direction of the gate region and the carrier tunneling direction of the source region. Consistently, the tunneling probability is enhanced, the carrier inside the source region has no competition, the gate electric field force is enhanced, the epitaxial layer is completely depleted, the subthreshold swing of the device is reduced, the power consumption is reduced, and the structure can reduce the device. size.
  • the source region is an in-situ P++ doped semiconductor material
  • the semiconductor material is any one of silicon, germanium silicon, a group of four materials, and a tri-five material;
  • the concentration is 1e 18 to 1e 21 cm -3 .
  • the material of the substrate layer is any one of silicon, germanium, SOI, GeOI, and III-V compound materials.
  • the doping type of the substrate layer is consistent with the source region.
  • the semiconductor material used to form the source region may specifically be: if it is based on a silicon material TFET, P-type doping, the impurities may be B, Al, Ga, In, Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W, Pb, O, Fe; if it is N-type doping, the impurities may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag, Cd, Pt.
  • the impurities may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt; N-type doping It may be Li, Sb, P, As, S, Se, Te, Cu, Au, Ag.
  • the drain region is an in situ N++ doped semiconductor material.
  • the material of the first insulating layer is SiO 2 , silicon nitride or silicon oxynitride; the material of the second insulating layer is SiO 2 , silicon nitride or silicon oxynitride .
  • the first insulating layer is mainly an isolation as a source region and a drain region, preventing the tunneling field effect transistor from leaking current in an off state.
  • the height of the gate region is less than or equal to the height of the source region.
  • the gate region includes a gate dielectric layer and a gate; and the gate dielectric layer is made of SiO2 and/or HfO2.
  • the height of the gate region and the source region are the same in order to better control the source region carriers, and avoid a point tunneling or line tunneling mixing mechanism due to the source region being higher than the gate region, thereby affecting device characteristics. .
  • a second aspect of the present invention provides a method of fabricating a tunneling field effect transistor, including:
  • the source region is in a rectangular parallelepiped shape
  • a drain region is formed on the first insulating layer and the upper portion of the epitaxial layer.
  • the source region of the tunneling field effect transistor may also be a nanowire structure, that is, similar to a cylindrical or elliptical column structure. If the source region is a nanowire structure, the epitaxial layer is surrounded by the source region. The gate region is also similarly surrounded outside the epitaxial layer. If the source region is a rectangular parallelepiped structure, the second insulating layer may be formed before the source region or after the source region is formed. If the source region is a nanowire structure, the second insulating layer may only be deposited and patterned before the source region is formed. Formed.
  • the tunneling field effect transistor formed by the method surrounds the source region by forming an epitaxial layer, and the gate region is formed on or around the source region, and the surface of the source region is subjected to the gate electric field, and the electric field direction and the source region of the gate region are carried.
  • the tunneling direction of the carriers is uniform, the tunneling probability is enhanced, the carriers in the source region have no competition relationship, the gate electric field force is enhanced, the epitaxial layer is completely depleted, the subthreshold swing of the device is reduced, and the power consumption is reduced.
  • the structure can reduce the device size.
  • the opening a hole in the intermediate portion of the second insulating layer to expose the substrate layer, and forming a source region on the substrate layer of the opening region, comprising:
  • a source region composed of an in situ P++ doped semiconductor material is formed on the substrate layer of the open region of the second insulating layer.
  • a substrate layer is provided which is made of any one of silicon, germanium, SOI, GeOI, and III-V compound materials, and a second insulating layer is formed on the substrate layer by a chemical vapor deposition process or an oxidation process. Additionally, the second insulating layer may be before or after the source region is formed. If the source region is a nanowire structure, The second insulating layer is then deposited and patterned prior to formation of the source region. The second insulating layer mainly serves as a spacer substrate layer and other materials subsequently formed on the second insulating layer.
  • the forming the first insulating layer on the source region away from the other end of the substrate layer comprises:
  • Forming an epitaxial layer on a side of the source region including:
  • a semiconductor layer composed of an intrinsically doped semiconductor is deposited on a side of the source region, and the semiconductor layer is etched to expose the first insulating layer, and the remaining portion of the semiconductor layer is used as the epitaxial layer.
  • an insulating layer is deposited on the outside of the source region and etched, leaving only the portion at the top of the source region as the first insulating layer, as isolation between the source region and the drain region, preventing leakage current in the off state.
  • the gate region includes a dielectric layer and a gate; and forming a gate region on an outer side of the first insulating layer and the epitaxial layer comprises:
  • the present embodiment is not limited to the HfO 2 material, and other high K materials and/or SiO 2 may be used to form the dielectric layer.
  • the forming a drain region on an upper portion of the first insulating layer and the epitaxial layer comprises:
  • the height of the gate region is less than or equal to the height of the source region, and it is preferable that the height of the gate region and the height of the source region are consistent, in order to well control the source region carriers. Avoid The source-free zone is higher or lower than the gate region, and a point tunneling and line tunneling mixing mechanism is generated, which affects the characteristics of the device.
  • the epitaxial layer is disposed on both sides of the source region, or the epitaxial layer surrounds the source region, and the gate region acts on both sides of the source region, that is, the source
  • the region is subjected to the gate electric field, and the gate electric field direction is consistent with the source region carrier tunneling direction, and the tunneling probability is enhanced.
  • the source region is entirely located between the gate regions, and the tunneling area is increased.
  • Figure 1 is a schematic view showing the structure of a TFET provided by the patent of International Publication No. WO 2012/152762 A1;
  • FIG. 2 is a perspective view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 3 is a front view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 5 is a top view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing a second embodiment of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present disclosure
  • FIGS. 8(a) to 8(k) are schematic diagrams illustrating a manufacturing process of an example of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • the invention provides a vertical structure TFET which can not only reduce the device area and the gate control capability, but also can effectively reduce the SS value of the device and has a small size.
  • a vertical structure TFET which can not only reduce the device area and the gate control capability, but also can effectively reduce the SS value of the device and has a small size.
  • FIG. 2 is a perspective view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 3 is a front view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention
  • a cross-sectional view of a tunneling field effect transistor embodiment is shown in FIG. 5
  • FIG. 5 is a top view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention.
  • the tunneling field effect transistor 30 includes:
  • a source region 32 covering a portion of the surface of the substrate layer 31, the source region 32 being in the shape of a cylinder;
  • a first insulating layer 33 covering the one end surface of the source region 32 away from the substrate layer 31;
  • drain region 34 covering the surface of the first insulating layer 33 away from the source region 32;
  • a second insulating layer 35 covering the substrate layer 31, located around the source region 32, and the second insulating layer 35 is in contact with the source region 32;
  • Epitaxial layer 36, epitaxial layer 36 overlying the side of source region 32, and epitaxial layer 36 is in contact with the surface of second insulating layer 35 away from substrate layer 31;
  • a gate region 37 covering the surface of the epitaxial layer 36 away from the source region 32, the gate region 37 comprising a plurality of surfaces, wherein the two surfaces are in contact with the epitaxial layer 36 and the second insulating layer 35, respectively;
  • the second insulating layer 35 is used to isolate the gate region 37 from the substrate layer 31; the first insulating layer 33 and the epitaxial layer 36 are used to isolate the drain region 34 from the source region 32.
  • the material that the substrate layer 31 can be used in the specific implementation process includes any one of silicon, germanium, SOI, GeOI, III-V compound materials, and the like.
  • the substrate layer 31 may include two portions of intrinsic silicon 311 and buried oxide layer 312.
  • the source region 32 may be an in-situ P++ doped semiconductor material, and the semiconductor material may be any one of silicon, germanium silicon, a quadruplex material, and a tri-five material; the doping concentration may be 1e 18 to 1e 21 cm -3 .
  • the source region may be a square body or a nanowire structure, similar to the shape of a cylinder or an elliptical cylinder.
  • the second insulating layer 35 may be a whole, and the source region 32 is actually disposed on the substrate layer 31 through the upper notch of the second insulating layer 35.
  • the source region 32 is a square pillar, and the second insulation is The layer 35 has a corresponding square notch; the source region 32 is a circular cylinder or an elliptical cylinder, and the second insulating layer 35 has a corresponding circular or elliptical notch.
  • the second insulating layer 35 may also be a plurality of separate portions, and the gate region 37 and the substrate layer 31 can be isolated, which is not limited in the present invention.
  • the doping type of the substrate layer 31 may be the same as that of the source region 32.
  • the semiconductor material used to form the source region 32 may specifically be: if it is based on a silicon material TFET, P-type doping, the impurity may be B, Al, Ga, In , Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W, Pb, O, Fe; if it is based on a silicon material TFET, N-type doping, the impurity may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag, Cd, Pt.
  • the impurities may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt;
  • the TFET of the material may be Li, Sb, P, As, S, Se, Te, Cu, Au, Ag.
  • the drain region 34 is an in situ N++ doped semiconductor material.
  • the material of the first insulating layer 33 is SiO 2 , silicon nitride or silicon oxynitride; the material of the second insulating layer 35 is SiO 2 , silicon nitride or silicon oxynitride.
  • the height of the gate region 37 is less than or equal to the height of the source region 32. More preferably, the gate region 37 and the source region 32 are disposed at the same height to better control the source region 32 carriers.
  • the gate region 37 includes a gate dielectric layer 371 and a gate 372; the material of the gate dielectric layer 371 is SiO2 and/or HfO2.
  • the working principle of the tunneling field effect transistor described above is that the gate 372 is positively biased, the source region 32 is grounded, and the drain region 34 is positively biased; under the action of the gate voltage, minority carriers in the source region 32 are sourced from the source region.
  • the valence band of 32 is tunneled into the bottom of the conduction band in the epitaxial layer 36 region to form a tunneling current, which is subjected to the voltage of the drain region 34 on both sides, and flows into the drain region 34 to form a leakage current.
  • FIG. 6 is a cross-sectional view of a second embodiment of the tunneling field effect transistor according to the embodiment of the present invention, as shown in FIG. Yes, the structure of the source region 32 can adopt a fin shape, which is equivalent to a trapezoid, that is, the source region 32 and the lining.
  • the surface area of the bottom layer 31 is larger than the surface area in contact with the first insulating layer 33, which can further improve the control of the source region 32 by the gate region 37, and other structures are the same as those shown in Figs. 2-5.
  • the tunneling field effect transistor provided by the various embodiments of the present invention has a structure in which an epitaxial layer 36 region surrounds the source region 32, and a gate electrode acts on both sides of the source region 32, that is, the surface of the source region 32 is subjected to a gate electric field, and the gate electrode
  • the direction of the electric field is consistent with the carrier tunneling direction of the source region 32, and the tunneling probability is enhanced, and the source region 32 is entirely located between the gate regions 37, so the tunneling area is increased, and the source region 32 is internally compared with the prior art.
  • the carrier has no competing relationship, and enhances the force of the gate electric field, causing the epitaxial layer 36 to be completely depleted and changing the drain current, that is, the drain current can be increased under the same gate boost, that is, Under the condition that the voltage applied on the device is constant, the subthreshold swing of the device is effectively reduced, and the subthreshold characteristic of the device is enhanced. And according to the above implementation, the size of the device is not increased.
  • FIG. 7 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 7, the specific steps of the method for manufacturing the tunneling field effect transistor include:
  • the substrate layer is formed by processing a suitable substrate material in a desired shape.
  • a second insulating layer is deposited on the formed substrate layer, and the material may be SiO2 or silicon nitride, etc., and may be performed by a chemical vapor deposition process or an oxidation process, and the insulating layer 2 is used as a substrate. And an isolation layer of material subsequently formed on the insulating layer.
  • S103 opening a hole in the middle portion of the second insulating layer to expose the substrate layer, and forming a source region on the substrate layer of the open region.
  • the source region has a columnar shape such as a rectangular parallelepiped shape, a fin shape, or a cylindrical shape.
  • the source region is formed by: opening a hole in the middle portion of the second insulating layer by photolithography to expose the substrate layer; forming a semiconductor doped with P++ in situ on the substrate layer of the open region of the second insulating layer The source area of the material.
  • S104 forming a first insulating layer on the source region away from the other end of the substrate layer.
  • S105 forming an epitaxial layer on a side of the source region.
  • an insulating layer is formed outside the source region by using NOx, silicon nitride or silicon oxynitride, and etching the insulating layer only leaves a portion of the source region at the top of the end portion away from the substrate layer.
  • a first insulating layer; a semiconductor layer made of an intrinsically doped semiconductor is deposited on both sides of the source region, the etched semiconductor layer exposes the first insulating layer, and the remaining portion of the semiconductor layer is used as an epitaxial layer.
  • S106 forming a gate region on the outer side of the first insulating layer and the epitaxial layer.
  • the specific implementation is: depositing a dielectric layer on the outside of the first insulating layer and the epitaxial layer by using SiO 2 and/or HfO 2 materials, and depositing a gate on the outer side of the dielectric layer by using polysilicon or a metal material; etching the dielectric layer and a gate that exposes a first insulating layer on top of the first insulating layer.
  • the height of the gate region is less than or equal to the height of the source region, and more preferably, the height of the source region coincides with the height of the gate region.
  • S108 forming a drain region on the upper portion of the first insulating layer and the epitaxial layer.
  • an in-situ N++ doped semiconductor material is deposited on the first insulating layer and the epitaxial layer, and the semiconductor material is etched, leaving only the first insulating layer and a portion of the upper portion of the epitaxial layer as a drain region.
  • An optional method is that the height of the epitaxial layer is higher than that of the source region but lower than the first insulating layer.
  • the drain region formed after etching is U-shaped, and the periphery of the drain region is wrapped outside the first insulating layer and extended with the epitaxial layer. The layers are connected together.
  • the method further comprises: forming a tunneling field effect transistor by using silicon oxide, silicon nitride or a high dielectric constant dielectric deposition sidewall.
  • the manufacturing method of the tunneling field effect transistor provided in this embodiment, by forming a gate region on both sides of the source region, an epitaxial layer is formed between the source region and the gate dielectric layer of the gate region, and the gate electric field acts on the source region and The epitaxial layer, until the pn junction is depleted, reduces the gate voltage increment required to change the drain current, ie, effectively reduces the SS value of the device, and reduces the leakage current through the first insulating layer.
  • the above process is simple and compatible with CMOS processes.
  • FIG. 8(a) to FIG. 8(j) are examples of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • Step 1 Providing a substrate layer of a semiconductor.
  • the material of the underlayer may be silicon, germanium, SOI, GeOI, a III-V compound material or the like.
  • This example takes the silicon substrate layer 1 as an example, as shown in Fig. 8(a).
  • Step 2 Forming a second insulating layer on the above substrate layer.
  • a second insulating layer 2 is deposited, and the material is In the case of SiO2 or silicon nitride, a chemical vapor deposition process or an oxidation process may be employed.
  • the second insulating layer 2 serves as a spacer for the substrate and a material subsequently formed on the insulating layer.
  • Step 3 The second insulating layer 2 is patterned, and the second insulating layer 2 is opened to expose the substrate layer 1.
  • the second insulating layer 2 is patterned as shown in Fig. 8(c), and the intermediate layer exposes the substrate layer 1.
  • the layer is removed, and the exposed resistive layer 4 is removed, and the patterned hard mask layer 3 is patterned to form the second insulating layer 2.
  • Step 4 On a portion of the second insulating layer 2 where the substrate layer 1 is exposed, a source region of a vertical semiconductor material is formed.
  • the insulating layer may be before or after the source region; if the source region 5 is a nanowire structure, the insulating layer is deposited and patterned before the source region is formed.
  • the semiconductor material forming the source region may be silicon, germanium silicon, a group of four materials, a tri-five material, or the like; and the doping concentration is from 1e 18 to 1e 21 cm -3 .
  • the doping type of the substrate layer 1 is identical to the source region type.
  • the impurities may be B, Al, Ga, In, Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W , Pb, O, Fe; if it is N-type doping, the impurities may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag , Cd, Pt.
  • the P-type doping may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt;
  • the N-type doping may be Li , Sb, P, As, S, Se, Te, Cu, Au, Ag.
  • Step 5 deposit an insulating layer on the outer layer of the source region 5, and etch only the portion of the insulating layer at the top of the source region 5 as the first insulating layer 6.
  • a dielectric material insulating layer 6 is provided, which may be SiO2 or other dielectric material.
  • the insulating layer 6 is etched in the same manner as in step 3. Only the portion at the top of the source region remains as the first insulating layer 6.
  • the first insulating layer 6 serves as an isolation between the source region and the drain region to prevent leakage current in the off state.
  • the specific process is to form an insulating layer on the source region 5 composed of a semiconductor material in the insulating layer. Forming an isolation layer outside, patterning the isolation layer, leaving only the isolation layer on the top of the insulation layer, etching the insulation layers on both sides with the isolation layer as a mask, and removing the remaining isolation layer to form the above An insulating layer 6.
  • Step 6 Forming an epitaxial layer 7 on both sides of the source region 5.
  • the intrinsic (n-type) doped semiconductor layer 7 is deposited as shown in FIG. 8(g), the hard mask layer 8 is provided, and the hard mask layer 8 is patterned to expose the semiconductor layer 7 on the surface of the insulating layer 6, and the exposed semiconductor is etched away. Layer 7; and the remaining hard mask layer 8 is removed, and the remaining semiconductor layer 7 is used as the epitaxial layer 7.
  • a specific implementation provides a layer of the doped semiconductor layer on the outer side of the source region 5 and the first insulating layer 6, providing a hard mask layer, patterning a hard mask layer, exposing the top region of the semiconductor source region, and etching
  • the semiconductor layer is intrinsically doped at the top of the semiconductor source region, the mask layer is removed, and the remaining semiconductor layer is the epitaxial layer 7.
  • Step 8 A gate dielectric layer 9 is deposited on the outside of the epitaxial layer 7, and a gate material 10 is formed on the outside of the gate dielectric layer 9.
  • the gate dielectric layer 9 is deposited on the outside, and SiO2 or a high-k dielectric layer such as HfO2 or the like may be formed; the gate material 10 may be deposited, which may be polysilicon, metal or the like.
  • Step 8 Etching the gate dielectric layer 9 and the gate material 10.
  • the gate material 10 and the gate dielectric layer 9 are etched to expose the first insulating layer 6 at the top of the source region.
  • the height of the gate region is consistent with the height of the source region for good control of the source region carriers, because if the source region is higher or lower than the gate region, a point tunneling and line tunneling mixing mechanism is generated, which affects device characteristics.
  • Step 9 A drain region 12 is formed on the first insulating layer 6.
  • a low-k dielectric layer 11 is deposited, and patterned (using the process technology of method 3) to expose the first insulating layer 6, and the dielectric layer 11 around the first insulating layer 6 is higher than the first insulating layer.
  • Layer 6 a low-k dielectric layer 11 is deposited, and patterned (using the process technology of method 3) to expose the first insulating layer 6, and the dielectric layer 11 around the first insulating layer 6 is higher than the first insulating layer.
  • a drain region 12 is formed on the upper portion of the first insulating layer 6 by in-situ doping of an N++ type semiconductor layer. The excess semiconductor layer is etched, and the semiconductor layer on top of the insulating layer 6 is left as the drain region 12.
  • another dielectric material isolation is provided beside the gate region, the intermediate portion of the dielectric material isolation layer is patterned, the first insulating layer is exposed, and then the portion of the first insulating layer is exposed to form a semiconductor layer drain region, and then the drain region electrode is directly provided.
  • the drain region is connected, and the source region electrode direct source region is provided, and the gate electrode is directly connected to the gate layer of the gate region.
  • Step 10 Deposit the sidewalls, which can be silicon oxide, silicon nitride, high-k dielectric or other Edge material.
  • a metal contact or the like similar to a CMOS process is performed.
  • Co and TiN ion beam precipitation is performed on the surface, followed by rapid annealing process, then removing titanium nitride and cobalt, and finally depositing a passivation layer, opening contact holes, metallization, etc., forming Complete transistor).
  • the hard mask layer material may be a silicon oxide material or a silicon nitride or silicon oxynitride material.
  • the deposition process of the above steps can be realized by low pressure chemical vapor deposition (English name: Low Pressure Chemical Vapor Deposition, LPCVD for short) or physical vapor deposition (English full name: Physical Vapor Deposition, PVD for short); Molecular beam epitaxy, LPCVD, CVD, etc.).
  • the above process is a detailed process for fabricating the tunneling field effect transistor provided by the present invention.
  • the tunneling field effect transistor shown in FIG. 2-5 can be fabricated by the above method.
  • an alternative manufacturing scheme in which red is formed When the source region is structured, it can be formed into a fin shape (refer to the shape of the source region shown in FIG. 6), and the other configurations are the same as described above.
  • This will introduce the fin fabrication process of the Fin Field-Effect Transistor (FinFET) device, which can be a side wall transfer process or a photolithography process. Other processes are the same.
  • the control ability of the gate region to the source region can be further improved.
  • the manufacturing method of the tunneling field effect transistor provided in this embodiment is used to manufacture the tunneling field effect transistor described above, wherein the source region is located between the double gate regions, and the epitaxial layer is located between the source region and the gate dielectric layer, and the gate electric field acts.
  • the source region and the epitaxial layer the pn junction is depleted, and as the bias of the external gate is applied, the depletion region is gradually enlarged and completely depleted. Due to the existence of the depletion region, the multi-sub-motion is blocked, the minority carrier motion is active, and the TFET is the tunneling of the minority carrier, so the SS value is reduced, and the isolation of the first insulating layer effectively reduces the leakage current and improves Device performance.
  • the above manufacturing process is simple in technology, compatible with CMOS processes, and does not require complicated processes.
  • the source region structure in the device structure provided by the present invention can be used in any transistor structure based on the TFET tunneling mechanism to reduce the subthreshold swing, and is not limited to the tunneling field effect transistor of the present invention.

Abstract

Provided are a tunneling field-effect transistor and a manufacturing method therefor. A tunneling field-effect transistor (30) comprises: a substrate layer (31); a source region (32) partially covering the surface of the substrate layer (31); a first insulating layer (33) covering the end face of the source region (32) that is away from the substrate layer (31); a drain region (34) covering the surface of the first insulating layer (33) that is away from the source region (32); a second insulating layer (35) covering the portion of the substrate layer (31) that surrounds the source region (32); an epitaxial layer (36) covering a side surface of the source region (32) and contacting the surface of the second insulating layer (35) that is away from the substrate layer (31); and a gate region (37) covering the surface of the epitaxial layer (36) that is away from the source region (32) and contacting the epitaxial layer (36) and the second insulating layer (35) separately. The epitaxial layer (36) surrounds the source region (32), the gate region (37) acts upon two sides of the source region (32), the surface of the source region (32) is entirely under the action of a gate electric field, and the electric field direction of the gate region is consistent with the charge carrier tunneling direction of the source region, such that the tunneling probability is increased. Internal charge carriers in the source region do not contend with each other, and the action force of the gate electric field is increased, such that the epitaxial layer is completely consumed, the subthreshold swing of a device is reduced, and the power consumption is reduced.

Description

隧穿场效应晶体管及其制造方法Tunneling field effect transistor and method of manufacturing same 技术领域Technical field
本发明实施例涉及通信技术，尤其涉及一种隧穿场效应晶体管(英文：Tunnel field effect transistor，简称：TFET)及其制造方法。Embodiments of the present invention relate to communication technologies, and in particular, to a tunnel field effect transistor (TFET) and a method of fabricating the same.
背景技术Background technique
随着半导体技术的发展，为了持续紧跟摩尔定律，半导体器件尺寸将持续缩小，器件的制造成本增加，尤其是光刻工艺。另一个方面就是功耗问题，随着器件的特征尺寸的缩小，金氧化物半导体场效应晶体管(英文全称：Metal-Oxide-Semiconductor Field-Effect Transistor，简称：MOSFET)器件已经无法满足小尺寸器件的要求，因为在室温下其受到载流子波尔兹曼分布的限制，即kT/q。因此，室温下，亚阈值摆幅(英文全称：Subthreshold swing，简称：SS)无法小于60mV/decade，即在小尺寸器件条件下，功耗较高。With the development of semiconductor technology, in order to continue to follow Moore's Law, the size of semiconductor devices will continue to shrink, and the manufacturing cost of devices will increase, especially in photolithography. Another aspect is the power consumption problem. As the feature size of the device shrinks, the metal oxide semiconductor field effect transistor (English name: Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short) has been unable to meet the requirements of small-sized devices. It is required because it is limited by the carrier Boltzmann distribution at room temperature, ie kT/q. Therefore, at room temperature, the subthreshold swing (English full name: Subthreshold swing, referred to as: SS) can not be less than 60mV / decade, that is, in the case of small size devices, the power consumption is higher.
为了降低MOSFETs的功耗，需要减小供电电压，而当供电电压Vdd减小，依然保持高的驱动电流，这便要求极低的SS。但是，随着MOS器件尺寸持续缩小，MOSFET的电压缩小已经达到瓶颈，因此需要新的器件结构来跟随摩尔定律。而且这些器件的目标是供电电压小于0.5V，有极低的SS。开关机制的场效应晶体管(英文全称：Field Effect Transistor，简称：FET)能够实现SS小于60mV/dec的结构包括碰撞电离(impact-ionization)MOS器件，纳电机FETs以及隧穿场效应晶体管等。但是TFET作为极低功耗应用的一个最佳选择，因为室温下，TFET的SS值不受限于kT/q，即SS值小于60mV/decade，而且与CMOS工艺兼容以及工艺可扩展性，但是器件尺寸缩小实现高集成密度，会引起短沟道效应(short channel effect，SCE)，从而增加关断电流。In order to reduce the power consumption of MOSFETs, it is necessary to reduce the supply voltage, and when the supply voltage Vdd is reduced, the drive current is still maintained, which requires an extremely low SS. However, as MOS device sizes continue to shrink, the voltage reduction of MOSFETs has reached a bottleneck, so new device structures are needed to follow Moore's Law. Moreover, the goal of these devices is to supply voltages less than 0.5V with very low SS. The field effect transistor of the switching mechanism (English name: Field Effect Transistor, FET for short) can realize structures with SS less than 60mV/dec, including impact-ionization MOS devices, nano-motor FETs, and tunneling field effect transistors. But TFET is an excellent choice for very low power applications because the SS value of the TFET is not limited to kT/q at room temperature, ie the SS value is less than 60mV/decade, and is compatible with CMOS processes and process scalability, but The device size is reduced to achieve high integration density, which causes a short channel effect (SCE), which increases the off current.
微电子研究中心(英文：Interuniversity Microelectronics Centr，简称：IMEC)申请的国际公开号为WO2012/152762 A1的专利提供一种TFET的具体设计。图1为IMEC申请的国际公开号为WO2012/152762 A1的专利提供的TFET的结构示意图，如图1所示，图中的17、18、19分别表示源极、漏 极和栅极三个电极，12表示的是该TFET的源区，14表示该TFET的漏区，13为源区下面的部分，为未掺杂的硅，作为沟道，13a与13是一体形成的，但是13a是源区两侧的部分，同样是未掺杂的硅，作为外延层，15为栅电介质层，16表示栅区材料，20为绝缘层，42是该TFET的边墙，上述的TFET结构属于线性隧穿结构，源区12处于13区域的内部，在栅极电场的作用下，与源区12两侧的作为外延层的13a区域形成隧穿p-n结，当栅极19电压增加到一定值时，载流子发生隧穿。The specific design of a TFET is provided by the International Patent Publication No. WO 2012/152762 A1, which is incorporated by the International Publications. Figure 1 is a schematic view showing the structure of a TFET provided by the patent of the International Publication No. WO 2012/152762 A1, the disclosure of which is incorporated herein by reference. Three electrodes of the pole and the gate, 12 indicates the source region of the TFET, 14 indicates the drain region of the TFET, 13 is the portion under the source region, is undoped silicon, and serves as a channel, 13a and 13 are integrated Formed, but 13a is a portion on both sides of the source region, also undoped silicon, as an epitaxial layer, 15 is a gate dielectric layer, 16 is a gate region material, 20 is an insulating layer, and 42 is a sidewall of the TFET. The above TFET structure belongs to a linear tunneling structure, and the source region 12 is inside the 13 region. Under the action of the gate electric field, a tunneling pn junction is formed with the 13a region as an epitaxial layer on both sides of the source region 12, when the gate 19 When the voltage is increased to a certain value, carriers are tunneled.
然而，上述这种结构中源区和漏区之间的沟道区域必须足够宽，才能作为非栅控产生的带带隧穿的阻挡层，但是该沟道区域设置较宽时，会增加电阻，导致该TFET的亚阈值摆幅较大，功耗较高，并且增加器件尺寸。However, in the above structure, the channel region between the source region and the drain region must be sufficiently wide to serve as a barrier layer for tunneling generated by the non-gate control, but when the channel region is set wider, the resistance is increased. This results in a larger subthreshold swing of the TFET, higher power consumption, and increased device size.
发明内容Summary of the invention
本发明实施例提供一种隧穿场效应晶体管及其制造方法，用于解决沟道区域较宽导致电阻增加，进而使得的TFET的亚阈值摆幅较大，功耗较高，并且增加器件尺寸的问题。Embodiments of the present invention provide a tunneling field effect transistor and a method of fabricating the same, which are used to solve the problem that the channel region is wider and the resistance is increased, so that the subthreshold swing of the TFET is larger, the power consumption is higher, and the device size is increased. The problem.
本发明第一方面提供一种隧穿场效应晶体管，包括：A first aspect of the present invention provides a tunneling field effect transistor, including:
衬底层；Substrate layer
源区，所述源区覆盖在所述衬底层的部分表面，所述源区为柱体形状；a source region, the source region covering a portion of the surface of the substrate layer, the source region being in the shape of a cylinder;
第一绝缘层，所述第一绝缘层覆盖在所述源区远离所述衬底层的一端面上；a first insulating layer covering the one end surface of the source region away from the substrate layer;
漏区，所述漏区覆盖在所述第一绝缘层远离所述源区的表面上；a drain region covering the surface of the first insulating layer away from the source region;
第二绝缘层，所述第二绝缘层覆盖在所述衬底层上，位于所述源区周围，且所述第二绝缘层与所述源区接触；a second insulating layer overlying the substrate layer, located around the source region, and the second insulating layer is in contact with the source region;
外延层，所述外延层覆盖在所述源区的侧面上，且所述外延层与所述第二绝缘层远离所述衬底层的表面接触；An epitaxial layer covering the side of the source region, and the epitaxial layer is in contact with a surface of the second insulating layer away from the substrate layer;
栅区，所述栅区覆盖在所述外延层远离所述源区的表面上，所述栅区包括多个表面，其中两个表面分别与所述外延层和所述第二绝缘层接触；a gate region covering a surface of the epitaxial layer away from the source region, the gate region including a plurality of surfaces, wherein two surfaces are in contact with the epitaxial layer and the second insulating layer, respectively;
所述第二绝缘层用于隔离所述栅区与所述衬底层；所述第一绝缘层和所述外延层用于隔离所述漏区与所述源区。The second insulating layer is used to isolate the gate region from the substrate layer; the first insulating layer and the epitaxial layer are used to isolate the drain region from the source region.
可选的，上述的隧穿场效应晶体管的源区也可以是纳米线结构，即类似 于圆柱或者椭圆柱结构，若源区是纳米线结构，则外延层是围绕在源区的四周的，栅区也是类似。Optionally, the source region of the tunneling field effect transistor described above may also be a nanowire structure, that is, similar In a cylindrical or elliptical column structure, if the source region is a nanowire structure, the epitaxial layer is surrounded by the source region, and the gate region is similar.
本方案提供的隧穿场效应晶体管，通过将外延层围绕源区，栅区作用在源区侧面，源区表面均受到栅电场的作用，而且栅区电场方向和源区载流子隧穿方向一致，增强隧穿几率，源区内部载流子没有竞争关系，增强栅电场作用力，使外延层完全耗尽，减小器件的亚阈值摆幅，降低功耗，并且该结构可以减小器件尺寸。The tunneling field effect transistor provided by the scheme has the effect of the gate electric field on the surface of the source region by the epitaxial layer surrounding the source region, and the surface of the source region is affected by the gate electric field, and the electric field direction of the gate region and the carrier tunneling direction of the source region. Consistently, the tunneling probability is enhanced, the carrier inside the source region has no competition, the gate electric field force is enhanced, the epitaxial layer is completely depleted, the subthreshold swing of the device is reduced, the power consumption is reduced, and the structure can reduce the device. size.
在第一方面的一种实现方式中，所述源区为原位P++掺杂的半导体材料，所述半导体材料为硅、锗硅、四族材料和三五族材料中任一种；掺杂浓度为1e18～1e21cm-3。In an implementation manner of the first aspect, the source region is an in-situ P++ doped semiconductor material, and the semiconductor material is any one of silicon, germanium silicon, a group of four materials, and a tri-five material; The concentration is 1e 18 to 1e 21 cm -3 .
在第一方面的第二种实现方式中，所述衬底层的材料为硅、锗、SOI、GeOI，Ⅲ-Ⅴ族化合物材料中的任一种。In a second implementation manner of the first aspect, the material of the substrate layer is any one of silicon, germanium, SOI, GeOI, and III-V compound materials.
在上述两种方案中，可选的，衬底层的掺杂类型和源区一致。用来形成该源区的半导体材料具体可以是：如果是基于硅材料TFET，P型掺杂，杂质可以是B，Al，Ga，In，Ti，Pd，Na，Be，Zn，Au，Co，V，Ni，MO，Hg，Sr，Ge，W，Pb，O，Fe；如果是N型掺杂，杂质可以是Li，Sb，P，As，Bi，Te，Ti，C，Mg，Se，Cr，Ta，Cs，Ba，S，Mn，Ag，Cd，Pt。In the above two options, optionally, the doping type of the substrate layer is consistent with the source region. The semiconductor material used to form the source region may specifically be: if it is based on a silicon material TFET, P-type doping, the impurities may be B, Al, Ga, In, Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W, Pb, O, Fe; if it is N-type doping, the impurities may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag, Cd, Pt.
如果是基于锗材料的TFET，P型掺杂，杂质可以是B，Al，In，Ga，In，Be，Zn，Cr，Cd，Hg，Co，Ni，Mn，Fe，Pt；N型掺杂可以是Li，Sb，P，As，S，Se，Te，Cu，Au，Ag。If it is a TFET based on germanium material, P-type doping, the impurities may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt; N-type doping It may be Li, Sb, P, As, S, Se, Te, Cu, Au, Ag.
在第一方方面的第三种实现方式中，所述漏区为原位N++掺杂的半导体材料。In a third implementation of the first aspect, the drain region is an in situ N++ doped semiconductor material.
在上述任一种实现方式中，所述第一绝缘层的材料为SiO2、氮化硅或者硅的氮氧化物；所述第二绝缘层的材料为SiO2、氮化硅或者硅的氮氧化物。In any of the above implementations, the material of the first insulating layer is SiO 2 , silicon nitride or silicon oxynitride; the material of the second insulating layer is SiO 2 , silicon nitride or silicon oxynitride .
该第一绝缘层的主要是作为源区和漏区的一个隔离，防止所述隧穿场效应晶体管在关断态的情况下泄露电流。The first insulating layer is mainly an isolation as a source region and a drain region, preventing the tunneling field effect transistor from leaking current in an off state.
可选的，所述栅区的高度小于或等于所述源区的高度。进一步的，所述栅区包括栅电介质层和栅极；所述栅电介质层的材料为SiO2和/或HfO2。Optionally, the height of the gate region is less than or equal to the height of the source region. Further, the gate region includes a gate dielectric layer and a gate; and the gate dielectric layer is made of SiO2 and/or HfO2.
该方案中优选的是栅区和源区的高度一致，是为了更好的控制源区载流子，避免由于源区高于栅区，产生点隧穿或线隧穿混合机制，影响器件特性。 Preferably, the height of the gate region and the source region are the same in order to better control the source region carriers, and avoid a point tunneling or line tunneling mixing mechanism due to the source region being higher than the gate region, thereby affecting device characteristics. .
进一步，在上述结构的基础上，还需要沉积边墙形成完整的隧穿场效应晶体管器件。Further, on the basis of the above structure, it is also required to deposit a sidewall to form a complete tunneling field effect transistor device.
本发明第二方面提供一种隧穿场效应晶体管的制造方法，包括：A second aspect of the present invention provides a method of fabricating a tunneling field effect transistor, including:
形成衬底层；Forming a substrate layer;
在所述衬底层上形成第二绝缘层；Forming a second insulating layer on the substrate layer;
在所述第二绝缘层的中间区域开孔露出衬底层，并在所述开孔区域的衬底层上形成源区；所述源区为长方体形状；Opening a substrate layer in an intermediate portion of the second insulating layer, and forming a source region on the substrate layer of the opening region; the source region is in a rectangular parallelepiped shape;
在所述源区上远离所述衬底层的另一端形成第一绝缘层；Forming a first insulating layer on the source region away from the other end of the substrate layer;
在所述源区的侧面形成外延层；Forming an epitaxial layer on a side of the source region;
在所述第一绝缘层和所述外延层的整体外侧形成栅区；Forming a gate region on an outer side of the first insulating layer and the epitaxial layer;
去除所述栅区位于所述源区上部的部分以露出第一绝缘层；Removing a portion of the gate region located at an upper portion of the source region to expose the first insulating layer;
在所述第一绝缘层和所述外延层的上部形成漏区。A drain region is formed on the first insulating layer and the upper portion of the epitaxial layer.
在该方案中，上述的隧穿场效应晶体管的源区也可以是纳米线结构，即类似于圆柱或者椭圆柱结构，若源区是纳米线结构，则外延层是围绕在源区的四周的，栅区也是类似的围绕在外延层外部。若源区是长方体结构时，该第二绝缘层可以在形成源区之前，也可以在形成源区之后，若源区是纳米线结构，第二绝缘层只能在形成源区之前沉积并图形化形成。In this solution, the source region of the tunneling field effect transistor may also be a nanowire structure, that is, similar to a cylindrical or elliptical column structure. If the source region is a nanowire structure, the epitaxial layer is surrounded by the source region. The gate region is also similarly surrounded outside the epitaxial layer. If the source region is a rectangular parallelepiped structure, the second insulating layer may be formed before the source region or after the source region is formed. If the source region is a nanowire structure, the second insulating layer may only be deposited and patterned before the source region is formed. Formed.
该方法形成的隧穿场效应晶体管，通过形成外延层围绕源区，栅区形成在作用在源区两侧或者周围，源区表面均受到栅电场的作用，而且栅区电场方向和源区载流子隧穿方向一致，增强隧穿几率，源区内部载流子没有竞争关系，增强栅电场作用力，使外延层完全耗尽，减小器件的亚阈值摆幅，降低功耗，并且该结构可以减小器件尺寸。The tunneling field effect transistor formed by the method surrounds the source region by forming an epitaxial layer, and the gate region is formed on or around the source region, and the surface of the source region is subjected to the gate electric field, and the electric field direction and the source region of the gate region are carried. The tunneling direction of the carriers is uniform, the tunneling probability is enhanced, the carriers in the source region have no competition relationship, the gate electric field force is enhanced, the epitaxial layer is completely depleted, the subthreshold swing of the device is reduced, and the power consumption is reduced. The structure can reduce the device size.
在第二方面的第一种实现方案中，所述在所述第二绝缘层的中间区域开孔露出衬底层，并在所述开孔区域的衬底层上形成源区，包括：In a first implementation of the second aspect, the opening a hole in the intermediate portion of the second insulating layer to expose the substrate layer, and forming a source region on the substrate layer of the opening region, comprising:
通过光刻技术在所述第二绝缘层的中间区域开孔露出衬底层；Opening a substrate layer in a middle portion of the second insulating layer by a photolithography technique;
在所述第二绝缘层的开孔区域的衬底层上，形成由原位P++掺杂的半导体材料构成的源区。On the substrate layer of the open region of the second insulating layer, a source region composed of an in situ P++ doped semiconductor material is formed.
提供材料为硅、锗、SOI、GeOI，Ⅲ-Ⅴ族化合物材料中的任一种构成的衬底层，在该衬底层上采用化学气相沉积工艺或者氧化工艺形成第二绝缘层。另外，该第二绝缘层可以在形成源区之前或者之后。如果源区是纳米线结构， 则该第二绝缘层需在源区形成之前沉积并图形化。该第二绝缘层的主要起隔离衬底层和后续在该第二绝缘层上形成的其他材料。A substrate layer is provided which is made of any one of silicon, germanium, SOI, GeOI, and III-V compound materials, and a second insulating layer is formed on the substrate layer by a chemical vapor deposition process or an oxidation process. Additionally, the second insulating layer may be before or after the source region is formed. If the source region is a nanowire structure, The second insulating layer is then deposited and patterned prior to formation of the source region. The second insulating layer mainly serves as a spacer substrate layer and other materials subsequently formed on the second insulating layer.
在第二方面的第二种实现方式中，所述在所述源区上远离所述衬底层的另一端形成第一绝缘层，包括：In a second implementation manner of the second aspect, the forming the first insulating layer on the source region away from the other end of the substrate layer comprises:
采用SiO2、氮化硅或者硅的氮氧化物在所述源区外部形成绝缘层，并对该绝缘层进行刻蚀只保留所述源区上远离所述衬底层的一端顶部的部分作为第一绝缘层；Forming an insulating layer on the outside of the source region using NOx, silicon nitride or silicon oxynitride, and etching the insulating layer to retain only a portion of the source region away from the top of one end of the substrate layer as the first Insulation;
则所述在所述源区的侧面形成外延层，包括：Forming an epitaxial layer on a side of the source region, including:
在所述源区的侧面沉积由本征掺杂半导体构成的半导体层，刻蚀所述半导体层露出所述第一绝缘层，将所述半导体层的剩余部分作为所述外延层。A semiconductor layer composed of an intrinsically doped semiconductor is deposited on a side of the source region, and the semiconductor layer is etched to expose the first insulating layer, and the remaining portion of the semiconductor layer is used as the epitaxial layer.
在该方案中，在源区外部沉积绝缘层，并对其进行刻蚀，只保留源区顶部的部分作为第一绝缘层，作为源区和漏区的隔离，防止关断状态下的泄露电流。In this scheme, an insulating layer is deposited on the outside of the source region and etched, leaving only the portion at the top of the source region as the first insulating layer, as isolation between the source region and the drain region, preventing leakage current in the off state. .
在第二方面的第三种实现方式中，所述栅区包括电介质层和栅极；所述在所述第一绝缘层和所述外延层的整体外侧形成栅区，包括：In a third implementation manner of the second aspect, the gate region includes a dielectric layer and a gate; and forming a gate region on an outer side of the first insulating layer and the epitaxial layer comprises:
采用SiO2和/或HfO2材料在所述外延层的外部沉积电介质层，并采用多晶硅或者金属材料在所述电介质层外侧沉积栅极；Depositing a dielectric layer on the outside of the epitaxial layer using SiO2 and/or HfO2 material, and depositing a gate on the outside of the dielectric layer using polysilicon or a metal material;
则所述去除所述栅区位于所述第一绝缘层上部的部分以露出第一绝缘层，包括：And removing the portion of the gate region located at an upper portion of the first insulating layer to expose the first insulating layer, including:
刻蚀所述电介质层和所述栅极，露出所述第一绝缘层顶部的所述第一绝缘层。Etching the dielectric layer and the gate to expose the first insulating layer on top of the first insulating layer.
本方案中不限于HfO2材料，也可以采用其他的高K材料和/或SiO2形成电介质层。The present embodiment is not limited to the HfO 2 material, and other high K materials and/or SiO 2 may be used to form the dielectric layer.
在第二方面的第四种实现方式中，所述在所述第一绝缘层和所述外延层的上部形成漏区，包括：In a fourth implementation manner of the second aspect, the forming a drain region on an upper portion of the first insulating layer and the epitaxial layer comprises:
在所述第一绝缘层和所述外延层上部沉积原位N++掺杂的半导体材料，并刻蚀所述半导体材料，只保留所述第一绝缘层和所述外延层上部的部分作为所述漏区。Depositing an in-situ N++ doped semiconductor material on the first insulating layer and the epitaxial layer, and etching the semiconductor material, leaving only the first insulating layer and a portion of the upper portion of the epitaxial layer as the Drain zone.
在上述两种方案中，一般情况下栅区的高度小于或等于所述源区的高度，优选的是栅区的高度和源区的高度一致，是为了很好的控制源区载流子，避 免源区高于或者低于栅区，产生点隧穿和线隧穿混合机制，影响器件特性的问题。In the above two schemes, in general, the height of the gate region is less than or equal to the height of the source region, and it is preferable that the height of the gate region and the height of the source region are consistent, in order to well control the source region carriers. Avoid The source-free zone is higher or lower than the gate region, and a point tunneling and line tunneling mixing mechanism is generated, which affects the characteristics of the device.
在上述任一实现方式之后，还需要采用硅氧化物、氮化硅或高介电常数的电介质沉积边墙，形成隧穿场效应晶体管。After any of the above implementations, it is also necessary to form a tunneling field effect transistor by using silicon oxide, silicon nitride or a high dielectric constant dielectric deposition sidewall.
本发明提供的隧穿场效应晶体管及其制造方法，通过采用新的结构，将外延层设置在源区的两侧，或者外延层围绕源区，栅区作用在源区的两侧，即源区受到栅电场的作用，且栅电场方向和源区载流子隧穿方向一致，增强隧穿几率，并且该新的结构中，源区整体位于栅区之间，隧穿面积增大，相较于现有技术，源区内部的载流子没有竞争关系，进一步增强了栅电场的作用力，即增强遂穿电流，直至外延层完全耗尽，即在同样的栅极增压下可以增大漏极电流的变化，即减小器件的亚阈值摆幅，即增强器件的亚阈值特性。The tunneling field effect transistor and the method for fabricating the same according to the present invention, by adopting a new structure, the epitaxial layer is disposed on both sides of the source region, or the epitaxial layer surrounds the source region, and the gate region acts on both sides of the source region, that is, the source The region is subjected to the gate electric field, and the gate electric field direction is consistent with the source region carrier tunneling direction, and the tunneling probability is enhanced. In the new structure, the source region is entirely located between the gate regions, and the tunneling area is increased. Compared with the prior art, carriers in the source region have no competition relationship, further enhancing the force of the gate electric field, that is, enhancing the tunneling current until the epitaxial layer is completely depleted, that is, it can be increased under the same gate boosting. The change in the large drain current, ie, the subthreshold swing of the device, enhances the subthreshold characteristics of the device.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.
图1为IMEC申请的国际公开号为WO2012/152762 A1的专利提供的TFET的结构示意图；Figure 1 is a schematic view showing the structure of a TFET provided by the patent of International Publication No. WO 2012/152762 A1;
图2为本发明实施例提供的隧穿场效应晶体管实施例一的立体图；2 is a perspective view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention;
图3为本发明实施例提供的隧穿场效应晶体管实施例一的主视图；3 is a front view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention;
图4为本发明实施例提供的隧穿场效应晶体管实施例一横截面图；4 is a cross-sectional view showing a tunneling field effect transistor according to an embodiment of the present invention;
图5为本发明实施例提供的隧穿场效应晶体管实施例一的俯视图；FIG. 5 is a top view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention; FIG.
图6为本发明实施例提供的隧穿场效应晶体管实施例二横截面图；6 is a cross-sectional view showing a second embodiment of a tunneling field effect transistor according to an embodiment of the present invention;
图7为本发明实施例提供的隧穿场效应晶体管的制造方法实施例一的流程图；FIG. 7 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present disclosure;
图8(a)至图8(k)为本发明实施例提供的隧穿场效应晶体管的制造方法一实例的制造过程说明示意图。8(a) to 8(k) are schematic diagrams illustrating a manufacturing process of an example of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
具体实施方式 detailed description
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
本发明提供一种不仅可以缩小器件面积、栅控能力更强的垂直结构的TFET，能够有效的降低器件的SS值并且尺寸较小，具体的实现请参考下面的实施例。The invention provides a vertical structure TFET which can not only reduce the device area and the gate control capability, but also can effectively reduce the SS value of the device and has a small size. For the specific implementation, please refer to the following embodiments.
图2为本发明实施例提供的隧穿场效应晶体管实施例一的立体图；图3为本发明实施例提供的隧穿场效应晶体管实施例一的主视图；图4为本发明实施例提供的隧穿场效应晶体管实施例一横截面图；图5为本发明实施例提供的隧穿场效应晶体管实施例一的俯视图。如图2-5所示，该隧穿场效应晶体管30，包括：2 is a perspective view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention; FIG. 3 is a front view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention; A cross-sectional view of a tunneling field effect transistor embodiment is shown in FIG. 5; FIG. 5 is a top view of a first embodiment of a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 2-5, the tunneling field effect transistor 30 includes:
衬底层31； Substrate layer 31;
源区32，源区32覆盖在衬底层31的部分表面，源区32为柱体形状；a source region 32 covering a portion of the surface of the substrate layer 31, the source region 32 being in the shape of a cylinder;
第一绝缘层33，第一绝缘层33覆盖在源区32远离衬底层31的一端面上；a first insulating layer 33 covering the one end surface of the source region 32 away from the substrate layer 31;
漏区34，漏区34覆盖在第一绝缘层33远离源区32的表面上；a drain region 34 covering the surface of the first insulating layer 33 away from the source region 32;
第二绝缘层35，第二绝缘层35覆盖在衬底层31上，位于源区32周围，且第二绝缘层35与源区32接触；a second insulating layer 35 covering the substrate layer 31, located around the source region 32, and the second insulating layer 35 is in contact with the source region 32;
外延层36，外延层36覆盖在源区32的侧面上，且外延层36与第二绝缘层35远离衬底层31的表面接触； Epitaxial layer 36, epitaxial layer 36 overlying the side of source region 32, and epitaxial layer 36 is in contact with the surface of second insulating layer 35 away from substrate layer 31;
栅区37，栅区37覆盖在外延层36远离源区32的表面上，栅区37包括多个表面，其中两个表面分别与外延层36和第二绝缘层35接触；a gate region 37 covering the surface of the epitaxial layer 36 away from the source region 32, the gate region 37 comprising a plurality of surfaces, wherein the two surfaces are in contact with the epitaxial layer 36 and the second insulating layer 35, respectively;
第二绝缘层35用于隔离栅区37与衬底层31；第一绝缘层33和外延层36用于隔离漏区34与源区32。The second insulating layer 35 is used to isolate the gate region 37 from the substrate layer 31; the first insulating layer 33 and the epitaxial layer 36 are used to isolate the drain region 34 from the source region 32.
在本实施例中，该衬底层31在具体实现的过程中可以采用的材料包括硅、锗、SOI、GeOI，Ⅲ-Ⅴ族化合物材料等中的任一种。可选的，该衬底层31可以包括本征硅311和埋入氧化层312两部分。In this embodiment, the material that the substrate layer 31 can be used in the specific implementation process includes any one of silicon, germanium, SOI, GeOI, III-V compound materials, and the like. Optionally, the substrate layer 31 may include two portions of intrinsic silicon 311 and buried oxide layer 312.
源区32可为原位P++掺杂的半导体材料，半导体材料可为硅、锗硅、四 族材料和三五族材料中任一种；掺杂浓度可为1e18～1e21cm-3。The source region 32 may be an in-situ P++ doped semiconductor material, and the semiconductor material may be any one of silicon, germanium silicon, a quadruplex material, and a tri-five material; the doping concentration may be 1e 18 to 1e 21 cm -3 .
可选的，源区可以为方形主体，也可以是纳米线结构，类似于圆柱体或者椭圆柱体的形状。Optionally, the source region may be a square body or a nanowire structure, similar to the shape of a cylinder or an elliptical cylinder.
第二绝缘层35可以是一个整体，源区32实际上是穿过第二绝缘层35的上的缺口设置在衬底层31上的，例如：源区32是方形柱体，则该第二绝缘层35上有对应的方形缺口；源区32是圆形柱体或者椭圆形柱体，则该第二绝缘层35上有对应的圆形或椭圆形缺口。另外，第二绝缘层35也可以是多个分离的部分，能够将栅区37和衬底层31隔离即可，对此本发明不做限制。The second insulating layer 35 may be a whole, and the source region 32 is actually disposed on the substrate layer 31 through the upper notch of the second insulating layer 35. For example, the source region 32 is a square pillar, and the second insulation is The layer 35 has a corresponding square notch; the source region 32 is a circular cylinder or an elliptical cylinder, and the second insulating layer 35 has a corresponding circular or elliptical notch. In addition, the second insulating layer 35 may also be a plurality of separate portions, and the gate region 37 and the substrate layer 31 can be isolated, which is not limited in the present invention.
衬底层31的掺杂类型可和源区32一致，用来形成该源区32的半导体材料具体可以是：如果是基于硅材料TFET，P型掺杂，杂质可以是B，Al，Ga，In，Ti，Pd，Na，Be，Zn，Au，Co，V，Ni，MO，Hg，Sr，Ge，W，Pb，O，Fe；如果是基于硅材料TFET，N型掺杂，杂质可以是Li，Sb，P，As，Bi，Te，Ti，C，Mg，Se，Cr，Ta，Cs，Ba，S，Mn，Ag，Cd，Pt。The doping type of the substrate layer 31 may be the same as that of the source region 32. The semiconductor material used to form the source region 32 may specifically be: if it is based on a silicon material TFET, P-type doping, the impurity may be B, Al, Ga, In , Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W, Pb, O, Fe; if it is based on a silicon material TFET, N-type doping, the impurity may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag, Cd, Pt.
如果是基于锗材料的TFET，P型掺杂，杂质可以是B，Al，In，Ga，In，Be，Zn，Cr，Cd，Hg，Co，Ni，Mn，Fe，Pt；如果是基于锗材料的TFET，N型掺杂可以是Li，Sb，P，As，S，Se，Te，Cu，Au，Ag。If it is a TFET based on germanium material, P-type doping, the impurities may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt; The TFET of the material may be Li, Sb, P, As, S, Se, Te, Cu, Au, Ag.
具体实现中，漏区34为原位N++掺杂的半导体材料。第一绝缘层33的材料为SiO2、氮化硅或者硅的氮氧化物；第二绝缘层35的材料为SiO2、氮化硅或者硅的氮氧化物。In a specific implementation, the drain region 34 is an in situ N++ doped semiconductor material. The material of the first insulating layer 33 is SiO 2 , silicon nitride or silicon oxynitride; the material of the second insulating layer 35 is SiO 2 , silicon nitride or silicon oxynitride.
优选的，栅区37的高度小于或等于源区32的高度。更优选的是将栅区37和源区32设置成相同的高度，更好的控制源区32载流子。Preferably, the height of the gate region 37 is less than or equal to the height of the source region 32. More preferably, the gate region 37 and the source region 32 are disposed at the same height to better control the source region 32 carriers.
其中，栅区37包括栅电介质层371和栅极372；栅电介质层371的材料为SiO2和/或HfO2。The gate region 37 includes a gate dielectric layer 371 and a gate 372; the material of the gate dielectric layer 371 is SiO2 and/or HfO2.
上述的隧穿场效应晶体管的工作原理为：栅极372加正偏压，源区32接地，漏区34加正偏压；在栅电压的作用下，源区32少数载流子从源区32的价带顶隧穿到外延层36区域的导带底中，形成隧穿电流，并受到两侧漏区34电压的作用，流入漏区34形成漏电流。The working principle of the tunneling field effect transistor described above is that the gate 372 is positively biased, the source region 32 is grounded, and the drain region 34 is positively biased; under the action of the gate voltage, minority carriers in the source region 32 are sourced from the source region. The valence band of 32 is tunneled into the bottom of the conduction band in the epitaxial layer 36 region to form a tunneling current, which is subjected to the voltage of the drain region 34 on both sides, and flows into the drain region 34 to form a leakage current.
可选的，在上述实施例提供的隧穿场效应晶体管基础上，图6为本发明实施例提供的隧穿场效应晶体管实施例二横截面图，如图6所示，与上述方案不同的是，源区32的结构可采用鳍条形状，相当于梯形，即源区32与衬 底层31接触的表面积大于与第一绝缘层33接触的表面积，该种能够进一步提高栅区37对源区32的控制能力，其他的结构与图2-5中所示的相同。Optionally, based on the tunneling field effect transistor provided in the foregoing embodiment, FIG. 6 is a cross-sectional view of a second embodiment of the tunneling field effect transistor according to the embodiment of the present invention, as shown in FIG. Yes, the structure of the source region 32 can adopt a fin shape, which is equivalent to a trapezoid, that is, the source region 32 and the lining. The surface area of the bottom layer 31 is larger than the surface area in contact with the first insulating layer 33, which can further improve the control of the source region 32 by the gate region 37, and other structures are the same as those shown in Figs. 2-5.
亚阈值摆幅的定义为：S＝dVgs/d(log10Id)。S在数值上就等于为使漏极电流Id变化一个数量级时所需要的栅极电压增量ΔVgs。The subthreshold swing is defined as: S = dVgs / d (log10Id). S is numerically equal to the gate voltage delta ΔVgs required to vary the drain current Id by an order of magnitude.
本发明各个实施例提供的隧穿场效应晶体管，其结构中外延层36区域围绕源区32，栅极作用到源区32两侧，即源区32表面均受到栅电场的作用，而且栅极电场方向和源区32的载流子隧穿方向一致，增强了隧穿几率，而且源区32整体位于栅区37之间，因此隧穿面积增大，与现有技术对比，源区32内部的载流子没有竞争关系，而且增强了栅电场的作用力，导致外延层36完全耗尽，改变漏极电流，即在同样的栅极增压下可以增大漏极电流的变化，即，在器件上施加的电压不变的情况下，有效降低器件的亚阈值摆幅，增强了器件的亚阈值特性。并且按照上述的实现方案，也不会增加器件的尺寸。The tunneling field effect transistor provided by the various embodiments of the present invention has a structure in which an epitaxial layer 36 region surrounds the source region 32, and a gate electrode acts on both sides of the source region 32, that is, the surface of the source region 32 is subjected to a gate electric field, and the gate electrode The direction of the electric field is consistent with the carrier tunneling direction of the source region 32, and the tunneling probability is enhanced, and the source region 32 is entirely located between the gate regions 37, so the tunneling area is increased, and the source region 32 is internally compared with the prior art. The carrier has no competing relationship, and enhances the force of the gate electric field, causing the epitaxial layer 36 to be completely depleted and changing the drain current, that is, the drain current can be increased under the same gate boost, that is, Under the condition that the voltage applied on the device is constant, the subthreshold swing of the device is effectively reduced, and the subthreshold characteristic of the device is enhanced. And according to the above implementation, the size of the device is not increased.
图7为本发明实施例提供的隧穿场效应晶体管的制造方法实施例一的流程图，如图7所示，该隧穿场效应晶体管的制造方法的具体步骤包括：FIG. 7 is a flowchart of Embodiment 1 of a method for manufacturing a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 7, the specific steps of the method for manufacturing the tunneling field effect transistor include:
S101：形成衬底层。S101: forming a substrate layer.
选择合适的衬底材料按照需要的形状加工形成该衬底层。The substrate layer is formed by processing a suitable substrate material in a desired shape.
S102：在衬底层上形成第二绝缘层。S102: forming a second insulating layer on the substrate layer.
在本实施例中，在所形成的衬底层上，沉积一层第二绝缘层，材料可以是SiO2或者氮化硅等，可以采用化学汽相沉积工艺或者氧化工艺，该绝缘层2作为衬底和后续形成在该绝缘层上的材料的隔离层。In this embodiment, a second insulating layer is deposited on the formed substrate layer, and the material may be SiO2 or silicon nitride, etc., and may be performed by a chemical vapor deposition process or an oxidation process, and the insulating layer 2 is used as a substrate. And an isolation layer of material subsequently formed on the insulating layer.
S103：在第二绝缘层的中间区域开孔露出衬底层，并在开孔区域的衬底层上形成源区。S103: opening a hole in the middle portion of the second insulating layer to expose the substrate layer, and forming a source region on the substrate layer of the open region.
在本实施例中，源区为长方体形状、鳍条形状或者圆柱体等柱状形状。具体的形成源区的方式是：通过光刻技术在第二绝缘层的中间区域开孔露出衬底层；在第二绝缘层的开孔区域的衬底层上，形成由原位P++掺杂的半导体材料构成的源区。In the present embodiment, the source region has a columnar shape such as a rectangular parallelepiped shape, a fin shape, or a cylindrical shape. Specifically, the source region is formed by: opening a hole in the middle portion of the second insulating layer by photolithography to expose the substrate layer; forming a semiconductor doped with P++ in situ on the substrate layer of the open region of the second insulating layer The source area of the material.
S104：在源区上远离衬底层的另一端形成第一绝缘层。S104: forming a first insulating layer on the source region away from the other end of the substrate layer.
S105：在源区的侧面形成外延层。S105: forming an epitaxial layer on a side of the source region.
在本实施例中，采用SiO2、氮化硅或者硅的氮氧化物在源区外部形成绝缘层，并对该绝缘层进行刻蚀只保留源区上远离衬底层的一端顶部的部分作 为第一绝缘层；在源区的两侧沉积由本征掺杂半导体构成的半导体层，刻蚀半导体层露出第一绝缘层，将半导体层的剩余部分作为外延层。In this embodiment, an insulating layer is formed outside the source region by using NOx, silicon nitride or silicon oxynitride, and etching the insulating layer only leaves a portion of the source region at the top of the end portion away from the substrate layer. A first insulating layer; a semiconductor layer made of an intrinsically doped semiconductor is deposited on both sides of the source region, the etched semiconductor layer exposes the first insulating layer, and the remaining portion of the semiconductor layer is used as an epitaxial layer.
S106：在第一绝缘层和外延层的整体外侧形成栅区。S106: forming a gate region on the outer side of the first insulating layer and the epitaxial layer.
S107：去除栅区位于第一绝缘层上部的部分以露出第一绝缘层。S107: removing a portion of the gate region located at an upper portion of the first insulating layer to expose the first insulating layer.
在本实施例中，具体实现为：采用SiO2和/或HfO2材料在第一绝缘层以及外延层的外部沉积电介质层，并采用多晶硅或者金属材料在电介质层外侧沉积栅极；刻蚀电介质层和栅极，露出第一绝缘层顶部的第一绝缘层。In this embodiment, the specific implementation is: depositing a dielectric layer on the outside of the first insulating layer and the epitaxial layer by using SiO 2 and/or HfO 2 materials, and depositing a gate on the outer side of the dielectric layer by using polysilicon or a metal material; etching the dielectric layer and a gate that exposes a first insulating layer on top of the first insulating layer.
优选的，栅区的高度小于或等于源区的高度，更优选的，该源区高度与栅区的高度一致。Preferably, the height of the gate region is less than or equal to the height of the source region, and more preferably, the height of the source region coincides with the height of the gate region.
S108：在第一绝缘层和外延层的上部形成漏区。S108: forming a drain region on the upper portion of the first insulating layer and the epitaxial layer.
在本实施例中，具体的，在第一绝缘层和外延层上部沉积原位N++掺杂的半导体材料，并刻蚀半导体材料，只保留第一绝缘层和外延层上部的部分作为漏区。一种可选的方式为，外延层的高度高于源区却低于第一绝缘层，这是刻蚀后形成的漏区为U型，漏区周边包裹在第一绝缘层外侧并与外延层连接在一起。In this embodiment, specifically, an in-situ N++ doped semiconductor material is deposited on the first insulating layer and the epitaxial layer, and the semiconductor material is etched, leaving only the first insulating layer and a portion of the upper portion of the epitaxial layer as a drain region. An optional method is that the height of the epitaxial layer is higher than that of the source region but lower than the first insulating layer. The drain region formed after etching is U-shaped, and the periphery of the drain region is wrapped outside the first insulating layer and extended with the epitaxial layer. The layers are connected together.
可选的，方法还包括：采用硅氧化物、氮化硅或高介电常数的电介质沉积边墙，形成隧穿场效应晶体管。Optionally, the method further comprises: forming a tunneling field effect transistor by using silicon oxide, silicon nitride or a high dielectric constant dielectric deposition sidewall.
本实施例提供的隧穿场效应晶体管的制造方法，通过在源区的两侧形成栅区，形成的外延层位于源区和栅区的栅电介质层之间，栅极电场作用在源区和外延层，直至耗尽p-n结，降低改变漏极电流所需要的栅极电压增量，即有效降低器件的SS值，并且通过第一绝缘层降低泄露电流。上述工艺过程简单，并且能够与CMOS工艺兼容。In the manufacturing method of the tunneling field effect transistor provided in this embodiment, by forming a gate region on both sides of the source region, an epitaxial layer is formed between the source region and the gate dielectric layer of the gate region, and the gate electric field acts on the source region and The epitaxial layer, until the pn junction is depleted, reduces the gate voltage increment required to change the drain current, ie, effectively reduces the SS value of the device, and reduces the leakage current through the first insulating layer. The above process is simple and compatible with CMOS processes.
在上述实施例的基础上，下面举一实例详细说明本制造方法的具体实现步骤：图8(a)至图8(j)为本发明实施例提供的隧穿场效应晶体管的制造方法一实例的制造过程说明示意图。Based on the above embodiments, an specific implementation step of the manufacturing method will be described in detail below. FIG. 8(a) to FIG. 8(j) are examples of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention. A schematic diagram of the manufacturing process.
步骤1：提供一半导体构成的衬底层。Step 1: Providing a substrate layer of a semiconductor.
该衬底层的材料可以是是硅、锗、SOI、GeOI，Ⅲ-Ⅴ族化合物材料等。本实例以硅衬底层1为例，如图8(a)。The material of the underlayer may be silicon, germanium, SOI, GeOI, a III-V compound material or the like. This example takes the silicon substrate layer 1 as an example, as shown in Fig. 8(a).
步骤2：在上述的衬底层上形成第二绝缘层。Step 2: Forming a second insulating layer on the above substrate layer.
如图8(b)所示，在所形成的衬底层1上，沉积一层第二绝缘层2，材料可 以是SiO2或者氮化硅等，可以采用化学汽相沉积工艺或者氧化工艺。该第二绝缘层2作为衬底和后续形成在该绝缘层上的材料的隔离层。As shown in FIG. 8(b), on the formed substrate layer 1, a second insulating layer 2 is deposited, and the material is In the case of SiO2 or silicon nitride, a chemical vapor deposition process or an oxidation process may be employed. The second insulating layer 2 serves as a spacer for the substrate and a material subsequently formed on the insulating layer.
步骤3：图形化上述第二绝缘层2，在该第二绝缘层2上开孔露出衬底层1.Step 3: The second insulating layer 2 is patterned, and the second insulating layer 2 is opened to expose the substrate layer 1.
如图8(c)图形化该第二绝缘层2，中间区域露出衬底层1。图形化第二绝缘层2通过开孔露出部分衬底所采用的工艺：使用光刻技术包括提供硬掩膜3在绝缘层上，并提供电阻层4在硬掩膜层，通过光刻曝光电阻层，并移除该曝光电阻层4，图形化硬掩膜层3图形化第二绝缘层2。The second insulating layer 2 is patterned as shown in Fig. 8(c), and the intermediate layer exposes the substrate layer 1. The process of patterning the second insulating layer 2 to expose a portion of the substrate through the opening: using a photolithography technique to provide a hard mask 3 on the insulating layer, and providing the resistive layer 4 in the hard mask layer, through the lithographic exposure resistor The layer is removed, and the exposed resistive layer 4 is removed, and the patterned hard mask layer 3 is patterned to form the second insulating layer 2.
步骤4：在第二绝缘层2中露出衬底层1的部分上，形成一个垂直的半导体材料构成的源区。Step 4: On a portion of the second insulating layer 2 where the substrate layer 1 is exposed, a source region of a vertical semiconductor material is formed.
如图8(d)：以该第二绝缘层2为掩膜，在中间区域形成柱体原位P++掺杂的半导体材料构成源区5。若该源区5为长方体形状或者鳍条形状则该绝缘层可以在形成源区之前或者源区之后；若该源区5是纳米线结构，该绝缘层在源区形成之前沉积并图形化。8(d): using the second insulating layer 2 as a mask, a pillar-in-situ P++ doped semiconductor material is formed in the intermediate region to constitute the source region 5. If the source region 5 has a rectangular parallelepiped shape or a fin shape, the insulating layer may be before or after the source region; if the source region 5 is a nanowire structure, the insulating layer is deposited and patterned before the source region is formed.
形成源区的半导体材料可以是硅、锗硅，四族材料，三五族材料等等；掺杂浓度在1e18～1e21cm-3。衬底层1的掺杂类型和源区类型一致。The semiconductor material forming the source region may be silicon, germanium silicon, a group of four materials, a tri-five material, or the like; and the doping concentration is from 1e 18 to 1e 21 cm -3 . The doping type of the substrate layer 1 is identical to the source region type.
如果是基于硅材料TFET，P型掺杂，杂质可以是B，Al，Ga，In，Ti，Pd，Na，Be，Zn，Au，Co，V，Ni，MO，Hg，Sr，Ge，W，Pb，O，Fe；如果是N型掺杂，杂质可以是Li，Sb，P，As，Bi，Te，Ti，C，Mg，Se，Cr，Ta，Cs，Ba，S，Mn，Ag，Cd，Pt。If it is based on a silicon material TFET, P-type doping, the impurities may be B, Al, Ga, In, Ti, Pd, Na, Be, Zn, Au, Co, V, Ni, MO, Hg, Sr, Ge, W , Pb, O, Fe; if it is N-type doping, the impurities may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba, S, Mn, Ag , Cd, Pt.
如果是基于锗材料的TFET，P型掺杂可以B，Al，In，Ga，In，Be，Zn，Cr，Cd，Hg，Co，Ni，Mn，Fe，Pt；N型掺杂可以是Li，Sb，P，As，S，Se，Te，Cu，Au，Ag。If it is a TFET based on germanium material, the P-type doping may be B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, Pt; the N-type doping may be Li , Sb, P, As, S, Se, Te, Cu, Au, Ag.
步骤5：在源区5外层沉积绝缘层，并进行刻蚀只保留该绝缘层在源区5顶部的部分作为第一绝缘层6.Step 5: deposit an insulating layer on the outer layer of the source region 5, and etch only the portion of the insulating layer at the top of the source region 5 as the first insulating layer 6.
如图8(e)：提供电介质材料绝缘层6，可以是SiO2或者其他电介质材料。As shown in Fig. 8(e): a dielectric material insulating layer 6 is provided, which may be SiO2 or other dielectric material.
如图8(f)，刻蚀绝缘层6，方法同步骤3。只保留源区顶部的部分作为第一绝缘层6。该第一绝缘层6作为源区和漏区的一个隔离，防止关断态下的泄露电流。As shown in FIG. 8(f), the insulating layer 6 is etched in the same manner as in step 3. Only the portion at the top of the source region remains as the first insulating layer 6. The first insulating layer 6 serves as an isolation between the source region and the drain region to prevent leakage current in the off state.
具体过程是，在半导体材料构成的源区5上形成一层绝缘层，在绝缘层 外形成一隔离层，图形化该隔离层，只保留该绝缘层顶部的隔离层，以该隔离层为掩膜刻蚀两侧的绝缘层，移走剩下的隔离层的部分，形成上述第一绝缘层6。The specific process is to form an insulating layer on the source region 5 composed of a semiconductor material in the insulating layer. Forming an isolation layer outside, patterning the isolation layer, leaving only the isolation layer on the top of the insulation layer, etching the insulation layers on both sides with the isolation layer as a mask, and removing the remaining isolation layer to form the above An insulating layer 6.
步骤6：在该源区5的两侧形成外延层7。Step 6: Forming an epitaxial layer 7 on both sides of the source region 5.
如图8(g)沉积本征(n型)掺杂半导体层7，提供硬掩膜层8，并图形化硬掩膜层8露出绝缘层6表面的半导体层7，刻蚀掉露出的半导体层7；并移除剩下的硬掩膜层8，保留下来的半导体层7作为外延层7。The intrinsic (n-type) doped semiconductor layer 7 is deposited as shown in FIG. 8(g), the hard mask layer 8 is provided, and the hard mask layer 8 is patterned to expose the semiconductor layer 7 on the surface of the insulating layer 6, and the exposed semiconductor is etched away. Layer 7; and the remaining hard mask layer 8 is removed, and the remaining semiconductor layer 7 is used as the epitaxial layer 7.
即具体的实现时在源区5和第一绝缘层6的外侧提供一层本证掺杂的半导体层，提供硬掩膜层，图形化硬掩膜层，露出半导体源区顶部区域，刻蚀半导体源区顶部本征掺杂的半导体层，移除掩膜层，保留下来的半导体层为外延层7。That is, a specific implementation provides a layer of the doped semiconductor layer on the outer side of the source region 5 and the first insulating layer 6, providing a hard mask layer, patterning a hard mask layer, exposing the top region of the semiconductor source region, and etching The semiconductor layer is intrinsically doped at the top of the semiconductor source region, the mask layer is removed, and the remaining semiconductor layer is the epitaxial layer 7.
步骤8：在外延层7的外侧沉积栅电介质层9，并在栅电介质层9的外侧形成栅极材料10。Step 8: A gate dielectric layer 9 is deposited on the outside of the epitaxial layer 7, and a gate material 10 is formed on the outside of the gate dielectric layer 9.
如图8(h)，在外侧沉积栅电介质层9，可以使SiO2或者高K电介质层如HfO2等等；沉积栅极材料10，可以是多晶硅，金属等等。As shown in FIG. 8(h), the gate dielectric layer 9 is deposited on the outside, and SiO2 or a high-k dielectric layer such as HfO2 or the like may be formed; the gate material 10 may be deposited, which may be polysilicon, metal or the like.
步骤8：对栅电介质层9和栅极材料10进行刻蚀。Step 8: Etching the gate dielectric layer 9 and the gate material 10.
如图8(i)，刻蚀栅极材料10和栅电介质层9，露出源区顶部的第一绝缘层6。栅区高度和源区高度一致，是为了很好的控制源区载流子，因为如果源区高于或者低于栅区，会产生点隧穿和线隧穿混合机制，影响器件特性。As shown in Figure 8(i), the gate material 10 and the gate dielectric layer 9 are etched to expose the first insulating layer 6 at the top of the source region. The height of the gate region is consistent with the height of the source region for good control of the source region carriers, because if the source region is higher or lower than the gate region, a point tunneling and line tunneling mixing mechanism is generated, which affects device characteristics.
步骤9：在第一绝缘层6上形成漏区12。Step 9: A drain region 12 is formed on the first insulating layer 6.
如图8(j)，沉积低K电介质层11，并图形化(采用方法3的工艺技术)露出第一绝缘层6，并且该第一绝缘层6周围的电介质层11高于该第一绝缘层6。As shown in FIG. 8(j), a low-k dielectric layer 11 is deposited, and patterned (using the process technology of method 3) to expose the first insulating layer 6, and the dielectric layer 11 around the first insulating layer 6 is higher than the first insulating layer. Layer 6.
如图8(k)，在第一绝缘层6上部采用原位掺杂N++型半导体层形成漏区12。刻蚀多余的半导体层，保留绝缘层6顶部的半导体层作为漏区12。As shown in FIG. 8(k), a drain region 12 is formed on the upper portion of the first insulating layer 6 by in-situ doping of an N++ type semiconductor layer. The excess semiconductor layer is etched, and the semiconductor layer on top of the insulating layer 6 is left as the drain region 12.
即提供另一个电介质材料隔离位于栅区旁边，图形化该电介质材料隔离层中间部分，露出第一绝缘层，然后再露出该第一绝缘层的部分形成半导体层漏区，后续提供漏区电极直接连接漏区，提供源区电极直接源区，提供栅极电极直接连接栅区的栅极层。That is, another dielectric material isolation is provided beside the gate region, the intermediate portion of the dielectric material isolation layer is patterned, the first insulating layer is exposed, and then the portion of the first insulating layer is exposed to form a semiconductor layer drain region, and then the drain region electrode is directly provided. The drain region is connected, and the source region electrode direct source region is provided, and the gate electrode is directly connected to the gate layer of the gate region.
步骤10：沉积边墙，可以是硅氧化物，氮化硅，高K电介质或者其他绝 缘材料。再进行类似于CMOS工艺的金属接触等等工艺。(进行氩离子束刻蚀后，在表面进行Co和TiN离子束沉淀，接着进行快速退火工艺，然后去除氮化钛和钴，最后进行沉积钝化层，开接触孔以及金属化等等，形成完整晶体管)。Step 10: Deposit the sidewalls, which can be silicon oxide, silicon nitride, high-k dielectric or other Edge material. A metal contact or the like similar to a CMOS process is performed. (After argon ion beam etching, Co and TiN ion beam precipitation is performed on the surface, followed by rapid annealing process, then removing titanium nitride and cobalt, and finally depositing a passivation layer, opening contact holes, metallization, etc., forming Complete transistor).
注意：硬掩膜层材料可以是氧化硅材料或者氮化硅或者氮氧化硅材料等。Note that the hard mask layer material may be a silicon oxide material or a silicon nitride or silicon oxynitride material.
注意：以上步骤的沉积工艺，可以通过低压化学气相沉积(英文全称：Low Pressure Chemical Vapor Deposition，简称：LPCVD)或者物理气相沉积(英文全称：Physical Vapor Deposition，简称：PVD)等实现；外延工艺(分子束外延，LPCVD，CVD等)。Note: The deposition process of the above steps can be realized by low pressure chemical vapor deposition (English name: Low Pressure Chemical Vapor Deposition, LPCVD for short) or physical vapor deposition (English full name: Physical Vapor Deposition, PVD for short); Molecular beam epitaxy, LPCVD, CVD, etc.).
上述过程为制作本发明提供的隧穿场效应晶体管的详细工艺过程，图2-5所示的隧穿场效应晶体管可采用上述方法制造，另外，一种可选的制造方案中红，在形成源区结构时候，可将其制作成鳍条形状(参考图6中示出的源区的形状)，其他的结构上述方案相同。这将引入鳍式场效晶体管(英文全称：Fin Field-Effect Transistor，简称：FinFET)器件的鳍条制作工艺，可以是边墙转移工艺，也可以是光刻工艺等等，其他的工艺均相同，使用该方式可以能够进一步提高栅区对源区的控制能力。The above process is a detailed process for fabricating the tunneling field effect transistor provided by the present invention. The tunneling field effect transistor shown in FIG. 2-5 can be fabricated by the above method. In addition, an alternative manufacturing scheme in which red is formed When the source region is structured, it can be formed into a fin shape (refer to the shape of the source region shown in FIG. 6), and the other configurations are the same as described above. This will introduce the fin fabrication process of the Fin Field-Effect Transistor (FinFET) device, which can be a side wall transfer process or a photolithography process. Other processes are the same. By using this method, the control ability of the gate region to the source region can be further improved.
本实施例提供的隧穿场效应晶体管的制造方法，用于制造前述的隧穿场效应晶体管，源区位于双栅区之间，外延层位于源区和栅电介质层之间，栅极电场作用在源区和外延层，耗尽p-n结，随着外加栅偏压的作用，导致耗尽区域逐渐变大，进而完全耗尽。由于耗尽区的存在多子运动受阻，少数载流子运动活跃，而TFET是少子发生隧穿，因此导致SS值减小，且通过该第一绝缘层的隔离，有效降低了泄露电流，提高器件性能。另外，上述制造过程的工艺技术简单，能够于CMOS工艺兼容，不需要复杂工艺。The manufacturing method of the tunneling field effect transistor provided in this embodiment is used to manufacture the tunneling field effect transistor described above, wherein the source region is located between the double gate regions, and the epitaxial layer is located between the source region and the gate dielectric layer, and the gate electric field acts. In the source region and the epitaxial layer, the pn junction is depleted, and as the bias of the external gate is applied, the depletion region is gradually enlarged and completely depleted. Due to the existence of the depletion region, the multi-sub-motion is blocked, the minority carrier motion is active, and the TFET is the tunneling of the minority carrier, so the SS value is reduced, and the isolation of the first insulating layer effectively reduces the leakage current and improves Device performance. In addition, the above manufacturing process is simple in technology, compatible with CMOS processes, and does not require complicated processes.
本发明提供的器件结构中的源区结构可以用在任何基于TFET隧穿机理的晶体管结构中，降低亚阈值摆幅，并不只限于本发明的隧穿场效应晶体管。The source region structure in the device structure provided by the present invention can be used in any transistor structure based on the TFET tunneling mechanism to reduce the subthreshold swing, and is not limited to the tunneling field effect transistor of the present invention.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。 Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims (13)

  1. 一种隧穿场效应晶体管，其特征在于，包括：A tunneling field effect transistor, comprising:
    衬底层；Substrate layer
    源区，所述源区覆盖在所述衬底层的部分表面，所述源区为柱体形状；a source region, the source region covering a portion of the surface of the substrate layer, the source region being in the shape of a cylinder;
    第一绝缘层，所述第一绝缘层覆盖在所述源区远离所述衬底层的一端面上；a first insulating layer covering the one end surface of the source region away from the substrate layer;
    漏区，所述漏区覆盖在所述第一绝缘层远离所述源区的表面上；a drain region covering the surface of the first insulating layer away from the source region;
    第二绝缘层，所述第二绝缘层覆盖在所述衬底层上，位于所述源区周围，且所述第二绝缘层与所述源区接触；a second insulating layer overlying the substrate layer, located around the source region, and the second insulating layer is in contact with the source region;
    外延层，所述外延层覆盖在所述源区的侧面上，且所述外延层与所述第二绝缘层远离所述衬底层的表面接触；An epitaxial layer covering the side of the source region, and the epitaxial layer is in contact with a surface of the second insulating layer away from the substrate layer;
    栅区，所述栅区覆盖在所述外延层远离所述源区的表面上，所述栅区包括多个表面，其中两个表面分别与所述外延层和所述第二绝缘层接触；a gate region covering a surface of the epitaxial layer away from the source region, the gate region including a plurality of surfaces, wherein two surfaces are in contact with the epitaxial layer and the second insulating layer, respectively;
    所述第二绝缘层用于隔离所述栅区与所述衬底层；所述第一绝缘层和所述外延层用于隔离所述漏区与所述源区。The second insulating layer is used to isolate the gate region from the substrate layer; the first insulating layer and the epitaxial layer are used to isolate the drain region from the source region.
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述源区为原位P++掺杂的半导体材料，所述半导体材料为硅、锗硅、四族材料和三五族材料中任一种；掺杂浓度为1e18～1e21cm-3。The tunneling field effect transistor according to claim 1, wherein the source region is an in-situ P++ doped semiconductor material, and the semiconductor material is silicon, germanium silicon, a group of four materials, and a tri-five material. Any one; the doping concentration is 1e 18 to 1e 21 cm -3 .
  3. 根据权利要求1或2所述的隧穿场效应晶体管，其特征在于，所述漏区为原位N++掺杂的半导体材料。The tunneling field effect transistor of claim 1 or 2, wherein the drain region is an in situ N++ doped semiconductor material.
  4. 根据权利要求1至3任一项所述的隧穿场效应晶体管，其特征在于，所述衬底层的材料为硅、锗、SOI、GeOI，Ⅲ-Ⅴ族化合物材料中的任一种。The tunneling field effect transistor according to any one of claims 1 to 3, wherein the material of the substrate layer is any one of silicon, germanium, SOI, GeOI, and III-V compound materials.
  5. 根据权利要求1至4任一项所述的隧穿场效应晶体管，其特征在于，所述第一绝缘层的材料为SiO2、氮化硅或者硅的氮氧化物；所述第二绝缘层的材料为SiO2、氮化硅或者硅的氮氧化物。The tunneling field effect transistor according to any one of claims 1 to 4, wherein the material of the first insulating layer is oxynitride of SiO2, silicon nitride or silicon; and the second insulating layer The material is SiO2, silicon nitride or silicon oxynitride.
  6. 根据权利要求1至5任一项所述的隧穿场效应晶体管，其特征在于，所述栅区的高度小于或等于所述源区的高度。The tunneling field effect transistor according to any one of claims 1 to 5, wherein a height of the gate region is less than or equal to a height of the source region.
  7. 根据权利要求6所述的隧穿场效应晶体管，其特征在于，所述栅区包括栅电介质层和栅极；所述栅电介质层的材料为SiO2和/或HfO2。The tunneling field effect transistor according to claim 6, wherein the gate region comprises a gate dielectric layer and a gate; and the gate dielectric layer is made of SiO2 and/or HfO2.
  8. 一种隧穿场效应晶体管的制造方法，其特征在于，包括： A method for manufacturing a tunneling field effect transistor, comprising:
    形成衬底层；Forming a substrate layer;
    在所述衬底层上形成第二绝缘层；Forming a second insulating layer on the substrate layer;
    在所述第二绝缘层的中间区域开孔露出衬底层，并在所述开孔区域的衬底层上形成源区；所述源区为柱状形状；Opening a substrate layer in an intermediate portion of the second insulating layer, and forming a source region on the substrate layer of the opening region; the source region is a columnar shape;
    在所述源区上远离所述衬底层的另一端形成第一绝缘层；Forming a first insulating layer on the source region away from the other end of the substrate layer;
    在所述源区的侧面形成外延层；Forming an epitaxial layer on a side of the source region;
    在所述第一绝缘层和所述外延层的整体外侧形成栅区；Forming a gate region on an outer side of the first insulating layer and the epitaxial layer;
    去除所述栅区位于所述源区上部的部分以露出第一绝缘层；Removing a portion of the gate region located at an upper portion of the source region to expose the first insulating layer;
    在所述第一绝缘层和所述外延层的上部形成漏区。A drain region is formed on the first insulating layer and the upper portion of the epitaxial layer.
  9. 根据权利要求8所述的方法，其特征在于，所述在所述第二绝缘层的中间区域开孔露出衬底层，并在所述开孔区域的衬底层上形成源区，包括：The method according to claim 8, wherein the opening a hole in the intermediate portion of the second insulating layer to expose the substrate layer and forming the source region on the substrate layer of the opening region comprises:
    通过光刻技术在所述第二绝缘层的中间区域开孔露出衬底层；Opening a substrate layer in a middle portion of the second insulating layer by a photolithography technique;
    在所述第二绝缘层的开孔区域的衬底层上，形成由原位P++掺杂的半导体材料构成的源区。On the substrate layer of the open region of the second insulating layer, a source region composed of an in situ P++ doped semiconductor material is formed.
  10. 根据权利要求8或9所述的方法，其特征在于，所述在所述源区上远离所述衬底层的另一端形成第一绝缘层，包括：The method according to claim 8 or 9, wherein the forming the first insulating layer on the other end of the source region away from the substrate layer comprises:
    采用SiO2、氮化硅或者硅的氮氧化物在所述源区外部形成绝缘层，并对该绝缘层进行刻蚀只保留所述源区上远离所述衬底层的一端顶部的部分作为第一绝缘层；Forming an insulating layer on the outside of the source region using NOx, silicon nitride or silicon oxynitride, and etching the insulating layer to retain only a portion of the source region away from the top of one end of the substrate layer as the first Insulation;
    则所述在所述源区的侧面形成外延层，包括：Forming an epitaxial layer on a side of the source region, including:
    在所述源区的侧面沉积由本征掺杂半导体构成的半导体层，刻蚀所述半导体层露出所述第一绝缘层，将所述半导体层的剩余部分作为所述外延层。A semiconductor layer composed of an intrinsically doped semiconductor is deposited on a side of the source region, and the semiconductor layer is etched to expose the first insulating layer, and the remaining portion of the semiconductor layer is used as the epitaxial layer.
  11. 根据权利要求8至10任一项所述的方法，其特征在于，所述栅区包括电介质层和栅极；所述在所述第一绝缘层和所述外延层的整体外侧形成栅区，包括：The method according to any one of claims 8 to 10, wherein the gate region comprises a dielectric layer and a gate; and the gate region is formed on an outer side of the first insulating layer and the epitaxial layer, include:
    采用SiO2和/或HfO2材料在所述外延层的外部沉积电介质层，并采用多晶硅或者金属材料在所述电介质层外侧沉积栅极；Depositing a dielectric layer on the outside of the epitaxial layer using SiO2 and/or HfO2 material, and depositing a gate on the outside of the dielectric layer using polysilicon or a metal material;
    则所述去除所述栅区位于所述第一绝缘层上部的部分以露出第一绝缘层，包括：And removing the portion of the gate region located at an upper portion of the first insulating layer to expose the first insulating layer, including:
    刻蚀所述电介质层和所述栅极，露出所述第一绝缘层顶部的所述第一绝 缘层。Etching the dielectric layer and the gate to expose the first top of the first insulating layer Edge layer.
  12. 根据权利要求8至11任一项所述的方法，其特征在于，所述在所述第一绝缘层和所述外延层的上部形成漏区，包括：The method according to any one of claims 8 to 11, wherein the forming a drain region on an upper portion of the first insulating layer and the epitaxial layer comprises:
    在所述第一绝缘层和所述外延层上部沉积原位N++掺杂的半导体材料，并刻蚀所述半导体材料，只保留所述第一绝缘层和所述外延层上部的部分作为所述漏区。Depositing an in-situ N++ doped semiconductor material on the first insulating layer and the epitaxial layer, and etching the semiconductor material, leaving only the first insulating layer and a portion of the upper portion of the epitaxial layer as the Drain zone.
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：The method of claim 12, wherein the method further comprises:
    采用硅氧化物、氮化硅或高介电常数的电介质沉积边墙，形成隧穿场效应晶体管。 A tunneling field effect transistor is formed by using silicon oxide, silicon nitride or a high dielectric constant dielectric deposition sidewall.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085672A (en) * 2019-04-19 2019-08-02 宁波大学 A kind of TFET device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853824B1 (en) * 2013-09-19 2014-10-07 National Chiao Tung University Enhanced tunnel field effect transistor
CN104701374A (en) * 2013-12-10 2015-06-10 中芯国际集成电路制造(上海)有限公司 Tunneling field effect transistor and forming method thereof
CN105097820A (en) * 2014-05-16 2015-11-25 台湾积体电路制造股份有限公司 Memory device and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5652827B2 (en) * 2009-09-30 2015-01-14 国立大学法人北海道大学 Tunnel field effect transistor and manufacturing method thereof
US8890118B2 (en) * 2010-12-17 2014-11-18 Intel Corporation Tunnel field effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853824B1 (en) * 2013-09-19 2014-10-07 National Chiao Tung University Enhanced tunnel field effect transistor
CN104701374A (en) * 2013-12-10 2015-06-10 中芯国际集成电路制造(上海)有限公司 Tunneling field effect transistor and forming method thereof
CN105097820A (en) * 2014-05-16 2015-11-25 台湾积体电路制造股份有限公司 Memory device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085672A (en) * 2019-04-19 2019-08-02 宁波大学 A kind of TFET device

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