KR20150016769A - Tunneling Field Effect Transistor and Manufacturing Method thereof - Google Patents

Tunneling Field Effect Transistor and Manufacturing Method thereof Download PDF

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KR20150016769A
KR20150016769A KR1020130092634A KR20130092634A KR20150016769A KR 20150016769 A KR20150016769 A KR 20150016769A KR 1020130092634 A KR1020130092634 A KR 1020130092634A KR 20130092634 A KR20130092634 A KR 20130092634A KR 20150016769 A KR20150016769 A KR 20150016769A
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layer
channel
source
drain
gate
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강인만
서재화
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경북대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7311—Tunnel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Disclosed are a tunneling field effect transistor and a manufacturing method thereof. The tunneling field effect transistor according to the present invention includes a buffer layer, a source layer which is vertically arranged on the upper side of the buffer layer and is composed of a nanowire, a channel layer which is arranged to surround the upper and lateral sides of the nanowire, a drain layer which is arranged on the preset region of the upper side of the channel layer, a gate insulation layer which is arranged on the upper side of the buffer layer and surrounds the lateral side of the channel layer, and a gate layer which is formed in a direction which is orthogonal to the nanowire and surrounds the gate insulation layer.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a tunneling field effect transistor,

The present invention relates to a tunneling field effect transistor and a method of manufacturing the tunneling field effect transistor, and more particularly, to a tunneling field effect transistor in which a tunneling current can be increased by increasing a surface where a channel layer and a source layer contact with each other through a three- And a manufacturing method thereof.

As the size of the semiconductor device is reduced and the performance is improved, power consumption is increased at the opposite level. However, miniaturization of MOSFETs has been limited in semiconductor devices, and conventional MOSFETs have a physical limit that the subthreshold swing (SS) can not be lowered below 60 mV / dec at room temperature, There has been a fundamental problem that significant performance degradation occurs on the ground.

Therefore, there is a need to develop a device to replace or complement the conventional MOSFET. As a solution to this problem, a tunneling element used mainly in oscillator circuits has been spotlighted.

Specifically, the tunneling field effect transistor controls the flow of electrons and holes by a tunneling method, which is different from the thermionic emission of an existing MOSFET, so that a minute change in the input voltage (drive voltage) can lead to a large change in the output current .

This implies that the change of ON / OFF state occurs very abruptly according to the change of the gate voltage, and it means that a lower threshold voltage (SS) is possible.

Therefore, it is expected that the tunneling field effect transistor will be able to operate normally even at a very low driving voltage of 1 V or less. Therefore, using the tunneling transistor, it is possible to obtain similar performance to the conventional MOSFET while consuming less power, Tunneling field effect transistors have been expected to be realized.

Such a tunneling field effect transistor is basically a planar type tunneling phenomenon at the interface between the drain region and the channel region, as shown in FIG. 1, and thus the transistor operates.

However, such a planar tunneling field effect transistor has a disadvantage in that the current level is low because the tunneling phenomenon that determines the amount of actual current is limited due to the two-dimensional structure.

Patent No. 10-1232159

It is an object of the present invention to provide a tunneling field effect transistor in which a tunneling current can be increased by increasing a surface in contact with a channel layer and a source layer through a three-dimensional structure and a manufacturing method thereof There is.

According to an aspect of the present invention, there is provided a tunneling field effect transistor comprising: a source layer including a buffer layer and nanowires arranged vertically above the buffer layer; a channel layer disposed on the upper surface and the side surface of the nanowire; A drain layer disposed on a predetermined region of the upper surface of the channel layer, a gate insulating layer disposed on the buffer layer and surrounding the side surface of the channel layer, a gate insulating layer formed in a direction orthogonal to the nanowire, And a gate layer disposed surrounding the layer.

In this case, at least one of the nanowire, the channel layer, the gate insulating layer, and the gate layer may have a cylindrical structure.

On the other hand, the source layer, the channel layer, and the drain layer are doped with P + , P -, and N + types, respectively, and tunneling phenomenon may occur on the surface where the source layer and the channel layer are in contact with each other.

In this case, the source layer, the channel layer, and the drain layer may be silicon doped with P + , P -, and N + type, respectively.

Meanwhile, the channel layer may surround the side surface of the nanowire with a thickness of 3 nm or more and 5 nm or less.

A method of fabricating a tunneling field effect transistor includes forming a source layer of a buffer layer and a nanowire vertically disposed on the buffer layer, forming a channel material layer on the source layer, Forming a drain material layer above the material layer, etching the channel material layer and the drain material layer to form a channel layer surrounding the top and side surfaces of the nanowire, and a drain disposed in a predetermined region of the top surface of the channel layer, Forming a gate insulating layer and a gate layer surrounding the side surface of the channel layer.

In this case, the step of forming the gate insulating layer and the gate layer may include etching the drain layer formed on the upper surface of the channel layer to a predetermined size, disposing the buffer layer on the buffer layer, Forming the gate insulating layer, and forming a gate layer formed in a direction perpendicular to the nanowires to surround the gate insulating layer.

In this case, the method of manufacturing a tunneling field effect transistor according to the present invention includes the steps of forming a gate electrode in contact with the gate layer, forming a source electrode in contact with the buffer layer, and forming a drain electrode disposed in contact with the drain layer Step < / RTI >

Meanwhile, the forming of the source layer may include forming a source material layer and patterning the source material layer into a predetermined shape to form the nanowire.

At least one of the nanowire, the channel layer, the gate insulating layer, and the gate layer may have a cylindrical structure.

On the other hand, the source layer, the channel layer, and the drain layer are doped with P + , P -, and N + types, respectively, and tunneling phenomenon may occur on the surface where the source layer and the channel layer are in contact with each other.

In this case, the source layer, the channel layer, and the drain layer may be silicon doped with P + , P -, and N + type, respectively.

Meanwhile, the channel layer may surround the side surface of the nanowire with a thickness of 3 nm or more and 5 nm or less.

According to the tunneling field effect transistor and the method of manufacturing the same according to the present invention, a tunneling field effect transistor having an increased tunneling current than a conventional planar type can be obtained by a relatively simple process.

FIG. 1 illustrates a conventional planar-type tunneling field-effect transistor,
FIG. 2 illustrates a tunneling field effect transistor according to an embodiment of the present invention. FIG.
FIGS. 3 to 12 illustrate a method of manufacturing a tunneling field effect transistor according to an embodiment of the present invention. FIGS.
13 is a current-voltage curve according to a change in length t epi of the tunneling field effect transistor 100 according to an embodiment of the present invention, and
FIG. 14 shows a current-voltage curve according to the H source length change of the tunneling field effect transistor 100 according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a structure of a tunneling field effect transistor according to an embodiment of the present invention.

2, a tunneling field effect transistor 100 includes a source layer 110 including a buffer layer 113 and a nanowire 115, a channel layer 130, a drain layer 150, a gate insulating layer 170 A gate layer 190, a gate electrode 210, a source electrode 230, and a drain electrode 250.

When the electric field is applied to the gate layer 190, the band gap of the energy band between the source layer 110 and the channel layer 130 becomes thinner, It is a transistor with the principle that the current flows by the dynamic tunneling phenomenon.

The source layer 110 includes the buffer layer 113 and the nanowires 115 and may be referred to as a substrate since it functions as a substrate in the present device.

Considering that the source region is grounded in the semiconductor device, the source layer 110 may be disposed below the tunneling field effect transistor 100 as shown in FIG.

Specifically, the source layer 110 includes a buffer layer 113 and nanowires 115 vertically disposed on the buffer layer. The buffer layer 113 and the nanowires 115 are made of the same material.

The term " nanowire " as used in this detailed description is only adopted for convenience of explanation of the tunneling field effect transistor according to the present invention, and the term " nanowire " And the like are not limited or limited. Any vertical columnar structure (or protruding structure) suitable for the tunneling field effect transistor in accordance with the present invention may be implemented as nanowire 115.

Source layer 110 is a P + ion implantation may be configured with a P + type doped silicon is formed by, and can be specifically doped with 10 20 atoms / cm -3 concentration.

The source layer 110 may serve to supply carriers (electrons or holes) to the tunneling field effect transistor 100.

The nanowire 115 of the source layer 110 may be a cylindrical structure with a diameter of 10 nm. By having such a nano-size, the tunneling field effect transistor 100 according to the present invention can contribute to the miniaturization of semiconductor devices.

As the length of the nanowire 115 is increased, the area in which the source region and the channel region contact each other can be widened, so that a high on-state current ( I on ) can be obtained. Therefore, the length of the tunneling phenomenon represented by H source in FIG. 2 may be 20 nm or more, more specifically 70 nm or more.

The operation current characteristics according to the H source length change will be described later with the graph shown in FIG.

Channel layer 130 is placed surrounding the top and sides of the nanowire (115), P - type or N - may be composed of a silicone-type doping, specifically doped with 10 16 atoms / cm -3 concentration Lt; / RTI >

2, the channel layer 130 may have a cylindrical structure in which the nanowires 115 in a cylindrical shape are surrounded by 360 degrees.

If the tunneling phenomenon occurs only in one direction in the conventional two-dimensional tunneling field effect transistor (see FIG. 1), the tunneling field effect transistor 100 according to an embodiment of the present invention can prevent the tunneling phenomenon by 360 degrees And can have a high operating current.

2, the tunneling phenomenon can be more easily generated at the interface between the source layer 110 and the channel layer 130 as the thickness of the channel layer 130 expressed by t epi is smaller. Therefore, the tunneling field effect transistor 100 according to an embodiment of the present invention may have a thickness of 3 nm or more and 5 nm or less.

The operating current characteristics according to the change in thickness tepi will be described later with the graph shown in Fig.

The drain layer 150 is disposed in a predetermined region on the upper surface of the channel layer 130. Referring to FIG. 2, the predetermined region is an area on the upper surface of the channel layer 130 in which the outer periphery of the region occupied by the drain layer 150 belongs to the inside of the outer periphery of the channel layer 130.

By disposing the drain layer 150 so as to be smaller than the upper width of the channel layer 130, the tunneling phenomenon can be prevented at the junction between the channel layer 130 and the drain layer 150. As a result, The current flow (leakage current) due to the tunneling phenomenon between the drain layer 130 and the drain layer 150 can be minimized.

The drain layer 150 may be made of N + type doped silicon, and may be doped with a concentration of 10 18 atoms / cm -3 .

The carrier supplied from the source layer 110 can act as a passageway to generate a drain current so as to pass to the external device.

The gate insulating layer 170 is disposed on the buffer layer 113 and surrounds the side surface of the channel layer 130.

2, the gate insulating layer 170 is disposed in a cylindrical shape covering the top surface of the buffer layer 113 while surrounding the channel layer 130 in a cylindrical shape at 360 degrees.

The gate insulating layer 170 isolates the gate layer 190 from the channel layer 130 and may be formed of silicon oxide (SiO 2 ). On the other hand, although silicon oxide is used as an insulating material in this embodiment, other oxides may be used in the implementation.

Specifically, the thickness of the gate insulating layer 170 should be thin so that the gate voltage can be appropriately applied to the channel layer 130, and at the same time, the leakage current between the gate layer 190 and the channel layer 130 It should be thick enough to be thick enough.

The gate layer 190 is formed in a direction orthogonal to the nanowires 115 and is disposed surrounding the gate insulating layer 170.

2, the gate layer 190 is disposed in a cylindrical shape surrounding the gate insulating layer 170 in a region where the channel layer 130 is formed.

Specifically, the structure in which the gate layer 190 surrounds the channel layer 130 is referred to as a gate all around structure (GAA). In the form having the GAA structure, the nano-sized channel layer 130 can achieve fully depletion even when the gate voltage is not applied and has a normally off characteristic, There is an advantage that there is almost no current. In addition, when a gate voltage is applied, the current can be accumulated in the nano-sized channel layer 130 in all 360 degrees directions, so that the current can flow more than in a two-dimensional structure of the same size . In this respect, the GAA structure of the tunneling field-effect transistor 100 according to an embodiment of the present invention is a structure suitable for a miniaturized semiconductor device.

When an electric field is applied to the gate layer 190 through the gate electrode 210, the bandgap of the energy band between the source layer 110 and the channel layer 130 becomes thin, and the tunneling effect is caused through the thinned band gap .

The gate layer 190 may be formed of a metal such as tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), nickel (Ni)

The gate electrode 210 is disposed adjacent to the gate layer 190 and allows voltage to be applied to the gate layer 190 from the outside. The gate electrode 210 may be made of the same material as the gate layer 190.

The source electrode 230 is disposed in contact with the buffer layer 113. Specifically, the source electrode 230 may be disposed on the buffer layer 113 of the first source layer 110 to supply a carrier to the source layer 110.

The drain electrode 250 is disposed in contact with the drain layer 150. Specifically, the drain electrode 250 may serve to electrically connect the carrier supplied from the source electrode 230 to an external device so as to be transferred to the external device.

The source electrode 230 and the drain electrode 250 may be formed of a metal such as tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au)

The tunneling field effect transistor 100 according to an embodiment of the present invention has been described above. The tunneling field effect transistor 100 according to an exemplary embodiment of the present invention will now be described.

The method of forming the respective layers to be described below can be performed by various methods such as MBE, ALD, MOCVD, PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method and resistance heating method.

FIGS. 3 to 12 are views illustrating a method of manufacturing the tunneling field effect transistor 100 according to an embodiment of the present invention.

Referring to FIG. 3, a source material layer 111 is first formed. Here, the source material layer 111 is etched in the next process, resulting in the source material layer 110, so that the source material layer 111 is named.

Specifically, the source material layer 111 may be formed of P + type doped silicon formed by P + ion implantation, more specifically doped to a concentration of 10 20 atoms / cm -3 .

Referring next to FIG. 4, the source material layer 111 is patterned into a predetermined shape to form the nanowire. That is, the source material layer 111 is etched leaving only the portion where the nanowire 115 is to be formed. The etching can be performed by an IBE (Ion Beam Etching) method.

Specifically, the nanowires 115 are patterned and etched to have a cylindrical structure with a diameter of 10 nm. Then, the nanowire 115 is etched to have a length of 20 nm or more, specifically, 70 nm or more. This etching results in the formation of a source layer 110 as shown in Fig.

According to the method of forming the nanowires 115 by the top-down as described above, it is relatively easy to form the nanowires without forming the process conditions (pressure or temperature) exactly like the method of forming the nanowires by the bottom- (115) structure can be formed.

5, a channel material layer 131 is formed on top of the source layer 110. [ Here, the channel material layer 131 is referred to as a channel material layer 131 because it becomes a channel layer 130 through a subsequent etching process.

Specifically, the channel material layer 131 may be made of P - type doped silicon, more specifically doped to a concentration of 10 16 atoms / cm 3 .

6, a drain material layer 151 is formed on the channel material layer 131. [ Hereinafter, the drain material layer 151 is referred to as a drain material layer 151 since it is a drain layer 150 through a subsequent etching process.

Specifically, the drain material layer 151 may be made of N + type doped silicon, and more specifically doped to a concentration of 10 18 atoms / cm -3 .

7, the channel layer 130 and the drain material layer 151 are etched at the same time to form a channel layer 130 and a drain layer 150. Referring to FIG.

Specifically, the channel layer 130 is patterned and etched into a cylindrical structure such that the thickness t epi of the channel region 130 where the nanowires 115 are located is 3 nm or more and 5 nm or less. The etching can be performed by an IBE (Ion Beam Etching) method.

According to the method of simultaneously etching the channel material layer 131 and the drain material layer 151 as described above, the process can be simplified compared to the case where the channel layer 130 and the drain layer 150 are formed separately .

 Referring next to FIG. 8, the drain layer 150 is etched to a predetermined size. More specifically, the drain layer 150 may be etched using an IBE (Ion Beam Etching) method.

8A and 8B, the outer diameter of the region of the drain layer 150 is smaller than that of the region of the channel layer 130 so as to minimize the contact between the gate layer 190 and the drain layer 150, It is the size set to come in.

By etching the drain layer 150 to a predetermined size, the tunneling phenomenon can be prevented at the junction between the channel layer 130 and the drain layer 150. As a result, in the off state, the channel layer 130 and the drain layer (Leakage current) due to the tunneling phenomenon between the source and drain electrodes 150 and 150.

Referring to FIG. 9, a gate insulating layer 170 is disposed on the buffer layer 113 and surrounds the side surface of the channel layer 130.

The gate insulating layer 170 isolates the gate layer 190 from the channel layer 130 and may be formed of silicon oxide (SiO 2 ). On the other hand, although silicon oxide is used as an insulating material in this embodiment, other oxides may be used in the implementation.

9, the gate insulating layer 170 is deposited to cover the upper surface of the buffer layer 113 while surrounding the channel layer 130 and the drain layer 150 in a cylindrical shape at 360 degrees.

10, the gate insulating layer 170 is etched so that the gate insulating layer 170 is shaped to thinly surround the channel layer 130. In this case, More specifically, the gate insulating layer 170 may be etched by an IBE (Ion Beam Etching) method.

The reason why the gate insulating layer 170 is etched as shown in FIG. 10 is to allow the gate voltage to be appropriately applied to the channel layer 130. At the same time, the thickness of the gate insulating layer 170 surrounding the channel layer 130 should be sufficiently thick to prevent leakage current between the gate layer 190 and the channel layer 130.

In addition, the upper surface of the drain layer 150 is exposed to the outside through a chemical mechanical polishing (CMP) process, as shown in FIG. This is for electrically joining the drain layer 150 and the drain electrode 250.

Referring to FIG. 11, a gate layer 190 is formed in a direction perpendicular to the nanowires 115 to surround the gate insulating layer 170.

The gate layer 190 may be comprised of polysilicon. Specifically, the gate layer 190 is formed in a form (GAA structure) in which the gate insulating layer 170 is surrounded by 360 degrees.

A gate electrode 210 disposed in contact with the gate layer 190, a source electrode 230 disposed in contact with the buffer layer 113, and a drain electrode 250 disposed in contact with the drain layer 150 are formed as a metal The tunneling field effect transistor 100 may be formed as shown in FIG.

FIG. 13 shows a current-voltage curve according to a change in the t epi length of the tunneling field-effect transistor 100 according to an embodiment of the present invention.

Specifically, a current-voltage curve (SS = 60 [mV / dec]) of a conventional planar structure tunneling field effect transistor with a gate length of 60 nm was shown together and used as a comparison standard.

As shown in FIG. 13, it can be seen that the operating current (on-current) is increased as the length of t epi decreases, and the SS (subthreshold swing) is improved due to the increase of the threshold voltage.

As a result, when considering the possibility of side step, the appropriate t epi As a value, you will be able to select 3-5 nm.

FIG. 14 shows a current-voltage curve according to the H source length change of the tunneling field effect transistor 100 according to an embodiment of the present invention. Specifically, FIG. 14 shows the current-voltage curve according to the change of H source in the condition of 3 nm t epi derived under the optimal condition in FIG.

Since the increase of the H source is directly related to the increase of the region where the tunneling occurs, that is, the region where the channel layer 130 and the source layer 110 are in contact with each other, the current value is proportional to the increase of the H source as shown in FIG. As shown in Fig. In other words, it is understood that, in the implementation of the tunneling field-effect transistor 100 of the present invention, the length of the nanowire 115 of the source layer 110 is made as long as possible to increase the amount of current.

100: tunneling field effect transistor 110: source layer
130: channel layer 150: drain layer
170: gate insulating layer 190: gate layer

Claims (13)

In a tunneling field effect transistor,
A source layer comprising a buffer layer and a nanowire disposed vertically above the buffer layer;
A channel layer surrounding the top and side surfaces of the nanowire;
A drain layer disposed in a predetermined region of the upper surface of the channel layer;
A gate insulating layer disposed on the buffer layer and surrounding the side surface of the channel layer;
And a gate layer formed in a direction orthogonal to the nanowires and surrounding the gate insulating layer. The method according to claim 1,
Wherein at least one of the nanowire, the channel layer, the gate insulating layer, and the gate layer is a cylindrical structure. The method according to claim 1,
The source layer, the channel layer, and the drain layer are doped with P + , P -, and N + type, respectively,
Wherein a tunneling phenomenon occurs on a surface where the source layer and the channel layer are in contact with each other. The method of claim 3,
Wherein the source layer, the channel layer, and the drain layer are silicon doped with P + , P -, and N + type, respectively. The method according to claim 1,
Wherein the channel layer comprises:
And a side surface of the nanowire is surrounded with a thickness of 3 nm or more and 5 nm or less. A method of manufacturing a tunneling field effect transistor,
Forming a source layer of a buffer layer and a nanowire vertically disposed on the buffer layer;
Forming a channel material layer over the source layer;
Forming a layer of drain material over the channel material layer;
Etching the channel material layer and the drain material layer to form a channel layer surrounding the top and side surfaces of the nanowire and a drain layer disposed in a predetermined region of the top surface of the channel layer;
And forming a gate insulating layer and a gate layer surrounding the side surface of the channel layer. The method according to claim 6,
Wherein forming the gate insulating layer and the gate layer comprises:
Etching the drain layer formed on the upper surface of the channel layer to a predetermined size;
Forming a gate insulating layer disposed on the buffer layer and surrounding a side surface of the channel layer;
And forming a gate layer in a direction perpendicular to the nanowires to surround the gate insulating layer. ≪ Desc / Clms Page number 21 > 8. The method of claim 7,
Forming a gate electrode in contact with the gate layer;
Forming a source electrode in contact with the buffer layer; And
And forming a drain electrode in contact with the drain layer. ≪ Desc / Clms Page number 21 > The method according to claim 6,
Wherein forming the source layer comprises:
Providing a source material layer; And
And patterning the source material layer in a predetermined pattern to form the nanowire. ≪ Desc / Clms Page number 21 > The method according to claim 6,
Wherein at least one of the nanowire, the channel layer, the gate insulating layer, and the gate layer is a cylindrical structure. The method according to claim 6,
The source layer, the channel layer, and the drain layer are doped with P + , P -, and N + type, respectively,
Wherein a tunneling phenomenon occurs on a surface where the source layer and the channel layer are in contact with each other. 12. The method of claim 11,
Wherein the source layer, the channel layer, and the drain layer are silicon doped with P + , P -, and N + type, respectively. The method according to claim 6,
Wherein the channel layer comprises:
Wherein the side surface of the nanowire is surrounded with a thickness of 3 nm or more and 5 nm or less.

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CN107799607A (en) * 2017-10-31 2018-03-13 沈阳工业大学 Conduction type is adjustable, and source and drain resistive formula bilateral folds gate transistor and its manufacture method
CN107819027A (en) * 2017-10-31 2018-03-20 沈阳工业大学 A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method
CN108987477A (en) * 2017-06-02 2018-12-11 三星电子株式会社 Vertical tunneling field-effect transistor and its manufacturing method
KR20190079486A (en) * 2017-12-27 2019-07-05 삼성전자주식회사 Vertical field effect transistor having two-dimensional channel structure
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