CN107819027A - A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method - Google Patents
A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method Download PDFInfo
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- 230000004888 barrier function Effects 0.000 claims abstract description 54
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 82
- 239000010409 thin film Substances 0.000 claims description 80
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- 238000005530 etching Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
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- 238000005036 potential barrier Methods 0.000 claims description 4
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- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
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Abstract
The present invention relates to a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method, device of the present invention has H-shaped gate electrode and symmetrical architectural feature, with stronger grid control ability and by adjusting the interchangeable electrode voltage of source and drain the interchangeable area of metal source and drain can be controlled to be used as source region or drain region, change tunnelling current direction.The advantages of present invention has low speed paper tape reader static power disspation and reverse leakage current, stronger grid control ability, low subthreshold swing and can realize two-way switch function.In contrast to common MOSFETs types device, more excellent switching characteristic is realized using tunneling effect；In contrast to common tunneling field-effect transistor, in contrast to Schotthy barrier transistor, there is more preferable switching characteristic, the present invention need not be doped in source-drain area, Schottky barrier is easily formed, and source-drain area can be better controlled for H-shaped gate electrode, therefore is adapted to popularization and application.
Description
Technical field
The present invention relates to super large-scale integration manufacturing field, and in particular to one kind is applied to low power consumption integrated circuit system
The source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method with low current leakage made.
Background technology
The elementary cell MOSFETs of integrated circuit must become less and less, produce therewith according to the requirement of Moore's Law, size
The problem of raw, is not only the increase of difficulty in manufacturing process, and device itself is various by size diminishes triggered ill effect
All the more highlight.Nowadays itself produces the physics of electric current when MOSFETs types device is due to its work used by IC design
The limitation of mechanism, its subthreshold swing cannot be below 60mV/dec all the time.
It is common wear utilized when field-effect transistor uses as switching-type device be carrier tunneling mechanism, can make general
The subthreshold swing of logical tunneling field-effect transistor is better than the 60mV/dec limit of MOSFETs type devices.However, it is based on silicon substrate
The tunneling field-effect transistor of material, because energy gap limits, tunnelling probability is limited, contrasts MOSFETs type devices, it is difficult to produce
The conducting electric current of raw same order, more seriously, the miscellaneous of different conduction-types is respectively adopted in its source electrode and drain electrode
Matter is doped, the unsymmetric structure feature formed cause its source electrode and drain electrode can not real tunnel now exchange mutually, because
This can not functionally substitute the MOSFETs type devices with symmetrical structure feature completely.Using N-type tunneling field-effect transistor as
Example, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunneling field-effect crystal now
Pipe, by the PN junction that source and drain is formed always belongs to forward bias condition, then gate electrode now can not well control conducting electric current
Size so that whole tunneling field-effect transistor failure.
Schottky barrier field effect transistor, by the use of Schottky barrier tunnelling as conducting mechanism, due to tunneling barrier height
Bigger tunnelling probability can be achieved less than the energy gap of tunnel field-effect transistor in degree, and by the use of metal as incidence end,
It is can be achieved under equal area size than semiconductor conduction band or the more electron impact amounts of valence band, and then obtain bigger tunnel-effect
Current density, therefore the conducting current density higher than tunneling field-effect transistor can be obtained.But common Schottky gesture
It is the gate electrode switching characteristic for realizing device to build field-effect transistor（Reversely cut-off or reverse-conducting are positive for gate electrode forward conduction
Cut-off）, the impurity doping of specific conductivity type is carried out to the source region of device or drain region, this in technique to be difficult in source electricity
Between pole and source region, good Schottky contacts are realized between drain electrode and drain region, and the doping to source region and drain region causes grid
The control ability of electrode pair drain region and source region reduces, and causes the switch performance of device to decline.If not to the semiconductor regions of device
Doping, though the Schottky barrier between source electrode and source region, drain electrode and drain region is then easily achieved in technique, but this can make
Obtain device and produce different types of carrier conducting in forward and reverse, i.e., can make under gate electrode forward bias and reverse biased
It is in the conduction state to obtain device, so that grid loses the control action as devices switch device.
The content of the invention
Goal of the invention
In contrast to current MOSFETs technologies, tunneling transistor technology and Schotthy barrier transistor technology, to realize device simultaneously
Working characteristics with low subthreshold swing, high forward conduction electric current, source electrode, electric leakage with such as MOSFETs devices
Extremely interchangeable logic function, make up current MOSFETs, tunneling transistor and Schotthy barrier transistor technology it is a variety of on
Inferior position is stated, the present invention proposes a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacture method.The transistor has
Logic function has source-drain electrode interchangeable two-way with being currently based on the completely compatible advantageous feature of MOSFETs integrated circuits
Switching characteristic, forward and reverse electric current are than working characteristics such as high and low subthreshold swing, high forward conduction electric currents.
Technical scheme
The present invention is achieved through the following technical solutions：
A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, the silicon substrate comprising SOI wafer, it is characterised in that：SOI is brilliant
Be the insulated substrate layer of SOI wafer above round silicon substrate, the top of the insulated substrate layer of SOI wafer for monocrystalline silicon thin film, again
Doped region；Monocrystalline silicon thin film has U-shaped structure feature, is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material；It is heavily doped
Miscellaneous area is located at the intermediate region of the bottom horizontal portion of monocrystalline silicon thin film U-shaped structure, the conduction type resolver of its impurity
The conductivity type of part, do not influenceed to control by H-shaped gate electrode field-effect inside it, be not less than 10 for impurity concentration17cm-3Partly lead
Body material；The interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain are made up of metal material, respectively positioned at monocrystalline silicon thin film
The upper middle portion of the both sides vertical component of the U-shaped structure formed；The interchangeable area a of metal source and drain front and rear surfaces and inner side
Surface contacts with each other with the interchangeable intrinsic region a of source and drain, and by thirdly face surrounds, contact surface forms Schottky barrier；Metal source and drain
Interchangeable area a bottom contacts with each other with monocrystalline silicon thin film, and contact surface forms Schottky barrier；The interchangeable area b's of metal source and drain
Front and rear surfaces and inner surface contact with each other with the interchangeable intrinsic region b of source and drain, and by thirdly face surrounds, contact surface forms Schottky
Potential barrier；The interchangeable area b of metal source and drain bottom contacts with each other with monocrystalline silicon thin film, and contact surface forms Schottky barrier；Source and drain can
Exchange the upper zone that the intrinsic region a and interchangeable intrinsic region b of source and drain is located at the both sides vertical component of monocrystalline silicon thin film U-shaped structure respectively
The front and rear surfaces and inner surface in domain, it is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material；It is monocrystalline silicon thin film, heavily doped
Miscellaneous area, the interchangeable intrinsic region a of source and drain, the interchangeable intrinsic region b of source and drain, the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain
A U-shaped structure is collectively constituted；Grid electrode insulating layer be located at monocrystalline silicon thin film U-shaped structure bottom horizontal portion upper surface and
The inner surface and front and rear surfaces of front and rear surfaces and monocrystalline silicon thin film U-shaped structure both sides vertical component；H-shaped gate electrode is by metal
Material or polycrystalline silicon material are formed, to the inner surface and front and rear surfaces shape of the both sides vertical component of monocrystalline silicon thin film U-shaped structure
Wrapped up in into three bread, overlook SOI wafer, H-shaped gate electrode is in English capitalization H shape, H-shaped gate electrode and monocrystalline along source and drain direction
It is insulated from each other by grid electrode insulating layer between silicon thin film U-shaped structure, H-shaped gate electrode positioned at monocrystalline silicon thin film U-shaped structure it is recessed
The subregion with insulating medium barrier layer, H-shaped gate electrode are only right between groove inboard portion lower surface and grid electrode insulating layer
The front and rear surfaces and inner surface of the upper area of the both sides vertical component of monocrystalline silicon thin film U-shaped structure, i.e., to interchangeable of source and drain
The area a and interchangeable intrinsic region b of source and drain is levied by obvious field-effect control action, and it is vertical to the both sides of monocrystalline silicon thin film U-shaped structure
Partial lower zone and the bottom horizontal portion region of monocrystalline silicon thin film U-shaped structure do not have obvious field-effect control action；
The interchangeable electrode a of source and drain is made up of metal material, positioned at the interchangeable area a of metal source and drain top；The interchangeable electrode b of source and drain also by
Metal material is formed, positioned at the interchangeable area b of metal source and drain top, the interchangeable electrode a of source and drain, the interchangeable electrode b of source and drain and H-shaped
It is insulated from each other by insulating medium barrier layer between these three electrodes of gate electrode；The left and right sides of heavily doped region is in symmetrical structure,
Same output characteristics can be realized in the case where the interchangeable electrode a of the source and drain and interchangeable electrode b of source and drain is symmetrically exchanged.
A kind of manufacture method of the source and drain resistive formula H-shaped grid-control two-way switch transistor, it is characterised in that：
Its manufacturing step is as follows：
Step 1：One SOI wafer is provided, bottom is the silicon substrate of SOI wafer, is insulated substrate layer above silicon substrate,
The upper surface of insulated substrate layer is monocrystalline silicon thin film, and by ion implanting or diffusion technique, the monocrystalline silicon above SOI wafer is thin
The intermediate region doping of film, preliminarily forms heavily doped region；
Step 2：Part monocrystalline silicon thin film and heavily doped region are removed by photoetching, etching technics, monocrystalline is formed in SOI wafer
Silicon thin film and heavily doped region；
Step 3：The intermediate projections at left and right sides of the monocrystalline silicon thin film of bottom and the upper surface of heavily doped region and monocrystalline silicon thin film
Partial outer surface, by aoxidizing or depositing, etching technics, form grid electrode insulating layer；
Step 4：By depositing technics, dielectric is deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film
Upper surface, preliminarily form SI semi-insulation dielectric barrier；
Step 5：By etching technics, partial etching, further shape are carried out to the insulating medium barrier layer deposited in step 4
Into insulating medium barrier layer；
Step 6：Metal or polysilicon are deposited above SOI wafer, planarizes surface to the upper surface for exposing monocrystalline silicon thin film,
Form H-shaped gate electrode；
Step 7：By etching technics, the upper surface intermediate region of the left and right sides vertical component of monocrystalline silicon thin film is carved
Erosion, then by depositing technics, deposit metal in SOI wafer upper surface, metal is formed Xiao Te with monocrystalline silicon thin film contact portion
Base potential barrier, surface to the upper surface for exposing monocrystalline silicon thin film is planarized, form the interchangeable area a of metal source and drain and metal source and drain can be mutual
Change area b；
Step 8：By depositing technics, dielectric is deposited above SOI wafer, the dielectric for forming remainder stops
Layer；Pass through the insulation above the interchangeable area a and interchangeable area b of metal source and drain of etching technics removal metal source and drain behind planarization surface
Dielectric barrier to the upper surface for exposing the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain, then by depositing technics to
Etch injection metal to through hole in the through hole formed to be completely filled, finally surface planarisation is handled, it is interchangeable to form source and drain
The electrode a and interchangeable electrode b of source and drain.
Advantage and effect
The invention has the advantages that and beneficial effect：
1. the symmetrical interchangeable two-way switch characteristic of source and drain：
Device of the present invention is a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, at the interchangeable electrode a 9 of source and drain
At the interchangeable electrode b 10 of source and drain, i.e., have respectively each other close to the part of grid electrode insulating layer 7 in the both sides of monocrystalline silicon thin film 1
Independent Schottky barrier is formed, because device has bilateral symmetry, under the control action of H-shaped gate electrode 8, and monocrystalline silicon
The both sides of film 1 top is in the near surface contacted with grid electrode insulating layer 7 while Schottky barrier tunneling effect occurs, and passes through tune
Save the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of the source and drain interchangeable area a 5 of voltage control metal source and drain and source metal
Leak interchangeable area b 6 and be used as source region or drain region, therefore Schottky barrier tunnelling current direction can be changed, realize the source and drain of the present invention
Symmetrical interchangeable two-way switch characteristic.
2. low subthreshold swing and high conducting electric current characteristic：
Due to the present invention be by the change of the voltage of H-shaped gate electrode 8, to control the power of Schottky barrier tunnel-effect, and then
Realize that the resistance in transistor source region and drain region changes, source region and drain region current-carrying caused by Schottky barrier tunnel-effect
Sub- change in concentration the sensitiveness of gate electrode voltage will be significantly larger than common MOSFETs devices in accumulation horizon caused by raceway groove or
Inversion-layer electrons change in concentration can be realized lower than common MOSFETs types device to the sensitiveness of gate electrode voltage
Subthreshold swing.And because the height of Schottky barrier is less than the energy gap of semiconductor, and the incoming particle concentration of metal is high
In the incoming particle concentration of semiconductor energy gap, contrast tunneling field-effect transistor can realize higher forward conduction electric current.
3. low speed paper tape reader static power disspation, high forward and reverse electric current ratio and low reverse leakage current characteristic：
On the one hand, when the voltage that H-shaped gate electrode 8 is applied in is gradually risen up near flat-band voltage from negative voltage, metal source and drain can
Exchange between the area a 5 and interchangeable intrinsic region a 3 of source and drain, the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain it
Between the Schottky barrier that is formed respectively obvious tunnel-effect will not occur, therefore in the interchangeable Hes of intrinsic region a 3 of source and drain
The interchangeable intrinsic region b 4 of source and drain both can not form a large amount of hole accumulations, also can not form a large amount of electronics accumulations, the source and drain of transistor can be mutual
Change the intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain and be in high-impedance state, therefore whole transistor does not have obvious electric current stream
Cross, also will not due to short-channel effect, caused potential barrier reduces, gate electrode control ability weakens etc. as common MOSFETs devices
Quiescent dissipation increase problem caused by factor, on the other hand, when H-shaped gate electrode 8 is in reverse-biased, metal source and drain is interchangeable
Between area a 5 and the interchangeable intrinsic region a 3 of source and drain, institute between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Obvious tunnel-effect occurs for the Schottky barrier formed respectively, therefore can be mutual in the interchangeable intrinsic region a 3 of source and drain and source and drain
Change intrinsic region b 4 and produce hole accumulation so that the interchangeable intrinsic region a 3 of source and drain now shows p-type feature, although now tunnel
Effect causes the interchangeable intrinsic region a 3 of source and drain resistance decreases in the presence of H-shaped gate electrode 8, but because source and drain is interchangeable intrinsic
Area a 3 shows p-type feature, and reverse-biased PN junction structure is formed under drain-source voltage with the heavily doped region 2 of N-type, and due to the weight of N-type
Doped region 2 is not controlled by H-shaped gate electrode 8, will not change its conductivity type because of the change of the voltage of H-shaped gate electrode 8, because
High resistant blocking state is integrally presented in this transistor under reverse-biased, therefore it is brilliant to contrast common MOSFETs devices, tunneling field-effect
Lower reverse leakage current characteristic can be achieved in body pipe and Schotthy barrier transistor technology, the present invention；Therefore device has simultaneously
There is the advantages of low speed paper tape reader static power disspation, forward and reverse electric current are than high and low reverse leakage current.
Brief description of the drawings
Fig. 1 is a kind of top view of source and drain resistive formula H-shaped grid-control two-way switch transistor of the present invention；
Fig. 2 is a kind of profile along dotted line A of source and drain resistive formula H-shaped grid-control two-way switch transistor of the present invention；
Fig. 3 is a kind of profile along dotted line B of source and drain resistive formula H-shaped grid-control two-way switch transistor of the present invention；
Fig. 4 is the top view of step 1；
Fig. 5 is the profile along dotted line A of step 1；
Fig. 6 is the profile along dotted line B of step 1；
Fig. 7 is the top view of step 2；
Fig. 8 is the profile along dotted line A of step 2；
Fig. 9 is the profile along dotted line B of step 2；
Figure 10 is the profile along dotted line C of step 2；
Figure 11 is the profile along dotted line D of step 2；
Figure 12 is the profile along dotted line E of step 2；
Figure 13 is the top view of step 3；
Figure 14 is the profile along dotted line A of step 3；
Figure 15 is the profile along dotted line B of step 3；
Figure 16 is the profile along dotted line C of step 3；
Figure 17 is the profile along dotted line D of step 3；
Figure 18 is the profile along dotted line E of step 3；
Figure 19 is the top view of step 4；
Figure 20 is the profile along dotted line A of step 4；
Figure 21 is the profile along dotted line B of step 4；
Figure 22 is the profile along dotted line C of step 4；
Figure 23 is the profile along dotted line D of step 4；
Figure 24 is the profile along dotted line E of step 4；
Figure 25 is the top view of step 5；
Figure 26 is the profile along dotted line A of step 5；
Figure 27 is the profile along dotted line B of step 5；
Figure 28 is the profile along dotted line C of step 5；
Figure 29 is the profile along dotted line D of step 5；
Figure 30 is the profile along dotted line E of step 5；
Figure 31 is the top view of step 6；
Figure 32 is the profile along dotted line A of step 6；
Figure 33 is the profile along dotted line B of step 6；
Figure 34 is the profile along dotted line C of step 6；
Figure 35 is the profile along dotted line D of step 6；
Figure 36 is the profile along dotted line E of step 6；
Figure 37 is the top view of step 7；
Figure 38 is the profile along dotted line A of step 7；
Figure 39 is the profile along dotted line B of step 7；
Figure 40 is the top view of step 8；
Figure 41 is the profile along dotted line A of step 8；
Figure 42 is the profile along dotted line B of step 8.
Description of reference numerals：
1st, monocrystalline silicon thin film；2nd, heavily doped region；3rd, the interchangeable intrinsic region a of source and drain；4th, the interchangeable intrinsic region b of source and drain；5th, source metal
Leak interchangeable area a；6th, the interchangeable area b of metal source and drain；7th, grid electrode insulating layer；8th, H-shaped gate electrode；9th, the interchangeable electrode a of source and drain；
10th, the interchangeable electrode b of source and drain；11st, insulated substrate layer；12nd, silicon substrate；13rd, insulating medium barrier layer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
As shown in Figure 1, Figure 2 and Figure 3, a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, the silicon lining comprising SOI wafer
Bottom 12, the top of silicon substrate 12 of SOI wafer are the insulated substrate layer 11 of SOI wafer, the insulated substrate layer 11 of SOI wafer it is upper
Side is monocrystalline silicon thin film 1, heavily doped region 2；Monocrystalline silicon thin film 1 has U-shaped structure feature, is less than 10 for impurity concentration16cm-3's
Single-crystal semiconductor material；Heavily doped region 2 is located at the intermediate region of the bottom horizontal portion of monocrystalline silicon thin film 1U shape structures, and it is mixed
The conduction type of impurity determines the conductivity type of device, is not influenceed to control by the field-effect of H-shaped gate electrode 8 inside it, is impurity
Concentration is not less than 1017cm-3Semi-conducting material；The interchangeable area a 5 of metal source and drain and the interchangeable area b 6 of metal source and drain are by metal
Material is formed, the upper middle portion of the both sides vertical component of the U-shaped structure formed respectively positioned at monocrystalline silicon thin film 1；Metal
The interchangeable area a 5 of source and drain front and rear surfaces and inner surface contact with each other with the interchangeable intrinsic region a 3 of source and drain, and by thirdly face is enclosed
Around contact surface forms Schottky barrier；The interchangeable area a 5 of metal source and drain bottom contacts with each other with monocrystalline silicon thin film 1, contact surface
Form Schottky barrier；The interchangeable area b 6 of metal source and drain front and rear surfaces and inner surface and the interchangeable phases of intrinsic region b 4 of source and drain
Mutually contact, and by thirdly face surrounds, contact surface forms Schottky barrier；The interchangeable area b 6 of metal source and drain bottom and monocrystalline silicon
Film 1 contacts with each other, and contact surface forms Schottky barrier；The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain divide
Not Wei Yu monocrystalline silicon thin film 1U shape structures both sides vertical component upper area front and rear surfaces and inner surface, be impurity concentration
Less than 1016cm-3Single-crystal semiconductor material；The interchangeable intrinsic region a 3 of monocrystalline silicon thin film 1, heavily doped region 2, source and drain, source and drain
The interchangeable area a 5 of interchangeable intrinsic region b 4, metal source and drain and the interchangeable area b 6 of metal source and drain have collectively constituted a U-shaped knot
Structure；Grid electrode insulating layer 7 is located at upper surface and front and rear surfaces and the monocrystalline of monocrystalline silicon thin film 1U shape structural base horizontal components
The inner surface and front and rear surfaces of silicon thin film 1U shape structures both sides vertical component；H-shaped gate electrode 8 is by metal material or polysilicon material
Material is formed, and the inner surface and front and rear surfaces to the both sides vertical component of monocrystalline silicon thin film 1U shape structures form three bread and wrapped up in, and bow
Depending on SOI wafer, H-shaped gate electrode 8 is in English capitalization H shape, H-shaped gate electrode 8 and monocrystalline silicon thin film 1U shapes along source and drain direction
Insulated from each other by grid electrode insulating layer 7 between structure, H-shaped gate electrode 8 is located on the inside of monocrystalline silicon thin film 1U shapes texture grooves
There is the subregion of insulating medium barrier layer 13, H-shaped gate electrode 8 is only to list between portion lower surface and grid electrode insulating layer 7
The front and rear surfaces and inner surface of the upper area of the both sides vertical component of polycrystal silicon film 1U shape structures, i.e., it is interchangeable to source and drain intrinsic
Area a 3 and the interchangeable intrinsic region b 4 of source and drain are hung down by obvious field-effect control action to the both sides of monocrystalline silicon thin film 1U shape structures
The straight lower zone of part and the bottom horizontal portion region of monocrystalline silicon thin film 1U shape structures do not have obvious field-effect control to make
With；The interchangeable electrode a 9 of source and drain is made up of metal material, positioned at the interchangeable area a 5 of metal source and drain top；The interchangeable electricity of source and drain
Pole b 10 is also made up of metal material, and positioned at the interchangeable area b 6 of metal source and drain top, the interchangeable electrode a 9 of source and drain, source and drain can
It is insulated from each other by insulating medium barrier layer 13 between staggered poles b 10 and H-shaped gate electrode 8 these three electrodes；Heavily doped region 2
The left and right sides be in symmetrical structure, the feelings that can be symmetrically exchanged in the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain
Same output characteristics is realized under condition
The present invention provides a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, because device has a left side on source and drain direction
Right symmetrical structure feature, therefore can only pass through regulation as the tunneling field-effect transistor of single-way switch different from common
The interchangeable area a 5 of the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain voltage control metal source and drain and metal source and drain
Interchangeable area b 6 is used as source region or drain region, changes the sense of current, device is realized two-way switch characteristic, i.e. its source region and drain region
Can realize can exchange the function of exchange.
By heavily doped region 2 be N-type impurity exemplified by, when the interchangeable area a 5 of metal source and drain, the interchangeable area b 6 of metal source and drain it
Between when electrical potential difference be present, and when H-shaped gate electrode 8 is in reverse-biased, the interchangeable area a 5 of metal source and drain and source and drain are interchangeable intrinsic
The Schottky barrier formed respectively between area a 3, between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Obvious tunnel-effect occurs, therefore can produce hole in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain
Accumulation so that the interchangeable intrinsic region a 3 of source and drain now shows p-type feature, although now tunnel-effect causes interchangeable of source and drain
The resistance decreases in the presence of H-shaped gate electrode 8 of area a 3 are levied, but because the interchangeable intrinsic region a 3 of source and drain shows p-type feature, with N
The heavily doped region 2 of type forms reverse-biased PN junction structure under drain-source voltage, and because the heavily doped region 2 of N-type is not by H-shaped grid electricity
What pole 8 controlled, its conductivity type will not be changed because of the change of the voltage of H-shaped gate electrode 8, therefore transistor is under reverse-biased
It is overall that high resistant blocking state is presented；With the voltage that H-shaped gate electrode 8 is applied in, from negative voltage to gradually rise up to flat-band voltage attached
Closely, between the interchangeable area a 5 of metal source and drain and the interchangeable intrinsic region a 3 of source and drain, the interchangeable area b 6 of metal source and drain and source and drain can be mutual
Obvious tunnel-effect will not be occurred by changing between intrinsic region b 4 Schottky barrier formed respectively, therefore can be mutual in source and drain
Change the intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain and both can not form a large amount of hole accumulations, also can not form a large amount of electronics accumulations, it is brilliant
The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain of body pipe are in high-impedance state, therefore whole transistor is not
Have obvious electric current to flow through, device now has outstanding turn-off characteristic and Sub-Threshold Characteristic；As H-shaped gate electrode 8 is applied in
Voltage forward bias condition is further risen to by flat-band voltage, the interchangeable area a 5 of metal source and drain and source and drain are interchangeable intrinsic
The Schottky barrier formed respectively between area a 3, between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Obvious tunnel-effect can occur again so that the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain are formed greatly
Electronics accumulation is measured, and the voltage that the electron concentration accumulated is applied in H-shaped gate electrode 8 rises and gradually risen, therefore meeting
Good electronic conduction raceway groove is upwardly formed in source and drain side, when electron concentration increase to a certain extent when, transistor is by subthreshold value
Status transition is to forward conduction state.
To reach device function of the present invention, the present invention proposes a kind of source and drain resistive formula H-shaped grid-control two-way opened
Transistor is closed, its core texture is characterized as：
Device of the present invention is a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, has the structure of H-shaped grid, with
The outer surface of grid electrode insulating layer 7 contacts with each other, and forms three faces to grid electrode insulating layer 7 and surround, and overlooks viewing and English is presented
Literary capital H shape architectural feature, the upper section of the both sides vertical component of the U-shaped structure formed to monocrystalline silicon thin film 1, i.e.,
Intrinsic region a 3 interchangeable to the source and drain and interchangeable intrinsic region b 4 of source and drain has obvious field-effect control action, when H-shaped grid electricity
When pole 8 is in positively biased state, in contrast to planar structure, the electric-field intensity near the corner region of H-shaped gate electrode 8 can be added
By force, the probability for causing to produce carrier in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain is in equal grid electricity
Pressure increase so that subthreshold swing has declined, forward conduction electric current has increased；
The both sides of heavily doped region 2 and its part of the insulating medium barrier layer of top 13 are in symmetrical structure.When to the gate electrode of both sides
When applying backward voltage simultaneously, in the near surface that the top both sides of monocrystalline silicon thin film 1 contact with grid electrode insulating layer 7, i.e. source
Leak the interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain have accumulated it is largely opposite with the majority carrier type of heavily doped region 2
Carrier, these carriers understand some under the comprehensive function of Driftdiffusion and flow to heavily doped region 2, and in heavily doped region
2 with the majority carrier of heavily doped region therewith the opposite carrier of conduction type occur it is compound, because heavily doped region 2 is highly doped
Concentration range, it is sufficient to which the carrier from the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain is almost completely multiple
Conjunction is fallen, and due to being in reverse-biased high-impedance state between the interchangeable intrinsic region of source and drain as source region side and heavily doped region 2, therefore
Obvious electric current will not now be produced on source and drain direction to produce, this structure significantly reduces the reverse leakage electricity of transistor
Stream, and allow device to obtain higher forward and reverse electric current ratio.Due to symmetrical structure possessed by device of the present invention, lead to
Cross and control the interchangeable area a 5 of interchangeable source-drain electrode 19 and interchangeable source-drain electrode 210 switching metal source and drain and metal source and drain can
Exchange area b 6 and be used as source region or drain region, the output characteristics of device can't be influenceed, therefore can realize such as MOSFETs devices
The interchangeable two-way switch characteristic of source and drain.Grid electrode insulating layer 7 is the insulation material layer for producing tunnelling current.
The present invention is described further below in conjunction with the accompanying drawings：
A kind of unit of source and drain resistive formula H-shaped grid-control two-way switch transistor proposed by the invention is specific in SOI wafer
Manufacturing technology steps are as follows：
Step 1：As shown in Figure 4, Figure 5 and Figure 6, there is provided a SOI wafer, bottom are the silicon substrate 12 of SOI wafer, and silicon serves as a contrast
It is insulated substrate layer 11 above bottom, the upper surface of insulated substrate layer 11 is monocrystalline silicon thin film 1, passes through ion implanting or diffusion work
Skill, the intermediate region doping of the monocrystalline silicon thin film 1 above SOI wafer, preliminarily forms heavily doped region 2；
Step 2：As shown in Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 and Figure 12, part monocrystalline silicon is removed by photoetching, etching technics
Film 1 and heavily doped region 2, monocrystalline silicon thin film 1 and heavily doped region 2 are formed in SOI wafer；
Step 3：As shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18, monocrystalline silicon thin film 1 and heavily doped region in bottom
2 upper surface and the outer surface of the left and right sides intermediate raised portion of monocrystalline silicon thin film 1, by aoxidizing or depositing, etch work
Skill, form grid electrode insulating layer 7；
Step 4：As shown in Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24, by depositing technics, formed sediment above SOI wafer
Product dielectric, planarizes surface to the upper surface for exposing monocrystalline silicon thin film 1, preliminarily forms SI semi-insulation dielectric barrier 13；
Step 5：As shown in Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 and Figure 30, by etching technics, to being deposited in step 4
Insulating medium barrier layer 13 carry out partial etching, further formed insulating medium barrier layer 13；
Step 6：Such as Figure 31, Figure 32.Shown in Figure 33, Figure 34, Figure 35 and Figure 36, metal or polycrystalline are deposited above SOI wafer
Silicon, surface to the upper surface for exposing monocrystalline silicon thin film 1 is planarized, form H-shaped gate electrode 8；
Step 7：As shown in Figure 37, Figure 38 and Figure 39, by etching technics, to the left and right sides vertical component of monocrystalline silicon thin film 1
Upper surface intermediate region perform etching, then by depositing technics, deposit metal in SOI wafer upper surface, make metal and monocrystalline
Silicon thin film contact portion forms Schottky barrier, planarizes surface to the upper surface for exposing monocrystalline silicon thin film 1, forms metal source and drain
The interchangeable area a 5 and interchangeable area b 6 of metal source and drain；
Step 8：As shown in Figure 40, Figure 41 and Figure 42, by oxidation or depositing technics, deposit insulation Jie above SOI wafer
Matter, form the insulating medium barrier layer 13 of remainder；It is interchangeable by etching technics removal metal source and drain behind planarization surface
Area a 5 and the insulating medium barrier layer 13 of the tops of the interchangeable area b of metal source and drain 6 are to exposing the interchangeable area a 5 of metal source and drain and gold
Belong in the interchangeable area b 6 of source and drain upper surface, then the through hole formed by depositing technics to etching and inject metal or polysilicon extremely
Through hole is completely filled, and finally handles surface planarisation, forms the interchangeable electrode a 9 and interchangeable electrode b of source and drain of source and drain
10。
Claims (2)
1. a kind of source and drain resistive formula H-shaped grid-control two-way switch transistor, the silicon substrate comprising SOI wafer（12）, it is characterised in that：
The silicon substrate of SOI wafer（12）Top is the insulated substrate layer of SOI wafer（11）, the insulated substrate layer of SOI wafer（11）It is upper
Side is monocrystalline silicon thin film（1）, heavily doped region（2）；Monocrystalline silicon thin film（1）With U-shaped structure feature, it is less than for impurity concentration
1016cm-3Single-crystal semiconductor material；Heavily doped region（2）Positioned at monocrystalline silicon thin film（1）The bottom horizontal portion of U-shaped structure
Intermediate region, the conduction type of its impurity determine the conductivity type of device, inside it not H-shaped by gate electrode（8）Field-effect
Control is influenceed, is not less than 10 for impurity concentration17cm-3Semi-conducting material；The interchangeable area a of metal source and drain（5）Can with metal source and drain
Exchange area b（6）It is made up of metal material, respectively positioned at monocrystalline silicon thin film（1）The both sides vertical component of the U-shaped structure formed
Upper middle portion；The interchangeable area a of metal source and drain（5）Front and rear surfaces and inner surface and the interchangeable intrinsic region a of source and drain（3）Phase
Mutually contact, and by thirdly face surrounds, contact surface forms Schottky barrier；The interchangeable area a of metal source and drain（5）Bottom and monocrystalline silicon
Film（1）Contact with each other, contact surface forms Schottky barrier；The interchangeable area b of metal source and drain（6）Front and rear surfaces and inner surface
With the interchangeable intrinsic region b of source and drain（4）Contact with each other, and by thirdly face surrounds, contact surface forms Schottky barrier；Metal source and drain can
Exchange area b（6）Bottom and monocrystalline silicon thin film（1）Contact with each other, contact surface forms Schottky barrier；The interchangeable intrinsic region of source and drain
a（3）With the interchangeable intrinsic region b of source and drain（4）It is located at monocrystalline silicon thin film respectively（1）The upper zone of the both sides vertical component of U-shaped structure
The front and rear surfaces and inner surface in domain, it is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film（1）, again
Doped region（2）, the interchangeable intrinsic region a of source and drain（3）, the interchangeable intrinsic region b of source and drain（4）, the interchangeable area a of metal source and drain（5）And gold
Belong to the interchangeable area b of source and drain（6）A U-shaped structure is collectively constituted；Grid electrode insulating layer（7）Positioned at monocrystalline silicon thin film（1）U-shaped knot
The upper surface of structure bottom horizontal portion and front and rear surfaces and monocrystalline silicon thin film（1）The inner side table of U-shaped structure both sides vertical component
Face and front and rear surfaces；H-shaped gate electrode（8）It is made up of metal material or polycrystalline silicon material, to monocrystalline silicon thin film（1）U-shaped structure
The inner surface and front and rear surfaces of both sides vertical component form three bread and wrapped up in, and overlook SOI wafer, H-shaped gate electrode（8）Along source and drain side
To in English capitalization H shape, H-shaped gate electrode（8）With monocrystalline silicon thin film（1）Pass through grid electrode insulating layer between U-shaped structure
（7）It is insulated from each other, H-shaped gate electrode（8）Be located at monocrystalline silicon thin film（1）U-shaped structure groove inboard portion lower surface and gate electrode
Insulating barrier（7）Between there is insulating medium barrier layer（13）Subregion, H-shaped gate electrode（8）Only to monocrystalline silicon thin film（1）U
The front and rear surfaces and inner surface of the surface area upper area of the both sides vertical component of shape structure, i.e., it is interchangeable to source and drain intrinsic
Area a（3）With the interchangeable intrinsic region b of source and drain（4）By obvious field-effect control action, and to monocrystalline silicon thin film（1）The two of U-shaped structure
The lower zone and monocrystalline silicon thin film of side vertical component（1）The bottom horizontal portion region of U-shaped structure does not have obvious field-effect
Control action；The interchangeable electrode a of source and drain（9）It is made up of metal material, positioned at the interchangeable area a of metal source and drain（5）Top；Source and drain
Interchangeable electrode b（10）Also it is made up of metal material, positioned at the interchangeable area b of metal source and drain（6）Top, the interchangeable electrode of source and drain
a（9）, the interchangeable electrode b of source and drain（10）With H-shaped gate electrode（8）Pass through insulating medium barrier layer between these three electrodes（13）That
This insulation；Heavily doped region（2）The left and right sides be in symmetrical structure, can be in the interchangeable electrode a of source and drain（9）With the interchangeable electricity of source and drain
Pole b（10）Same output characteristics is realized in the case of symmetrical exchange.
2. a kind of manufacture method of source and drain resistive formula H-shaped grid-control two-way switch transistor as claimed in claim 1, its feature exist
In：
Its manufacturing step is as follows：
Step 1：A SOI wafer is provided, bottom is the silicon substrate of SOI wafer（12）, it is insulated substrate above silicon substrate
Layer（11）, insulated substrate layer（11）Upper surface be monocrystalline silicon thin film（1）, by ion implanting or diffusion technique, to SOI wafer
The monocrystalline silicon thin film of top（1）Intermediate region doping, preliminarily form heavily doped region（2）；
Step 2：Part monocrystalline silicon thin film is removed by photoetching, etching technics（1）And heavily doped region（2）, the shape in SOI wafer
Into monocrystalline silicon thin film（1）And heavily doped region（2）；
Step 3：Monocrystalline silicon thin film in bottom（1）And heavily doped region（2）Upper surface and monocrystalline silicon thin film（1）Left and right two
The outer surface of side intermediate raised portion, by aoxidizing or depositing, etching technics, form grid electrode insulating layer（7）；
Step 4：By depositing technics, dielectric is deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film
（1）Upper surface, preliminarily form SI semi-insulation dielectric barrier（13）；
Step 5：By etching technics, to the insulating medium barrier layer deposited in step 4（13）Partial etching is carried out, enters one
Step forms insulating medium barrier layer（13）；
Step 6：Deposit metal or polysilicon above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film（1）Upper table
Face, form H-shaped gate electrode（8）；
Step 7：By etching technics, to monocrystalline silicon thin film（1）Left and right sides vertical component upper surface intermediate region carry out
Etching, then by depositing technics, deposit metal in SOI wafer upper surface, metal is formed Xiao with monocrystalline silicon thin film contact portion
Special base potential barrier, planarization surface is to exposing monocrystalline silicon thin film（1）Upper surface, form metal source and drain interchangeable area a（5）And metal
The interchangeable area b of source and drain（6）；
Step 8：By depositing technics, dielectric is deposited above SOI wafer, the dielectric for forming remainder stops
Layer（13）；The interchangeable area a of metal source and drain is removed by etching technics behind planarization surface（5）With the interchangeable area b of metal source and drain（6）
The insulating medium barrier layer of top（13）To exposing the interchangeable area a of metal source and drain（5）With the interchangeable area b of metal source and drain（6）It is upper
Injection metal to through hole is completely filled in surface, then the through hole formed by depositing technics to etching, finally that surface is flat
Change is handled, and forms the interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）.
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| CN113611751A (en) * | 2021-07-15 | 2021-11-05 | 沈阳工业大学 | High-low Schottky barrier undoped XNOR logic digital chip and manufacturing method thereof |
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| CN113471205B (en) * | 2021-06-30 | 2023-11-03 | 沈阳工业大学 | Nonvolatile resettable bi-directional switching device and method of manufacturing the same |
| CN113611751A (en) * | 2021-07-15 | 2021-11-05 | 沈阳工业大学 | High-low Schottky barrier undoped XNOR logic digital chip and manufacturing method thereof |
| CN113611751B (en) * | 2021-07-15 | 2023-11-10 | 沈阳工业大学 | High-low Schottky barrier undoped XNOR logic digital chip and manufacturing method thereof |
| CN113764531A (en) * | 2021-08-31 | 2021-12-07 | 沈阳工业大学 | Source-drain auxiliary programmable single-gate Schottky barrier transistor and manufacturing method thereof |
| CN113764531B (en) * | 2021-08-31 | 2023-10-20 | 沈阳工业大学 | Source-drain auxiliary programmable single-gate Schottky barrier transistor and manufacturing method thereof |
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| CN113948576B (en) * | 2021-09-27 | 2023-09-08 | 沈阳工业大学 | Deep and shallow combined Schottky barrier tunnel transistor and manufacturing method thereof |
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