CN107799589B - H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and its manufacturing method - Google Patents
H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and its manufacturing method Download PDFInfo
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- CN107799589B CN107799589B CN201711048116.2A CN201711048116A CN107799589B CN 107799589 B CN107799589 B CN 107799589B CN 201711048116 A CN201711048116 A CN 201711048116A CN 107799589 B CN107799589 B CN 107799589B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The present invention relates to a kind of H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and its manufacturing methods, device of the present invention has rectangular gate and symmetrical structure feature, with stronger grid control ability and the second class interchangeable area of impurity heavy doping source and drain can be controlled as source region or drain region by adjusting the interchangeable electrode voltage of source and drain, change tunnelling current direction.The advantages of present invention has the function of low speed paper tape reader static power disspation reverse leakage current, low subthreshold swing and can realize two-way switch.In contrast to common MOSFETs type device, more excellent switching characteristic is realized using tunneling effect；In contrast to common tunneling field-effect transistor, the present invention has the interchangeable bi-directional symmetrical switching characteristic of source and drain not available for common tunneling field-effect transistor, therefore is suitble to promote and apply.
Description
Technical field
The present invention relates to super large-scale integration manufacturing fields, and in particular to one kind is suitable for low power consumption integrated circuit system
The H-shaped grid-control source and drain with low current leakage made symmetrically interchangeable type tunneling transistor and its manufacturing method.
Background technique
The basic unit MOSFETs of integrated circuit can become smaller and smaller according to the requirement of Moore's Law, size, therewith
What is come is not only that difficulty in manufacturing process is deepened, various ill effects also highlighting more.Nowadays IC design
The limitation of the physical mechanism of electric current itself is generated when used MOSFETs type device is due to its work, subthreshold swing begins
It cannot be below 60mV/dec eventually.And commonly tunneling field-effect transistor is as switching-type device in use, using carrier half
Conduction mechanism of the tunneling effect as electric current occurs between conductor energy band, subthreshold swing will be substantially better than MOSFETs type device
The 60mv/dec limit of part.However, the source region of common tunneling field-effect transistor and drain region use the impurity of different conduction-types,
This unsymmetric structure feature causes it that can not functionally replace the MOSFETs type device with symmetrical structure feature completely.
By taking N-type tunneling field-effect transistor as an example, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential,
Then tunneling field-effect transistor will be in the conductive state always, and the size of conducting electric current is no longer able to obtain good by gate electrode
Good control and adjusting, this makes the switching characteristic of entire tunneling field-effect transistor fail.
Summary of the invention
Goal of the invention
In order to effectively combine and utilize MOSFETs type device source electrode, the interchangeable and common tunneling field-effect transistor of drain electrode
The advantages of low subthreshold swing amplitude of oscillation, solving MOSFETs type device subthreshold swing can not reduce and common tunneling field-effect crystalline substance
Body pipe can only be proposed as the deficiency of single-way switch, the present invention a kind of H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and
Its manufacturing method.The transistor has logic function and is currently based on the completely compatible advantageous feature of MOSFETs integrated circuit, source
The symmetry of leakage two-end structure allows to exchange the function for realizing source and drain bi-directional symmetrical switch by the voltage to source electrode and drain electrode
Can, i.e., with the interchangeable two-way switch characteristic of source-drain electrode, additionally with forward and reverse electric current than high and low subthreshold swing,
The working characteristics such as high forward conduction electric current.
Technical solution
The present invention is achieved through the following technical solutions:
A kind of symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain, the silicon substrate comprising SOI wafer, it is characterised in that:
It is the substrate insulating layer of SOI wafer above the silicon substrate of SOI wafer, the top of the substrate insulating layer of SOI wafer is that monocrystalline silicon is thin
Film, first kind impurity heavily doped region；Monocrystalline silicon thin film has U-shaped structure feature, is lower than 10 for impurity concentration16cm-3Monocrystalline silicon
Semiconductor material；First kind impurity heavily doped region is located at the intermediate region of the bottom horizontal portion of monocrystalline silicon thin film U-shaped structure,
The conduction type of impurity determines the conductivity type of device, inside do not influenced to control by H-shaped gate electrode field-effect, be impurity
Concentration is not less than 1017cm-3Semiconductor material；The interchangeable area a of second class impurity heavy doping source and drain and the second class impurity heavy doping
The interchangeable area b of source and drain is adulterated by being formed by the upper section of the two sides vertical component of U-shaped structure to monocrystalline silicon thin film respectively
It is formed, impurity peak concentration is not less than 1018cm-3, wherein the front and rear surfaces of the second interchangeable area a of class impurity heavy doping source and drain and
Inner surface contacts with each other with the interchangeable intrinsic region a of source and drain, and by thirdly face surrounds；Second class impurity heavy doping source and drain is interchangeable
The front and rear surfaces and inner surface of area b contact with each other with the interchangeable intrinsic region b of source and drain, and by thirdly face surrounds；Source and drain is interchangeable
The intrinsic region a and interchangeable intrinsic region b of source and drain is located at the upper area of the two sides vertical component of monocrystalline silicon thin film U-shaped structure
Front and rear surfaces and inner surface are lower than 10 for impurity concentration16cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film, the first kind are miscellaneous
The interchangeable intrinsic region a of matter heavily doped region, source and drain, the interchangeable intrinsic region b of source and drain, the second interchangeable area a of class impurity heavy doping source and drain
A U-shaped structure has been collectively constituted with the second interchangeable area b of class impurity heavy doping source and drain；It is thin that grid electrode insulating layer is located at monocrystalline silicon
The upper surface of film U-shaped structure bottom horizontal portion and front and rear surfaces and monocrystalline silicon thin film U-shaped structure two sides vertical component it is interior
Side surface and front and rear surfaces；H-shaped gate electrode is made of metal material or polycrystalline silicon material, to the two of monocrystalline silicon thin film U-shaped structure
The inner surface and front and rear surfaces of the upper section of lateral vertical section point form three bread and wrap up in, and overlook SOI wafer, H-shaped gate electrode edge
Source and drain direction is in English capitalization H shape, passes through grid electrode insulating layer between H-shaped gate electrode and monocrystalline silicon thin film U-shaped structure
It is insulated from each other, H-shaped gate electrode between monocrystalline silicon thin film U-shaped structure groove inboard portion lower surface and grid electrode insulating layer
Partial region with insulating medium barrier layer, H-shaped gate electrode is only to the upper of the two sides vertical component of monocrystalline silicon thin film U-shaped structure
The front and rear surfaces and inner surface in portion region, i.e., intrinsic region a interchangeable to source and drain and the interchangeable intrinsic region b of source and drain have obvious field-effect
Control action, and the lower zone and monocrystalline silicon thin film U-shaped structure to the two sides vertical component of monocrystalline silicon thin film U-shaped structure
Bottom horizontal portion region does not have obvious field-effect control action；The interchangeable electrode a of source and drain is made of metal material, is located at second
The top of the interchangeable area a of class impurity heavy doping source and drain；The interchangeable electrode b of source and drain is also made of metal material, and it is miscellaneous to be located at the second class
The top of the interchangeable area b of matter heavy doping source and drain, the interchangeable electrode a of source and drain, the interchangeable electrode b of source and drain and H-shaped gate electrode these three
It is insulated from each other by insulating medium barrier layer between electrode；The left and right sides of first kind impurity heavily doped region is in symmetrical structure, energy
It is enough to realize same output characteristics in the case where the interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain are symmetrically exchanged.
A kind of manufacturing method of the symmetrical interchangeable type tunneling transistor of the H-shaped grid-control source and drain, it is characterised in that:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate of SOI wafer, and the upper surface of silicon substrate is substrate insulation
The upper surface of layer, substrate insulating layer is monocrystalline silicon thin film, by ion implanting or diffusion technique, to the monocrystalline above SOI wafer
The intermediate region of silicon thin film is adulterated, and first kind impurity heavily doped region is preliminarily formed；
Step 2: part monocrystalline silicon thin film and first kind impurity heavily doped region are removed by photoetching, etching technics, in SOI
Monocrystalline silicon thin film and first kind impurity heavily doped region are formed on wafer；
Step 3: left in the monocrystalline silicon thin film of bottom and the upper surface of first kind impurity heavily doped region and monocrystalline silicon thin film
The outer surface of right two sides intermediate raised portion forms grid electrode insulating layer by aoxidizing or depositing, etching technics；
Step 4: by depositing technics, depositing dielectric above SOI wafer, and planarization surface is to exposing monocrystalline silicon
The upper surface of film preliminarily forms SI semi-insulation dielectric barrier；
Step 5: by etching technics, partial etching is carried out to the insulating medium barrier layer deposited in step 4, into one
Step forms insulating medium barrier layer；
Step 6: metal or polysilicon, planarization surface to the upper table for exposing monocrystalline silicon thin film are deposited above SOI wafer
Face forms H-shaped gate electrode；
Step 7: by ion implantation technology, to the upper surface middle area of the left and right sides vertical component of monocrystalline silicon thin film
Domain is doped, and forms the interchangeable area a and the second interchangeable area b of class impurity heavy doping source and drain of the second class impurity heavy doping source and drain；
Step 8: by depositing technics, depositing dielectric above SOI wafer, forms the dielectric of rest part
Barrier layer；The interchangeable area a of the second class impurity heavy doping source and drain and the second class impurity are removed by etching technics behind planarization surface
Insulating medium barrier layer above the interchangeable area b of heavy doping source and drain to expose the second interchangeable area a of class impurity heavy doping source and drain and
The upper surface of the second interchangeable area b of class impurity heavy doping source and drain, then gold is injected into the through-hole of etching formation by depositing technics
Category is completely filled to through-hole, finally handles surface planarisation, forms the interchangeable electrode a and interchangeable electrode b of source and drain of source and drain.
Advantage and effect
The invention has the following advantages and beneficial effects:
1. the symmetrical interchangeable two-way switch characteristic of source and drain:
Device of the present invention is a kind of H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor, is leaned in monocrystalline silicon thin film 1
The part of nearly 7 two sides of grid electrode insulating layer is respectively provided with tunneling structure independent of each other, since device has bilateral symmetry,
Under the control action of H-shaped gate electrode 8, monocrystalline silicon thin film 1 be formed by above U-shaped structure two sides vertical components with gate electrode
Nearby simultaneously tunnelling occurs for the surface that insulating layer 7 contacts, by adjusting the interchangeable electrode a 9 and interchangeable electrode b of source and drain of source and drain
10 voltage controls the interchangeable area a 5 and the second interchangeable area b 6 of class impurity heavy doping source and drain of the second class impurity heavy doping source and drain
As source region or drain region, therefore changeable tunnelling current direction, realizing source and drain of the invention, symmetrically interchangeable two-way switch is special
Property.
2. low subthreshold swing:
Since the present invention is the tunneling mechanism based on tunneling field-effect transistor, and symmetrical double-gate structure is used, had good
Good grid control ability, under the control action of H-shaped gate electrode 8, energy band bends, the left and right sides of monocrystalline silicon thin film 1
Tunnelling occurs simultaneously near the surface contacted with grid electrode insulating layer 7, so that carrier passes through potential barrier with greater probability,
Larger current is quickly formed within a short period of time, and there is low subthreshold swing compared to MOSFETs type device.
3. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio:
When between the interchangeable area a 5 of the second class impurity heavy doping source and drain, the second interchangeable area b 6 of class impurity heavy doping source and drain
There are when potential difference, and when H-shaped gate electrode 8 is in subthreshold value or reverse-biased, due to first kind impurity heavily doped region 2 respectively with
The interchangeable area a 5 of second class impurity heavy doping source and drain, the second interchangeable area b 6 of class impurity heavy doping source and drain have opposite impurity class
Type, therefore 2 certainty of first kind impurity heavily doped region and the interchangeable area a 5 of the second class impurity heavy doping source and drain or the second class impurity weight
One of interchangeable area b 6 of doped source and drain is in reverse-biased, and first kind impurity heavily doped region 2 is inevitable miscellaneous with the second class
There are portion of monocrystalline silicon is thin between the interchangeable area a 5 of matter heavy doping source and drain or the second interchangeable area b 6 of class impurity heavy doping source and drain
Film 1, thus device have it is preferable inhibit field strength it is too strong caused by the ability that significantly increases of tunnelling current.In other words
It says, first kind impurity heavily doped region 2 is not due to that by the control of H-shaped gate electrode 8, can block the second class impurity heavy-doped source effectively
Leak the conducting of the majority carrier between interchangeable area a 5 or the second interchangeable area b 6 of class impurity heavy doping source and drain.Therefore this hair
It is bright to have the advantages that low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio.
Detailed description of the invention
Fig. 1 is a kind of top view of the symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain of the present invention；
Fig. 2 is a kind of sectional view along dotted line A of the symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain of the present invention；
Fig. 3 is a kind of sectional view along dotted line B of the symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain of the present invention；
Fig. 4 is the top view of step 1；
Fig. 5 is the sectional view along dotted line A of step 1；
Fig. 6 is the sectional view along dotted line B of step 1；
Fig. 7 is the top view of step 2；
Fig. 8 is the sectional view along dotted line A of step 2；
Fig. 9 is the sectional view along dotted line B of step 2；
Figure 10 is the sectional view along dotted line C of step 2；
Figure 11 is the sectional view along dotted line D of step 2；
Figure 12 is the sectional view along dotted line E of step 2；
Figure 13 is the top view of step 3；
Figure 14 is the sectional view along dotted line A of step 3；
Figure 15 is the sectional view along dotted line B of step 3；
Figure 16 is the sectional view along dotted line C of step 3；
Figure 17 is the sectional view along dotted line D of step 3；
Figure 18 is the sectional view along dotted line E of step 3；
Figure 19 is the top view of step 4；
Figure 20 is the sectional view along dotted line A of step 4；
Figure 21 is the sectional view along dotted line B of step 4；
Figure 22 is the sectional view along dotted line C of step 4；
Figure 23 is the sectional view along dotted line D of step 4；
Figure 24 is the sectional view along dotted line E of step 4；
Figure 25 is the top view of step 5；
Figure 26 is the sectional view along dotted line A of step 5；
Figure 27 is the sectional view along dotted line B of step 5；
Figure 28 is the sectional view along dotted line C of step 5；
Figure 29 is the sectional view along dotted line D of step 5；
Figure 30 is the sectional view along dotted line E of step 5；
Figure 31 is the top view of step 6；
Figure 32 is the sectional view along dotted line A of step 6；
Figure 33 is the sectional view along dotted line B of step 6；
Figure 34 is the sectional view along dotted line C of step 6；
Figure 35 is the sectional view along dotted line D of step 6；
Figure 36 is the sectional view along dotted line E of step 6；
Figure 37 is the top view of step 7；
Figure 38 is the sectional view along dotted line A of step 7；
Figure 39 is the sectional view along dotted line B of step 7；
Figure 40 is the top view of step 8；
Figure 41 is the sectional view along dotted line A of step 8；
Figure 42 is the sectional view along dotted line B of step 8.
Description of symbols:
1, monocrystalline silicon thin film；2, first kind impurity heavily doped region；3, the interchangeable intrinsic region a of source and drain；4, interchangeable of source and drain
Levy area b；5, the second interchangeable area a of class impurity heavy doping source and drain；6, the second interchangeable area b of class impurity heavy doping source and drain；7, grid electricity
Pole insulating layer；8, H-shaped gate electrode；9, the interchangeable electrode a of source and drain；10, the interchangeable electrode b of source and drain；11, substrate insulating layer；12, silicon
Substrate；13, insulating medium barrier layer.
Specific embodiment
Following further describes the present invention with reference to the drawings:
As shown in Figure 1, Figure 2 and Figure 3, the symmetrical interchangeable type tunneling transistor of a kind of H-shaped grid-control source and drain includes SOI wafer
Silicon substrate 12, be the substrate insulating layer 11 of SOI wafer, the substrate insulating layer of SOI wafer above the silicon substrate 12 of SOI wafer
11 top is monocrystalline silicon thin film 1, first kind impurity heavily doped region 2；Monocrystalline silicon thin film 1 has U-shaped structure feature, is that impurity is dense
Degree is lower than 1016cm-3Single-crystal semiconductor material；First kind impurity heavily doped region 2 is located at the bottom of monocrystalline silicon thin film 1U shape structure
The intermediate region of portion's horizontal component, the conduction type of impurity determine the conductivity type of device, inside not by H-shaped grid electricity
8 field-effect of pole influences control, is not less than 10 for impurity concentration17cm-3Semiconductor material；Second class impurity heavy doping source and drain can
Area a 5 and the second interchangeable area b 6 of class impurity heavy doping source and drain is exchanged respectively by being formed by U-shaped knot to monocrystalline silicon thin film 1
The upper section of the two sides vertical component of structure adulterates to be formed, and impurity peak concentration is not less than 1018cm-3, wherein the second class impurity weight
The front and rear surfaces and inner surface of the interchangeable area a 5 of doped source and drain contact with each other with the interchangeable intrinsic region a 3 of source and drain, and by thirdly
Face surrounds；The front and rear surfaces and inner surface and the interchangeable intrinsic region b of source and drain of the second interchangeable area b 6 of class impurity heavy doping source and drain
4 contact with each other, and by thirdly face surrounds；The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain are located at monocrystalline
The front and rear surfaces and inner surface of the upper area of the two sides vertical component of silicon thin film 1U shape structure are lower than 10 for impurity concentration16cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film 1, first kind impurity heavily doped region 2, the interchangeable intrinsic region a 3 of source and drain, source and drain
Interchangeable intrinsic region b 4, the interchangeable area a 5 of the second class impurity heavy doping source and drain and the second interchangeable area of class impurity heavy doping source and drain
B 6 has collectively constituted a U-shaped structure；Grid electrode insulating layer 7 is located at the upper of 1 U-shaped structure bottom horizontal portion of monocrystalline silicon thin film
The inner surface and front and rear surfaces of surface and front and rear surfaces and 1 U-shaped structure two sides vertical component of monocrystalline silicon thin film；H-shaped grid electricity
Pole 8 is made of metal material or polycrystalline silicon material, to the upper section of the two sides vertical component of 1 U-shaped structure of monocrystalline silicon thin film
Inner surface and front and rear surfaces form three bread and wrap up in, and overlook SOI wafer, and H-shaped gate electrode 8 is in English capitalization along source and drain direction
H shape, insulated from each other by grid electrode insulating layer 7 between 1 U-shaped structure of H-shaped gate electrode 8 and monocrystalline silicon thin film, H-shaped gate electrode 8
Between 1 U-shaped structure groove inboard portion lower surface of monocrystalline silicon thin film and grid electrode insulating layer 7 have dielectric resistance
The partial region of barrier 13, H-shaped gate electrode 8 is only to the upper area of the two sides vertical component of 1 U-shaped structure of monocrystalline silicon thin film
Front and rear surfaces and inner surface, i.e., intrinsic region a 3 interchangeable to source and drain and the interchangeable intrinsic region b 4 of source and drain have obvious field-effect to control
Effect, and to 1 U-shaped structure of lower zone and monocrystalline silicon thin film of the two sides vertical component of monocrystalline silicon thin film 1U shape structure
Bottom horizontal portion region does not have obvious field-effect control action；The interchangeable electrode a 9 of source and drain is made of metal material, is located at the
The top of the two interchangeable area a 5 of class impurity heavy doping source and drain；The interchangeable electrode b 10 of source and drain is also made of metal material, is located at the
The top of the two interchangeable area b 6 of class impurity heavy doping source and drain, the interchangeable electrode a 9 of source and drain, the interchangeable electrode b 10 of source and drain and H-shaped
It is insulated from each other by insulating medium barrier layer 13 between these three electrodes of gate electrode 8；The left and right two of first kind impurity heavily doped region 2
Side is in symmetrical structure, can be realized in the case where the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain are symmetrically exchanged
Same output characteristics.
The present invention provides a kind of H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor, has symmetrical structure special
Sign, the voltage by adjusting the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain control the second class impurity heavy-doped source
It leaks interchangeable area a 5 and the interchangeable area b 6 of the second class impurity heavy doping source and drain is used as source region or drain region, change tunnelling current side
To making device realize the symmetrical interchangeable characteristic of source and drain of bidirectional tunneling conducting.
By first kind impurity heavily doped region 2 be N-type impurity for, when the interchangeable area a 5 of the second class impurity heavy doping source and drain,
There are when potential difference between the second interchangeable area b 6 of class impurity heavy doping source and drain, and when H-shaped gate electrode 8 is in the reverse-biased shape of negative pressure
State, by gate electrode field-effect function influence, the interchangeable area a 5 of the second class impurity heavy doping source and drain can be to the interchangeable intrinsic region of source and drain
A 3 provides hole, the interchangeable area b 6 of the second class impurity heavy doping source and drain can provide hole to the interchangeable intrinsic region b 4 of source and drain, because
This can generate hole in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain and accumulate, so that source and drain interchangeable
The sign area a 3 and interchangeable intrinsic region b 4 of source and drain shows p-type state at this time, and the hole accumulated makes source and drain interchangeable intrinsic
(i.e. source region, drain region are in low-resistance to resistance decrease under the action of H-shaped gate electrode 8 by area a 3 and the interchangeable intrinsic region b 4 of source and drain
State), but the first kind impurity heavy doping due to the source and drain for showing p-type feature interchangeable intrinsic region a 3 and being at this time N-type at this time
Area 2 forms reverse-biased PN junction structure under drain-source voltage, and since first kind impurity heavily doped region 2 is not controlled by H-shaped gate electrode 8
System, because without changing its conductivity type due to change due to 8 voltage of H-shaped gate electrode, transistor under reverse-biased,
Since there are reverse-biased PN junction structure, high resistant blocking state is integrally presented in transistor；The voltage being applied with H-shaped gate electrode 8
It is gradually risen up near flat-band voltage from negative voltage, the second interchangeable area a 5 of class impurity heavy doping source and drain will not can be mutual to source and drain
Change intrinsic region a 3 a large amount of holes are provided, the second interchangeable area b 6 of class impurity heavy doping source and drain will not be to the interchangeable intrinsic region of source and drain
B 4 provides a large amount of holes, simultaneously because at this time in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain field strength compared with
Low, band curvature degree is smaller, therefore will not leading in the source and drain interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain
A large amount of tunelling electrons holes pair are generated between band and valence band, therefore interchangeable intrinsic in the interchangeable intrinsic region a 3 of source and drain and source and drain
Both a large amount of hole accumulations can not form in area b 4, also can not form a large amount of electronics accumulations, the interchangeable intrinsic region a 3 of the source and drain of transistor
It is in high-impedance state (i.e. source region and drain region are in high-impedance state) with the interchangeable intrinsic region b 4 of source and drain, therefore entire transistor
It does not have obvious electric current to flow through, device has outstanding turn-off characteristic and Sub-Threshold Characteristic at this time；As H-shaped gate electrode 8 is applied
The voltage added further rises to forward bias condition by flat-band voltage, and the interchangeable intrinsic region a 3 of source and drain and source and drain can be mutual at this time
It changes in intrinsic region b 4 by 8 field-effect function influence of H-shaped gate electrode, it may appear that larger electric field strength and stronger band curvature, therefore
Apparent tunnel-effect can occur, so that forming a large amount of electricity in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain
Sub- hole pair, wherein hole caused by the interchangeable intrinsic region of source and drain as source region one end can be via the second class impurity at the end
The interchangeable area's discharge of heavy doping source and drain, generated electrons are used as drain region one end via the flow direction of first kind impurity heavily doped region 2
The interchangeable intrinsic region of source and drain, it is empty with the valence band as caused by tunnel-effect in the interchangeable intrinsic region of source and drain as drain region one end
Cave occurs compound.And the conduction band electron as caused by tunnel-effect can be via in the interchangeable intrinsic region of source and drain as drain region one end
It is compound with the generation of its valence band hole as the second interchangeable area of class impurity heavy doping source and drain in drain region, pass through above-mentioned physical process
Form continuous conducting electric current.Since concentration of electron-hole pairs caused by tunnel-effect can be applied with H-shaped gate electrode 8
The rising of voltage and gradually rise, the concentration of electron-hole pairs increase caused by the tunnel-effect to a certain extent when, transistor
Forward conduction state is transitted to by sub-threshold status.
To reach device function of the present invention, the present invention proposes a kind of H-shaped grid-control source and drain symmetrically interchangeable type
Tunneling transistor, nuclear structure feature are as follows:
Device of the present invention is a kind of H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor, the knot with H-shaped grid
Structure contacts with each other with the outer surface of grid electrode insulating layer 7, and forms three faces to grid electrode insulating layer 7 and surround, and overlooks viewing and is in
Existing English capitalization H-shaped structure feature, the upper portion of the two sides vertical component of U-shaped structure is formed by monocrystalline silicon thin film 1
Point, i.e., intrinsic region a 3 interchangeable to source and drain and the interchangeable intrinsic region b 4 of source and drain have apparent field-effect control action, work as H-shaped
When gate electrode 8 is in positively biased state, in contrast to planar structure, the electric field strength near 8 corner region of H-shaped gate electrode can be obtained
To reinforcement, lead to generate the probability of carrier in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain same
Increase under gate voltage, so that subthreshold swing is declined, forward conduction electric current is increased；
The two sides of 13 part of insulating medium barrier layer of first kind impurity heavily doped region 2 and its top are in symmetrical structure.The
A kind of impurity heavily doped region 2 and the interchangeable area a 5 of the second class impurity heavy doping source and drain, first kind impurity heavily doped region 2 and second
The interchangeable area b 6 of class impurity heavy doping source and drain is respectively provided with opposite impurity type.When the gate electrode to two sides applies reversely simultaneously
When voltage, had accumulated near the surface that the top two sides of monocrystalline silicon thin film 1 are contacted with grid electrode insulating layer 7 largely with the second class
The identical carrier of impurity heavily doped region majority carrier type, these and the second class impurity heavily doped region majority carrier type
Identical carrier flows through source and drain interchangeable intrinsic region under the action of drain electrode voltage and reaches first kind impurity heavily doped region 2,
And it is multiple in the generation opposite with conduction type with the majority carrier of first kind impurity heavily doped region of first kind impurity heavily doped region 2
Close, due to first kind impurity heavily doped region 2 be high-dopant concentration region, it is sufficient to by from the interchangeable intrinsic region of source and drain these with
The identical carrier of second class impurity heavily doped region majority carrier type almost it is compound fall, and due to as source region side
The interchangeable intrinsic region of source and drain and first kind impurity heavily doped region 2 between be in reverse-biased high-impedance state, therefore at this time in source and drain side
Apparent electric current will not be generated upwards to generate, this structure significantly reduces the reverse leakage electricity of tunnelling type field effect transistor
Stream, and device is allowed to obtain higher forward and reverse electric current ratio.The symmetrical structure as possessed by device of the present invention leads to
It crosses the interchangeable electrode a 9 of control source and drain and the interchangeable electrode b 10 of source and drain switches the second interchangeable area a of class impurity heavy doping source and drain
5 and second the interchangeable area b 6 of class impurity heavy doping source and drain be used as source region or drain region, will not influence the output characteristics of device, because
This may be implemented such as the interchangeable two-way switch characteristic of the source and drain of MOSFETs device.Grid electrode insulating layer 7 is for generating tunnel
Wear the insulation material layer of electric current.
A kind of unit of the symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain proposed by the invention is in SOI wafer
Specific manufacturing technology steps it is as follows:
Step 1: as shown in Figure 4, Figure 5 and Figure 6, providing a SOI wafer, and bottom is the silicon substrate 12 of SOI wafer,
The upper surface of silicon substrate is substrate insulating layer 11, and the upper surface of substrate insulating layer 11 is monocrystalline silicon thin film 1, passes through ion implanting or expansion
Day labor skill adulterates the intermediate region of the monocrystalline silicon thin film 1 above SOI wafer, preliminarily forms first kind impurity heavily doped region 2；
Step 2: as shown in Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 and Figure 12, part list is removed by photoetching, etching technics
Polycrystal silicon film 1 and first kind impurity heavily doped region 2 form monocrystalline silicon thin film 1 and first kind impurity heavily doped region in SOI wafer
2；
Step 3: as shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18, in the monocrystalline silicon thin film 1 of bottom and first
The outer surface of 1 left and right sides intermediate raised portion of upper surface and monocrystalline silicon thin film of class impurity heavily doped region 2, passes through oxidation
Or deposit, etching technics, form grid electrode insulating layer 7；
Step 4: as shown in Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24, through depositing technics, in SOI wafer
Side's deposit dielectric, planarization surface preliminarily forms SI semi-insulation dielectric barrier to the upper surface for exposing monocrystalline silicon thin film 1
13；
Step 5: as shown in Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 and Figure 30, by etching technics, in step 4
The insulating medium barrier layer 13 of deposit carries out partial etching, is further formed insulating medium barrier layer 13；
Step 6: as shown in Figure 31, Figure 32, Figure 33, Figure 34, Figure 35 and Figure 36, metal or more is deposited above SOI wafer
Crystal silicon, planarization surface to the upper surface for exposing monocrystalline silicon thin film 1, forms H-shaped gate electrode 8；
Step 7: as shown in Figure 37, Figure 38 and Figure 39, by ion implantation technology, to the left and right sides of monocrystalline silicon thin film 1
The upper surface intermediate region of vertical component is doped, and forms the interchangeable area a 5 of the second class impurity heavy doping source and drain and the second class
The interchangeable area b 6 of impurity heavy doping source and drain；
Step 8: as shown in Figure 40, Figure 41 and Figure 42, by oxidation or depositing technics, insulation is deposited above SOI wafer
Medium forms the insulating medium barrier layer 13 of rest part；The second class impurity weight is removed by etching technics behind planarization surface
The insulating medium barrier layer 13 of 6 top the interchangeable area a 5 of doped source and drain and the interchangeable area b of the second class impurity heavy doping source and drain to
Expose the upper surface of the interchangeable area a 5 of the second class impurity heavy doping source and drain and the second interchangeable area b 6 of class impurity heavy doping source and drain,
Metal is injected in the through-hole formed again by depositing technics to etching or polysilicon to through-hole is completely filled, and finally puts down surface
Smoothization processing, forms the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain.
Claims (2)
1. a kind of symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain, the silicon substrate (12) comprising SOI wafer, feature exists
In: it is the substrate insulating layer (11) of SOI wafer above the silicon substrate (12) of SOI wafer, the substrate insulating layer (11) of SOI wafer
Top is monocrystalline silicon thin film (1), first kind impurity heavily doped region (2)；Monocrystalline silicon thin film (1) has U-shaped structure feature, is impurity
Concentration is lower than 1016cm-3Single-crystal semiconductor material；First kind impurity heavily doped region (2) is located at monocrystalline silicon thin film (1) U-shaped knot
The intermediate region of the bottom horizontal portion of structure, the conduction type of impurity determine the conductivity type of device, inside not by H
(8) field-effect of shape gate electrode influences control, is not less than 10 for impurity concentration17cm-3Semiconductor material；Second class impurity is heavily doped
The miscellaneous interchangeable area a(5 of source and drain) and the second interchangeable area b(6 of class impurity heavy doping source and drain) respectively by monocrystalline silicon thin film (1) institute
The upper section of the two sides vertical component of the U-shaped structure of formation adulterates to be formed, and impurity peak concentration is not less than 1018cm-3, wherein
The second interchangeable area a(5 of class impurity heavy doping source and drain) front and rear surfaces and inner surface and the interchangeable intrinsic region a(3 of source and drain) phase
Mutually contact, and by thirdly face surrounds；The second interchangeable area b(6 of class impurity heavy doping source and drain) front and rear surfaces and inner surface with
The interchangeable intrinsic region b(4 of source and drain) it contacts with each other, and by thirdly face surrounds；The interchangeable intrinsic region a(3 of source and drain) and source and drain it is interchangeable
Intrinsic region b(4) it is located at the front and rear surfaces of upper area of two sides vertical component of monocrystalline silicon thin film (1) U-shaped structure and interior
Surface is lower than 10 for impurity concentration16cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film (1), first kind impurity heavily doped region
(2), the interchangeable intrinsic region a(3 of source and drain), the interchangeable intrinsic region b(4 of source and drain), the second interchangeable area a of class impurity heavy doping source and drain
(5) and the second interchangeable area b(6 of class impurity heavy doping source and drain) collectively constituted a U-shaped structure；Grid electrode insulating layer (7) position
In the upper surface of monocrystalline silicon thin film (1) U-shaped structure bottom horizontal portion and front and rear surfaces and monocrystalline silicon thin film (1) U-shaped structure
The inner surface and front and rear surfaces of two sides vertical component；H-shaped gate electrode (8) is made of metal material or polycrystalline silicon material, to list
The inner surface and front and rear surfaces of the upper section of the two sides vertical component of polycrystal silicon film (1) U-shaped structure form three bread and wrap up in, and bow
Depending on SOI wafer, H-shaped gate electrode (8) is in English capitalization H shape, H-shaped gate electrode (8) and monocrystalline silicon thin film along source and drain direction
(1) insulated from each other by grid electrode insulating layer (7) between U-shaped structure, H-shaped gate electrode (8) is located at monocrystalline silicon thin film (1) U-shaped
With the part area of insulating medium barrier layer (13) between the lower surface and grid electrode insulating floor (7) of texture grooves inboard portion
Domain, H-shaped gate electrode (8) only front and rear surfaces to the upper area of the two sides vertical component of monocrystalline silicon thin film (1) U-shaped structure and interior
Surface, i.e., intrinsic region a(3 interchangeable to source and drain) and the interchangeable intrinsic region b(4 of source and drain) there is obvious field-effect control action, and it is right
The lower zone of the two sides vertical component of monocrystalline silicon thin film (1) U-shaped structure and the bottom water of monocrystalline silicon thin film (1) U-shaped structure
Flat partial region does not have obvious field-effect control action；The interchangeable electrode a(9 of source and drain) it is made of metal material, it is located at the second class
The interchangeable area a(5 of impurity heavy doping source and drain) top；The interchangeable electrode b(10 of source and drain) also it is made of metal material, it is located at second
The interchangeable area b(6 of class impurity heavy doping source and drain) top, the interchangeable electrode a(9 of source and drain), the interchangeable electrode b(10 of source and drain) and H
It is insulated from each other by insulating medium barrier layer (13) between shape gate electrode (8) these three electrodes；First kind impurity heavily doped region (2)
The left and right sides be in symmetrical structure, can in the interchangeable electrode a(9 of source and drain) and the interchangeable electrode b(10 of source and drain) symmetrically exchange
In the case of realize same output characteristics.
2. a kind of manufacturing method of the symmetrical interchangeable type tunneling transistor of H-shaped grid-control source and drain as described in claim 1, feature exist
In:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate (12) of SOI wafer, and the upper surface of silicon substrate is substrate insulation
The upper surface of layer (11), substrate insulating layer (11) is monocrystalline silicon thin film (1), by ion implanting or diffusion technique, to SOI wafer
The intermediate region of the monocrystalline silicon thin film (1) of top is adulterated, and first kind impurity heavily doped region (2) is preliminarily formed；
Step 2: part monocrystalline silicon thin film (1) and first kind impurity heavily doped region (2), In are removed by photoetching, etching technics
Monocrystalline silicon thin film (1) and first kind impurity heavily doped region (2) are formed in SOI wafer；
Step 3: in the monocrystalline silicon thin film (1) of bottom and upper surface and the monocrystalline silicon thin film of first kind impurity heavily doped region (2)
(1) outer surface of left and right sides intermediate raised portion forms grid electrode insulating layer by aoxidizing or depositing, etching technics
(7)；
Step 4: by depositing technics, depositing dielectric above SOI wafer, and planarization surface is to exposing monocrystalline silicon thin film
(1) upper surface preliminarily forms SI semi-insulation dielectric barrier (13)；
Step 5: by etching technics, partial etching is carried out to the insulating medium barrier layer (13) deposited in step 4, into one
Step forms insulating medium barrier layer (13)；
Step 6: metal or polysilicon, planarization surface to the upper table for exposing monocrystalline silicon thin film (1) are deposited above SOI wafer
Face is formed H-shaped gate electrode (8)；
Step 7: by ion implantation technology, to the upper surface intermediate region of the left and right sides vertical component of monocrystalline silicon thin film (1)
It is doped, forms the second interchangeable area a(5 of class impurity heavy doping source and drain) and the second interchangeable area b of class impurity heavy doping source and drain
(6)；
Step 8: by depositing technics, depositing dielectric above SOI wafer, and the dielectric for forming rest part stops
Layer (13)；Planarize surface after by etching technics removal the second interchangeable area a(5 of class impurity heavy doping source and drain) and the second class it is miscellaneous
The interchangeable area b(6 of matter heavy doping source and drain) above insulating medium barrier layer (13) to expose the second class impurity heavy doping source and drain can
Exchange area a(5) and the second interchangeable area b(6 of class impurity heavy doping source and drain) upper surface, then by depositing technics to etching formation
Through-hole in injection metal to through-hole be completely filled, finally surface planarisation is handled, formed the interchangeable electrode a(9 of source and drain)
With the interchangeable electrode b(10 of source and drain).
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| 具有辅助栅的新型低泄露U沟道无结场效应晶体管;杨光锐等;《科技创新导报》;20170610(第16期);第46-50页 * |
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