CN107819028B - H-shaped grid-control source and drain resistive formula conduction type is adjustable transistor npn npn and its manufacturing method - Google Patents
H-shaped grid-control source and drain resistive formula conduction type is adjustable transistor npn npn and its manufacturing method Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The present invention relates to a kind of adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing methods, transistor of the present invention has H-shaped gate electrode, conduction type regulation grid and symmetrical structure feature, and device of the present invention has the function of that achievable P-type conduction type and N-type conduction type can free switching and two-way switch functions.Have the advantages that low speed paper tape reader static power disspation, low reverse leakage current, stronger grid control ability and low subthreshold swing.In contrast to common MOSFETs type device, more excellent Sub-Threshold Characteristic and switching characteristic are realized using Schottky barrier tunneling effect, reduces the quiescent dissipation of transistor；In contrast to common tunneling field-effect transistor, the present invention has the symmetrically interchangeable two-way switch characteristic of source and drain not available for common tunneling field-effect transistor, realize P-type conduction type that various existing transistor technologies cannot achieve and N-type conduction type can free adjusting function, therefore be suitble to popularization and application.
Description
Technical field
The present invention relates to super large-scale integration manufacturing fields, and in particular to suitable for low power consumption integrated circuit manufacture
The adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing method with low current leakage.
Background technique
What common tunneling field-effect transistor utilized when using as switching-type device is the tunneling mechanism of carrier, can be made
The subthreshold swing of common tunneling field-effect transistor is better than the 60mV/dec limit of MOSFETs type device.However, being based on silicon
The tunneling field-effect transistor of sill, since forbidden bandwidth limits, tunnelling probability is limited, compares MOSFETs type device, it is difficult to
The conducting electric current of same order is generated, more seriously, different conduction-types are respectively adopted in source electrode and drain electrode
Impurity is doped, and is formed by unsymmetric structure feature it is caused to cannot achieve in source electrode and drain electrode and exchange mutually, because
This can not functionally replace the MOSFETs type device with symmetrical structure feature completely.It is with N-type tunneling field-effect transistor
Example, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunneling field-effect crystal at this time
Pipe, always belongs to forward bias condition since source and drain is formed by PN junction, then gate electrode can not well control conducting electric current at this time
Size so that the failure of entire tunneling field-effect transistor.
Schottky barrier field effect transistor, using Schottky barrier tunnelling as conducting mechanism, due to tunneling barrier height
Degree lower than tunnel field-effect transistor forbidden bandwidth, it can be achieved that bigger tunnelling probability, and using metal as incidence end, In
Electron impact amounts more more than semiconductor conduction band or valence band can be achieved under same area size, and then obtain bigger tunnel-effect
Current density, therefore conducting current density more higher than tunneling field-effect transistor can be obtained.However common Schottky gesture
Building the gate electrode switching characteristic that field effect transistor is realization device, (gate electrode forward conduction reversely ends or reverse-conducting is positive
Cut-off), source region to device or drain region carry out the impurity doping of specific conductivity type, this to be difficult in technique in source electricity
Between pole and source region, good Schottky contacts are realized between drain electrode and drain region, and the doping to source region and drain region is so that grid
Electrode reduces the control ability in drain region and source region, and the switch performance of device is caused to decline.If not to the semiconductor regions of device
Doping, though the Schottky barrier between source electrode and source region, drain electrode and drain region is then easily achieved in technique, however this can make
It obtains device and generates different types of carrier conducting in forward and reverse, i.e., can make under gate electrode forward bias and reverse biased
It is in the conductive state to obtain device, so that grid loses the control action as devices switch device.
In addition to this, it is based on existing transistor technology, once the structure of transistor is established, conduction type is according to doping
The difference of impurity conduction type, conduction type are also established therewith, and manufactured transistor is only P-type transistor or N-type
Transistor is one such, and conduction type not can be switched at work.That is, can not pass through in the transistor course of work
Certain control method changes its conduction type.
Summary of the invention
Goal of the invention:
In contrast to current MOSFETs technology, tunneling transistor technology and Schotthy barrier transistor technology, work as to make up
Various above-mentioned disadvantages of preceding MOSFETs, tunneling transistor and Schotthy barrier transistor technology, and realize mutual supplement with each other's advantages, and
Enabling transistor its conduction type of free switching in the course of work is N type or P type, and the present invention proposes there is low Asia
The working characteristics of the threshold value amplitude of oscillation, high forward conduction electric current, and have source electrode, drain electrode interchangeable and the interchangeable function of conduction type
The adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing method of energy.Its core purpose is that device is made to exist
While being functionally fully compatible with MOSFETs technology, the height with low subthreshold swing, high conducting electric current and low current leakage
The working characteristics such as forward and reverse electric current ratio, while transistor being made to have conduction type not available for the technologies such as MOSFETs changeable
New logic function, the function can increase the logic function of integrated circuit, expand the design method of integrated circuit.
Technical solution:
The present invention is achieved through the following technical solutions:
A kind of adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type, the silicon substrate comprising SOI wafer, SOI wafer
Silicon substrate above be SOI wafer substrate insulating layer, the top of the substrate insulating layer of SOI wafer is monocrystalline silicon thin film, conduction
Type regulates and controls the partial region of grid, grid electrode insulating layer and insulating medium barrier layer, and monocrystalline silicon thin film has concave several
What feature is lower than 10 for impurity concentration16cm-3Single-crystal semiconductor material, monocrystalline silicon thin film is formed by groove type structure
Side surface and front and back outer surface have grid electrode insulating layer；The interchangeable area a of the metal source and drain and interchangeable area b of metal source and drain is gold
Belong to material, is respectively formed in the intermediate region that monocrystalline silicon thin film is formed by vertical component upper end at left and right sides of groove structure；Gold
The front and rear surfaces and inner surface and the interchangeable intrinsic region a of source and drain for belonging to the interchangeable area a of source and drain mutually form Schottky contacts, and by
Thirdly face surrounds；The front and rear surfaces and inner surface and the interchangeable intrinsic region b of source and drain of the interchangeable area b of metal source and drain mutually form Xiao
Te Ji contact, and by thirdly face surrounds；The lower surface of the interchangeable area a of metal source and drain and monocrystalline silicon thin film mutually form schottky junctions
Touching, the lower surface of the interchangeable area b of metal source and drain and monocrystalline silicon thin film mutually form Schottky contacts；The interchangeable intrinsic region a of source and drain
It is that impurity concentration is lower than 10 with the interchangeable intrinsic region b of source and drain16cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film, source and drain can
Intrinsic region a 3, the interchangeable intrinsic region b of source and drain, the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain is exchanged to collectively constitute
One groove type structure；Grid electrode insulating layer is located at monocrystalline silicon thin film and is formed by the upper of groove type structural base horizontal component
Surface and front and rear surfaces and monocrystalline silicon thin film are formed by the inner surface and front and back table of groove type structure two sides vertical component
Face；H-shaped gate electrode is made of metal material or polycrystalline silicon material, and the two sides for being formed by groove type structure to monocrystalline silicon thin film are hung down
The inner surface and front and rear surfaces of the upper section of straight part form three bread and wrap up in, and overlook SOI wafer, H-shaped gate electrode is along source and drain
Direction is in English capitalization H shape, between H-shaped gate electrode and monocrystalline silicon thin film concave structure each other by grid electrode insulating layer
Insulation, the upper section that H-shaped gate electrode is only formed by the two sides vertical component of groove type structure to monocrystalline silicon thin film have field
Effect control effect, the lower zone and bottom water of the two sides vertical component of groove type structure are formed by monocrystalline silicon thin film
Flat partial region does not have obvious field-effect control action；Conduction type regulation grid are made of metal material or polycrystalline silicon material, position
Upper surface and the front and rear surfaces of groove type structural base horizontal component are formed by monocrystalline silicon thin film, to monocrystalline silicon thin film institute shape
At groove type structural base horizontal component formed three bread wrap up in, and by grid electrode insulating layer and monocrystalline silicon thin film it is insulated from each other
Isolation, conduction type regulation grid, which are only formed by groove type structural base horizontal component to monocrystalline silicon thin film, has field-effect control to make
With there is no obvious field-effect control to make the upper section that monocrystalline silicon thin film is formed by the two sides vertical component of groove type structure
With；H-shaped gate electrode is located at lower surface and the conductive-type for the part that monocrystalline silicon thin film is formed by the inside of the groove of groove type structure
Type regulates and controls the partial region between grid with insulating medium barrier layer, by exhausted between H-shaped gate electrode and conduction type regulation grid
The isolation insulated from each other of edge dielectric barrier；The interchangeable electrode a of source and drain is made of metal material, is located at the interchangeable area a of metal source and drain
Top；The interchangeable electrode b of source and drain is also made of metal material, and positioned at the top of the interchangeable area b of metal source and drain, source and drain is interchangeable
It is insulated from each other by insulating medium barrier layer between the interchangeable electrode b of electrode a, source and drain and H-shaped gate electrode these three electrodes；It is conductive
The left and right sides that type regulates and controls grid is in symmetrical structure, can symmetrically be exchanged in the interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain
In the case of realize same output characteristics.
A kind of adjustable specific manufacturing step of transistor npn npn preparation method of H-shaped grid-control source and drain resistive formula conduction type is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate of SOI wafer, and the upper surface of silicon substrate is substrate insulation
Layer, the upper surface of substrate insulating layer is monocrystalline silicon thin film, thin to the monocrystalline silicon above SOI wafer by photoetching or etching technics
Film performs etching, and removes front and rear sides and the subregional monocrystalline silicon thin film of middle part, and being formed has groove type structure feature
Monocrystalline silicon thin film；
Step 2: by aoxidizing or depositing, etching technics, before and after monocrystalline silicon thin film is formed by groove type structure outside
The overhead surface of the inner surface and bottom portion of groove horizontal component of side surface and groove two sides vertical component forms grid electrode insulating
Layer；
Step 3: depositing dielectric above SOI wafer, is planarized to surface and exposes monocrystalline silicon thin film, preliminarily forms
Insulating medium barrier layer；
Step 4: by etching technics, to being located at monocrystalline silicon thin film groove structure bottom level formed in step 3
The SI semi-insulation dielectric barrier of partial front and rear surfaces is performed etching to grid electrode insulating layer is exposed, and is further formed insulation and is situated between
Matter barrier layer；
Step 5: by depositing technics, depositing metal or polysilicon above SOI wafer, and planarization surface is to exposing list
Polycrystal silicon film preliminarily forms conduction type regulation grid；
Step 6: it first passes through etching technics and etches away monocrystalline silicon thin film and be formed by the upper of groove structure bottom horizontal portion
The insulating medium barrier layer of side is depositing metal or more by depositing technics to grid electrode insulating layer is exposed above SOI wafer
Crystal silicon planarizes surface to monocrystalline silicon thin film is exposed, and is further formed conduction type regulation grid；
Step 7: step 6 is etched away by etching technics and is formed by the upper area that conduction type regulates and controls grid, into one
Step forms conduction type regulation grid；
Step 8: by depositing technics, depositing dielectric above SOI wafer, and planarization surface is to exposing monocrystalline silicon
Film is further formed insulating medium barrier layer；
Step 9: by photoetching or etching technics, the SI semi-insulation dielectric barrier formed in step 8 is carried out
Partial etching, then metal or polysilicon are deposited above SOI wafer, planarization surface forms H-shaped grid to monocrystalline silicon thin film is exposed
Electrode；
Step 10: the two sides vertical component upper surface of groove structure is formed by monocrystalline silicon thin film by etching technics
Intermediate exterior portion performs etching, then deposits metal above SOI wafer by depositing technics, and planarization surface is to exposing monocrystalline
Silicon thin film makes the interchangeable area a of metal source and drain and metal so as to form the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain
The interchangeable area b of source and drain is located at outside the centre that monocrystalline silicon thin film is formed by above the left and right sides vertical component of groove structure
Side section, and wrapped up in by the interchangeable intrinsic region a of source and drain and interchangeable tri- bread of intrinsic region b of source and drain, make outside the interchangeable area a of metal source and drain
Contact portion, metal source and drain interchangeable area a lower surface bottom sidewall and monocrystalline silicon are thin between side wall and the interchangeable intrinsic region a of source and drain
Contact portion and source metal between the interchangeable area b lateral wall of contact portion, metal source and drain and the interchangeable intrinsic region b of source and drain between film
It leaks contact portion between interchangeable area b lower surface bottom sidewall and monocrystalline silicon thin film and forms Schottky contacts, form metal source and drain
The interchangeable area a and interchangeable area b of metal source and drain；
Step 11: by depositing technics, depositing dielectric above SOI wafer, and the insulation for forming rest part is situated between
Matter barrier layer；It is removed above the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain after planarizing surface by etching technics
Insulating medium barrier layer to the upper surface for exposing metal source and drain interchangeable area a and the interchangeable area b of metal source and drain, then pass through deposit
Injection metal to through-hole is completely filled in the through-hole that technique is formed to etching, finally handles surface planarisation, forms source and drain
The interchangeable electrode a and interchangeable electrode b of source and drain.
Advantage and effect:
The invention has the following advantages and beneficial effects:
1. the realization that N-type conduction and P-type conduction can arbitrarily switch function；
Once existing transistor structure is established, conduction type is also established simultaneously, and device of the present invention is a kind of H-shaped grid
The adjustable transistor npn npn of source and drain resistive formula conduction type and its manufacturing method are controlled, is height by the voltage that setting conduction type regulates and controls grid
Current potential, to source and drain both ends, in the work of H-shaped gate electrode, the generated tunneled holes under low potential form potential barrier blocking, to source and drain two
In the work of H-shaped gate electrode, the generated tunelling electrons under high potential form communication channel at end, and make transistor by the mode
Work is in N-type state；Similarly, regulating and controlling the voltage of grid by setting conduction type is low potential, to source and drain both ends in H-shaped gate electrode
Work generated tunelling electrons under high potential, which form potential barrier, to be stopped, and is worked in low potential in H-shaped gate electrode source and drain both ends
Tunneled holes caused by lower form communication channel, and make transistor work in p-type state by the mode；
2. the symmetrical interchangeable two-way switch characteristic of source and drain；
Device of the present invention is the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing method, list
The left and right ends of polycrystal silicon film are respectively provided with tunneling structure independent of each other close to the part of grid electrode insulating layer, since device has
There is bilateral symmetry, under the control action of H-shaped gate electrode, monocrystalline silicon thin film left and right ends are contacted with grid electrode insulating layer
Surface tunnelling nearby occurs simultaneously, in conjunction with conduction type regulation grid to the regulating and controlling effect of monocrystalline silicon thin film center portion potential,
So that device is formed forward conduction and reversed blocking, passes through the voltage control for adjusting source and drain interchangeable electrode a and the interchangeable electrode b of source and drain
The interchangeable area a and interchangeable area b of metal source and drain of metal source and drain processed is as source region or drain region, therefore changeable tunnelling current direction,
Realize source and drain of the invention symmetrically interchangeable two-way switch characteristic.
3. low subthreshold swing and high conducting electric current characteristic；
Due to the present invention be by the change of H-shaped gate electrode voltage, to control the power of Schottky barrier tunnel-effect, into
And realize that the resistance value in transistor source region and drain region changes, the source region caused by Schottky barrier tunnel-effect and drain region carry
Common MOSFETs device stack layer caused by channel will be significantly larger than to the sensibility of gate electrode voltage by flowing sub- concentration variation
Or inversion-layer electrons concentration changes the sensibility to gate electrode voltage, therefore may be implemented lower than common MOSFETs type device
Subthreshold swing.And since the height of Schottky barrier is less than the forbidden bandwidth of semiconductor, and the incoming particle concentration of metal
Higher than the incoming particle concentration of semiconductor energy gap, while H-shaped gate electrode is used, since H-shaped gate electrode is distinguished in three directions
Intrinsic region b interchangeable to the interchangeable intrinsic region a and source and drain of source and drain two sides forms three bread and wraps up in, and controls with outstanding gate electrode
Ability makes it possible to band and is easier to bend under identical gate voltage under the control action of H-shaped gate electrode, obtains bigger
Electric field strength, comparison tunneling field-effect transistor higher forward conduction electric current may be implemented.
4. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio；
By taking device works in N-type state as an example, exist when between the interchangeable area a of metal source and drain, the interchangeable area b of metal source and drain
When potential difference, and when H-shaped gate electrode is in subthreshold value or reverse-biased, since conduction type regulation grid always work at positively biased shape
The potential of state, the interchangeable intrinsic region a of source and drain and the interchangeable intrinsic region b of source and drain positioned at monocrystalline silicon thin film two sides is thin lower than monocrystalline silicon
Film middle section by conduction type regulation gate control part potential, by the field-effect of H-shaped gate electrode control source and drain can
Exchanging the intrinsic region a and interchangeable intrinsic region b of source and drain can not be by being led by the hole that Schottky barrier tunnel-effect is accumulated
Electric type regulation gate control in the formed potential barrier in monocrystalline silicon thin film middle section, that is, since conduction type regulates and controls the control of grid
Effect, the interchangeable area a of metal source and drain and metal source and drain can be effectively blocked in by being formed by potential barrier in monocrystalline silicon thin film middle section
Between interchangeable area b, between the interchangeable intrinsic region a of source and drain and the interchangeable intrinsic region b of source and drain hole current formation.Therefore originally
Invention has the advantages that low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio.
Detailed description of the invention
Fig. 1 is the top view of the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type of the present invention；
Fig. 2 is the sectional view along dotted line A of the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type of the present invention；
Fig. 3 is the sectional view along dotted line B of the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type of the present invention；
Fig. 4 is the top view of step 1；
Fig. 5 is the sectional view along dotted line A of step 1；
Fig. 6 is the sectional view along dotted line B of step 1；
Fig. 7 is the sectional view along dotted line C of step 1；
Fig. 8 is the top view of step 2；
Fig. 9 is the sectional view along dotted line A of step 2；
Figure 10 is the sectional view along dotted line B of step 2；
Figure 11 is the sectional view along dotted line C of step 2；
Figure 12 is the sectional view along dotted line D of step 2；
Figure 13 is the sectional view along dotted line E of step 2；
Figure 14 is the top view of step 3；
Figure 15 is the sectional view along dotted line A of step 3；
Figure 16 is the sectional view along dotted line B of step 3；
Figure 17 is the sectional view along dotted line C of step 3；
Figure 18 is the sectional view along dotted line D of step 3；
Figure 19 is the sectional view along dotted line E of step 3；
Figure 20 is the top view of step 4；
Figure 21 is the sectional view along dotted line A of step 4；
Figure 22 is the sectional view along dotted line B of step 4；
Figure 23 is the top view of step 5；
Figure 24 is the sectional view along dotted line A of step 5；
Figure 25 is the sectional view along dotted line B of step 5；
Figure 26 is the top view of step 6；
Figure 27 is the sectional view along dotted line A of step 6；
Figure 28 is the sectional view along dotted line B of step 6；
Figure 29 is the sectional view along dotted line C of step 6；
Figure 30 is the top view of step 7；
Figure 31 is the sectional view along dotted line A of step 7；
Figure 32 is the sectional view along dotted line B of step 7；
Figure 33 is the sectional view along dotted line C of step 7；
Figure 34 is the top view of step 8；
Figure 35 is the sectional view along dotted line A of step 8；
Figure 36 is the sectional view along dotted line B of step 8；
Figure 37 is the sectional view along dotted line C of step 8；
Figure 38 is the top view of step 9；
Figure 39 is the sectional view along dotted line A of step 9；
Figure 40 is the sectional view along dotted line B of step 9；
Figure 41 is the sectional view along dotted line C of step 9；
Figure 42 is the top view of step 10；
Figure 43 is the sectional view along dotted line A of step 10；
Figure 44 is the sectional view along dotted line B of step 10；
Figure 45 is the top view of step 11；
Figure 46 is the sectional view along dotted line A of step 11；
Figure 47 is the sectional view along dotted line B of step 11.
Description of symbols:
1, monocrystalline silicon thin film；2, conduction type regulates and controls grid；3, the interchangeable intrinsic region a of source and drain；4, the interchangeable intrinsic region of source and drain
b；5, the interchangeable area a of metal source and drain；6, the interchangeable area b of metal source and drain；7, grid electrode insulating layer；8, H-shaped gate electrode；9, source and drain can
Staggered poles a；10, the interchangeable electrode b of source and drain；11, substrate insulating layer；12, silicon substrate；13, insulating medium barrier layer.
Specific embodiment
Following further describes the present invention with reference to the drawings:
As shown in Figure 1, Figure 2 and Figure 3, the adjustable transistor npn npn of a kind of H-shaped grid-control source and drain resistive formula conduction type includes SOI
The silicon substrate 12 of wafer is the substrate insulating layer 11 of SOI wafer, the substrate insulation of SOI wafer above the silicon substrate 12 of SOI wafer
The top of layer 11 is the portion of monocrystalline silicon thin film 1, conduction type regulation grid 2, grid electrode insulating layer 7 and insulating medium barrier layer 13
Subregion, monocrystalline silicon thin film 1 have concave geometrical characteristic, are lower than 10 for impurity concentration16cm-3Single-crystal semiconductor material
Material, monocrystalline silicon thin film 1 are formed by groove type structure inner surface and front and back outer surface with grid electrode insulating layer 7；Metal
The interchangeable area a 5 of the source and drain and interchangeable area b 6 of metal source and drain is metal material, is respectively formed in monocrystalline silicon thin film 1 and is formed by
The intermediate region of vertical component upper end at left and right sides of groove structure；The front and rear surfaces and inside table of the interchangeable area a 5 of metal source and drain
Face and the interchangeable intrinsic region a 3 of source and drain mutually form Schottky contacts, and by thirdly face surrounds；The interchangeable area b 6 of metal source and drain
Front and rear surfaces and inner surface and the interchangeable intrinsic region b 4 of source and drain mutually form Schottky contacts, and by thirdly face surrounds；Gold
The lower surface and monocrystalline silicon thin film 1 for belonging to the interchangeable area a 5 of source and drain mutually form Schottky contacts, the interchangeable area b 6 of metal source and drain
Lower surface and monocrystalline silicon thin film 1 mutually form Schottky contacts；The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region of source and drain
B 4 is that impurity concentration is lower than 1016cm-3Single-crystal semiconductor material；The interchangeable intrinsic region a 3 of monocrystalline silicon thin film 1, source and drain, source
It leaks the interchangeable area a 5 of interchangeable intrinsic region b 4, metal source and drain and the interchangeable area b 6 of metal source and drain has collectively constituted a groove
Shape structure；Grid electrode insulating layer 7 is located at monocrystalline silicon thin film 1 and is formed by the upper surface of groove type structural base horizontal component with before
Rear surface and monocrystalline silicon thin film 1 are formed by the inner surface and front and rear surfaces of groove type structure two sides vertical component；H-shaped grid
Electrode 8 is made of metal material or polycrystalline silicon material, and the two sides vertical component of groove type structure is formed by monocrystalline silicon thin film 1
Upper section inner surface and front and rear surfaces form three bread and wrap up in, overlook SOI wafer, H-shaped gate electrode 8 is in along source and drain direction
English capitalization H shape, between 1 concave structure of H-shaped gate electrode 8 and monocrystalline silicon thin film each other absolutely by grid electrode insulating layer 7
Edge, the upper section that H-shaped gate electrode 8 is only formed by the two sides vertical component of groove type structure to monocrystalline silicon thin film 1 have field
Effect control effect, lower zone and the bottom of the two sides vertical component of groove type structure are formed by monocrystalline silicon thin film 1
Horizontal component region does not have obvious field-effect control action；Conduction type regulation grid 2 are made of metal material or polycrystalline silicon material,
Upper surface and the front and rear surfaces of groove type structural base horizontal component are formed by positioned at monocrystalline silicon thin film 1, to monocrystalline silicon thin film 1
Be formed by groove type structural base horizontal component and form three bread and wrap up in, and by grid electrode insulating layer 7 and monocrystalline silicon thin film 1 that
This is dielectrically separated from, and conduction type regulation grid 2, which are only formed by groove type structural base horizontal component to monocrystalline silicon thin film 1, field effect
Control action is answered, the upper section for being formed by the two sides vertical component of groove type structure to monocrystalline silicon thin film 1 does not have obvious field
Effect control effect；H-shaped gate electrode 8 is located at monocrystalline silicon thin film 1 and is formed by under the part on the inside of the groove of groove type structure
Partial region with insulating medium barrier layer 13, H-shaped gate electrode 8 and conduction type between surface and conduction type regulation grid 2
Regulate and control and passes through the isolation insulated from each other of insulating medium barrier layer 13 between grid 2；The interchangeable electrode a 9 of source and drain is made of metal material,
Positioned at the top of the interchangeable area a 5 of metal source and drain；The interchangeable electrode b 10 of source and drain is also made of metal material, is located at metal source and drain
The top of interchangeable area b 6, the interchangeable electrode a 9 of source and drain, the interchangeable electrode b 10 of source and drain and H-shaped gate electrode 8 these three electrodes
Between by insulating medium barrier layer 13 it is insulated from each other；The left and right sides that conduction type regulates and controls grid 2 is in symmetrical structure, can be in source and drain
The interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain realizes same output characteristics in the case where symmetrically exchanging.
The present invention provides the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing method, leads with N-type
Electricity can arbitrarily switch functional characteristic with P-type conduction state, and the voltage that grid 2 are regulated and controled by setting conduction type is high potential, to source
Leaking both ends, the generated tunneled holes under low potential form potential barrier blocking in the work of H-shaped gate electrode 8, to source and drain both ends in H-shaped
The work of gate electrode 8 generated tunelling electrons under high potential form communication channel, and make transistor work in N by the mode
Type state；Similarly, it is low potential by the voltage that setting conduction type regulates and controls grid 2, is worked in H-shaped gate electrode 8 source and drain both ends
Generated tunelling electrons form potential barrier and stop under high potential, to source and drain both ends in the work of H-shaped gate electrode 8 institute under low potential
The tunneled holes of generation form communication channel, and make transistor work in p-type state by the mode.
The present invention provides the adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type and its manufacturing method, has left and right
Symmetrical structure, source region and drain region may be implemented that the function of exchange can be exchanged.Since device has left and right pair on source and drain direction
The structure feature of title, therefore can only pass through as the tunneling field-effect transistor of single-way switch different from common and adjust source and drain
The voltage of interchangeable electrode a 9 and the interchangeable electrode b 10 of source and drain control the interchangeable area a 5 of metal source and drain and metal source and drain can be mutual
It changes area b 6 and is used as source region or drain region, change the flow direction of Schottky barrier tunnelling current, device is made to realize bidirectional tunneling conducting
The symmetrical interchangeable characteristic of source and drain, even if device realizes two-way switch characteristic.
When to the conduction type regulation application positive voltage of grid 2, the interchangeable area a 5 of metal source and drain, the interchangeable area b 6 of metal source and drain
Between there are when potential difference, H-shaped gate electrode 8 is such as in reverse-biased, the interchangeable area a 5 of metal source and drain and source and drain interchangeable
The Schottky gesture being respectively formed between sign area a 3, between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Obvious tunnel-effect occurs for base, so that the interchangeable intrinsic region a trivalent having electronic of source and drain flows to source metal by Schottky barrier
Interchangeable area a 5 is leaked, interchangeable 4 valence-band electrons of intrinsic region b of source and drain flow to the interchangeable area b of metal source and drain by Schottky barrier
6, therefore can generate hole in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain and accumulate, so that source and drain can be mutual
It changes intrinsic region a 3 and shows p-type feature at this time, although Schottky barrier tunnel-effect makes the interchangeable intrinsic region a 3 of source and drain at this time
Resistance value is remarkably decreased under the action of H-shaped gate electrode 8 with the interchangeable intrinsic region b 4 of source and drain, but due at this time to conduction type tune
It controls grid 2 and applies positive voltage, by the monocrystalline silicon thin film 1 for being located at 2 lower section of conduction type regulation grid for being controlled in conduction type regulation grid 2
The hole that can be accumulated in intrinsic region a 3 interchangeable to the two sides source and drain and interchangeable intrinsic region b 4 of source and drain of middle section formed
Potential barrier, and the middle section of the monocrystalline silicon thin film 1 due to being located at 2 lower section of conduction type regulation grid is not controlled by H-shaped gate electrode 8
, will not because of 8 voltage of H-shaped gate electrode change and change its barrier height, transistor is in anti-in H-shaped gate electrode 8
High resistant blocking state is integrally presented under inclined state；As the voltage that H-shaped gate electrode 8 is applied gradually rises up to flat rubber belting from negative voltage
Near voltage, between the interchangeable area a 5 of metal source and drain and the interchangeable intrinsic region a 3 of source and drain, the interchangeable area b 6 of metal source and drain and source
Apparent Schottky barrier tunnel effect will not be occurred by leaking the Schottky barrier being respectively formed between interchangeable intrinsic region b 4
It answers, therefore both can not form a large amount of holes in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain and accumulated, shape is not yet
It is accumulated at a large amount of electronics, the interchangeable intrinsic region a 3 of the source and drain of transistor and the interchangeable intrinsic region b 4 of source and drain are in high resistant shape
State, therefore entire transistor does not have obvious electric current and flows through, device has outstanding turn-off characteristic and Sub-Threshold Characteristic at this time；With
The voltage that is applied of H-shaped gate electrode 8 forward bias condition, the interchangeable area a of metal source and drain are further risen to by flat-band voltage
Between 5 and the interchangeable intrinsic region a 3 of source and drain, institute's difference between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Apparent tunnel-effect can occur again for the Schottky barrier of formation, be acted on by the forward voltage of H-shaped gate electrode 8, source metal
The electrons for leaking interchangeable area a 5 pass through tunnel-effect tunnelling to the conduction band of the interchangeable intrinsic region a 3 of source and drain, and metal source and drain can be mutual
The electrons of area b 6 are changed by the conduction band of tunnel-effect tunnelling to the interchangeable intrinsic region b 4 of source and drain, so that source and drain is interchangeable intrinsic
The area a 3 and interchangeable intrinsic region b 4 of source and drain forms a large amount of electronics accumulations, and the electron concentration accumulated is with 8 quilt of H-shaped gate electrode
The voltage of application rises and gradually rises, can be in source and drain side since the grid 2 of conduction type regulation at this time are constantly in high potential
Be upwardly formed good electronic conduction channel, when electron concentration increase to a certain extent when, transistor is by sub-threshold status transition
To forward conduction state.Make device work in N type state mode by the above method, similarly, by regulating and controlling to conduction type
Grid 2 apply negative voltage, and device work can be made in P type state mode.
To reach device function of the present invention, the present invention proposes H-shaped grid-control source and drain resistive formula conduction type adjustable type
Transistor, nuclear structure feature are as follows:
It is high potential by the voltage that setting conduction type regulates and controls grid 2, is worked low in H-shaped gate electrode 8 source and drain both ends
Generated tunneled holes form potential barrier and stop under current potential, to source and drain both ends produced by H-shaped gate electrode 8 works under high potential
Tunelling electrons formed communication channel, and by the mode make transistor work in N-type state；Similarly, by the way that conductive-type is arranged
The voltage that type regulates and controls grid 2 is low potential, to source and drain both ends in the work of H-shaped gate electrode 8 generated tunelling electrons under high potential
It forms potential barrier to stop, to source and drain both ends, in the work of H-shaped gate electrode 8, the generated tunneled holes under low potential form conducting ditch
Road, and make transistor work in p-type state by the mode；The left and right ends of monocrystalline silicon thin film 1 are close to grid electrode insulating layer 7
Part is respectively provided with tunneling structure independent of each other, since device has bilateral symmetry, makees in the control of H-shaped gate electrode 8
Under, near the surface contacted with grid electrode insulating layer 7 tunnelling occurs simultaneously for 1 left and right ends of monocrystalline silicon thin film, in conjunction with conduction
Type regulates and controls grid 2 to the adjustment effect of 1 middle section potential of monocrystalline silicon thin film, and device is made to form forward conduction and reversed blocking,
Voltage by adjusting the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain controls interchangeable 5 He of area a of metal source and drain
The interchangeable area b 6 of metal source and drain is used as source region or drain region, therefore changeable tunnelling current direction, realizes that source and drain of the invention is symmetrical
Interchangeable two-way switch characteristic.H-shaped gate electrode 8 be located at monocrystalline silicon thin film 1 be formed by groove type structure two sides hang down
The middle section of straight upper and front and back upper section intrinsic region a 3 interchangeable to source and drain and the interchangeable intrinsic region b 4 of source and drain
It forms three bread to wrap up in, electric field can be formed in angle part and reinforced, therefore there is outstanding gate electrode control ability, in H-shaped grid electricity
It under the control action of pole 8, makes it possible to band and is easier to bend under identical gate voltage, obtain bigger electric field strength, it is right
Higher forward conduction electric current may be implemented than tunneling field-effect transistor.
The adjustable transistor npn npn preparation method of a kind of H-shaped grid-control source and drain resistive formula conduction type proposed by the invention it is specific
Manufacturing step is as follows:
Step 1: as shown in Figure 4, Figure 5, Figure 6 and Figure 7, a SOI wafer is provided, bottom is the silicon substrate of SOI wafer
12, the upper surface of silicon substrate 12 is substrate insulating layer 11, and the upper surface of substrate insulating layer 11 is monocrystalline silicon thin film 1, by photoetching or
Etching technics performs etching the monocrystalline silicon thin film 1 above SOI wafer, removes front and rear sides and the subregional list of middle part
Polycrystal silicon film 1 forms the monocrystalline silicon thin film with groove type structure feature；
Step 2: as shown in Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 and Figure 13, by aoxidizing or depositing, etching technics, In
Monocrystalline silicon thin film 1 is formed by the front and back outer surface of groove type structure and the inner surface and groove of groove two sides vertical component
The overhead surface of bottom horizontal portion forms grid electrode insulating layer 7；
Step 3: as shown in Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19, deposit insulation is situated between above SOI wafer
Matter is planarized to surface and exposes monocrystalline silicon thin film 1, preliminarily forms insulating medium barrier layer 13；
Step 4: as shown in Figure 20, Figure 21 and Figure 22, by etching technics, to being located at monocrystalline formed in step 3
The SI semi-insulation dielectric barrier 13 of the front and rear surfaces of the groove structure bottom horizontal portion of silicon thin film 1 is performed etching to exposing grid
Electrode dielectric layer 7 is further formed insulating medium barrier layer 13；
Step 5: as shown in Figure 23, Figure 24 and Figure 25, by depositing technics, metal or polycrystalline are deposited above SOI wafer
Silicon, planarization surface preliminarily form conduction type regulation grid 2 to monocrystalline silicon thin film 1 is exposed；
Step 6: it as shown in Figure 26, Figure 27, Figure 28 and Figure 29, first passes through etching technics and etches away 1 shape of monocrystalline silicon thin film
At groove structure bottom horizontal portion top insulating medium barrier layer 13 to expose grid electrode insulating layer 7, passing through form sediment
Product technique deposits metal or polysilicon above SOI wafer, and planarization surface is further formed and leads to monocrystalline silicon thin film 1 is exposed
Electric type regulates and controls grid 2；
Step 7: it as shown in Figure 30, Figure 31, Figure 32 and Figure 33, step 6 is etched away by etching technics is formed by and lead
The upper area of electric type regulation grid 2 is further formed conduction type regulation grid 2；
Step 8: as shown in Figure 34, Figure 35, Figure 36 and Figure 37, by depositing technics, insulation is deposited above SOI wafer
Medium, planarization surface are further formed insulating medium barrier layer 13 to monocrystalline silicon thin film 1 is exposed；
Step 9: as shown in Figure 38, Figure 39, Figure 40 and Figure 41, by photoetching or etching technics, to institute's shape in step 8
At SI semi-insulation dielectric barrier 13 carry out partial etching, then deposit metal or polysilicon above SOI wafer, planarize table
Face forms H-shaped gate electrode 8 to monocrystalline silicon thin film 1 is exposed；
Step 10: as shown in Figure 42, Figure 43 and Figure 44, groove knot is formed by monocrystalline silicon thin film 1 by etching technics
The intermediate exterior portion of the two sides vertical component upper surface of structure performs etching, then is deposited above SOI wafer by depositing technics
Metal, planarization surface are interchangeable so as to form the interchangeable area a 5 of metal source and drain and metal source and drain to exposing monocrystalline silicon thin film 1
Area b 6, make the interchangeable area a 5 of metal source and drain and the interchangeable area b 6 of metal source and drain be located at monocrystalline silicon thin film 1 be formed by it is recessed
Intermediate exterior portion above the left and right sides vertical component of slot structure, and can be mutual by the interchangeable intrinsic region a 3 of source and drain and source and drain
It changes 4 three bread of intrinsic region b to wrap up in, makes to contact between interchangeable 5 lateral wall of area a of metal source and drain and the interchangeable intrinsic region a 3 of source and drain
Partially, contact portion, metal source and drain can be mutual between the interchangeable 5 lower surface bottom sidewall of area a of metal source and drain and monocrystalline silicon thin film 1
Change contact portion and the interchangeable 6 lower surface bottom area b of metal source and drain between 6 lateral wall of area b and the interchangeable intrinsic region b 4 of source and drain
Contact portion forms Schottky contacts between side wall and monocrystalline silicon thin film 1, forms the interchangeable area a 5 of metal source and drain and metal source and drain
Interchangeable area b 6；
Step 11:, by depositing technics, deposit insulation is situated between above SOI wafer as shown in Figure 45, Figure 46 and Figure 47
Matter forms the insulating medium barrier layer 13 of rest part；It is interchangeable by etching technics removal metal source and drain behind planarization surface
The insulating medium barrier layer 13 of 6 top area a 5 and the interchangeable area b of metal source and drain is to exposing the interchangeable area a 5 of metal source and drain and gold
Belong to the upper surface of the interchangeable area b 6 of source and drain, then injection metal is complete to through-hole into the through-hole of etching formation by depositing technics
Full packing is finally handled surface planarisation, forms the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain.
Claims (2)
1. a kind of adjustable transistor npn npn of H-shaped grid-control source and drain resistive formula conduction type, the silicon substrate (12) comprising SOI wafer is special
Sign is: being the substrate insulating layer (11) of SOI wafer, the substrate insulating layer of SOI wafer above the silicon substrate (12) of SOI wafer
(11) top is monocrystalline silicon thin film (1), conduction type regulates and controls grid (2), grid electrode insulating layer (7) and insulating medium barrier layer
(13) partial region, monocrystalline silicon thin film (1) have concave geometrical characteristic, are lower than 10 for impurity concentration16cm-3Monocrystalline
Silicon semiconductor material, monocrystalline silicon thin film (1) are formed by groove type structure inner surface and front and back outer surface with gate electrode
Insulating layer (7)；The interchangeable area a(5 of metal source and drain) and the interchangeable area b(6 of metal source and drain) it is metal material, it is respectively formed in monocrystalline
Silicon thin film (1) is formed by the intermediate region of vertical component upper end at left and right sides of groove structure；The interchangeable area a(5 of metal source and drain)
Front and rear surfaces and inner surface and the interchangeable intrinsic region a(3 of source and drain) mutually form Schottky contacts, and by thirdly face surrounds；
The interchangeable area b(6 of metal source and drain) front and rear surfaces and inner surface and the interchangeable intrinsic region b(4 of source and drain) mutually form Schottky
Contact, and by thirdly face surrounds；The interchangeable area a(5 of metal source and drain) lower surface and monocrystalline silicon thin film (1) mutually form Schottky
Contact, the interchangeable area b(6 of metal source and drain) lower surface and monocrystalline silicon thin film (1) mutually form Schottky contacts；Source and drain is interchangeable
Intrinsic region a(3) and the interchangeable intrinsic region b(4 of source and drain) it is that impurity concentration is lower than 1016cm-3Single-crystal semiconductor material；Monocrystalline
Silicon thin film (1), the interchangeable intrinsic region a(3 of source and drain), the interchangeable intrinsic region b(4 of source and drain), the interchangeable area a(5 of metal source and drain) and gold
Belong to the interchangeable area b(6 of source and drain) collectively constitute a groove type structure；Grid electrode insulating layer (7) is located at monocrystalline silicon thin film (1) institute
The upper surface of the groove type structural base horizontal component of formation and front and rear surfaces and monocrystalline silicon thin film (1) are formed by groove type
The inner surface and front and rear surfaces of structure two sides vertical component；H-shaped gate electrode (8) is made of metal material or polycrystalline silicon material,
The inner surface and front and rear surfaces of the upper section of the two sides vertical component of groove type structure are formed by monocrystalline silicon thin film (1)
It forms three bread to wrap up in, overlooks SOI wafer, H-shaped gate electrode (8) is in English capitalization " H " shape, H-shaped grid electricity along source and drain direction
Insulated from each other by grid electrode insulating layer (7) between pole (8) and monocrystalline silicon thin film (1) concave structure, H-shaped gate electrode (8) is only right
The upper section that monocrystalline silicon thin film (1) is formed by the two sides vertical component of groove type structure has field-effect control action, right
Monocrystalline silicon thin film (1) is formed by the lower zone of the two sides vertical component of groove type structure and bottom horizontal portion region does not have
There is obvious field-effect control action；Conduction type regulation grid (2) is made of metal material or polycrystalline silicon material, and it is thin to be located at monocrystalline silicon
Film (1) is formed by upper surface and the front and rear surfaces of groove type structural base horizontal component, is formed by monocrystalline silicon thin film (1)
Groove type structural base horizontal component forms three bread and wraps up in, and exhausted each other by grid electrode insulating layer (7) and monocrystalline silicon thin film (1)
Edge isolation, only being formed by groove type structural base horizontal component to monocrystalline silicon thin film (1) has field effect for conduction type regulation grid (2)
Control action is answered, the upper section for being formed by the two sides vertical component of groove type structure to monocrystalline silicon thin film (1) is not obvious
Field-effect control action；H-shaped gate electrode (8) is located at the portion that monocrystalline silicon thin film (1) is formed by the inside of the groove of groove type structure
With the partial region of insulating medium barrier layer (13), H-shaped gate electrode between the lower surface divided and conduction type regulation grid (2)
(8) it is isolated between conduction type regulation grid (2) by the way that insulating medium barrier layer (13) are insulated from each other；The interchangeable electrode a of source and drain
(9) it is made of metal material, positioned at the top of the interchangeable area a(5 of metal source and drain)；The interchangeable electrode b(10 of source and drain) also by metal
Material constitute, be located at the interchangeable area b(6 of metal source and drain) top, the interchangeable electrode a(9 of source and drain), the interchangeable electrode b of source and drain
(10) insulated from each other by insulating medium barrier layer (13) between H-shaped gate electrode (8) these three electrodes；Conduction type regulates and controls grid
(2) the left and right sides is in symmetrical structure, can be in the interchangeable electrode a(9 of source and drain) and the interchangeable electrode b(10 of source and drain) symmetrically exchange
In the case of realize same output characteristics.
2. a kind of adjustable transistor npn npn preparation method of H-shaped grid-control source and drain resistive formula conduction type, is technically characterized in that its manufacture
Steps are as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate (12) of SOI wafer, and the upper surface of silicon substrate (12) is substrate
The upper surface of insulating layer (11), substrate insulating layer (11) is monocrystalline silicon thin film (1), by photoetching or etching technics, to SOI wafer
The monocrystalline silicon thin film (1) of top performs etching, and removes front and rear sides and the subregional monocrystalline silicon thin film of middle part (1), is formed
Monocrystalline silicon thin film (1) with groove type structure feature；
Step 2: by aoxidizing or depositing, etching technics, before and after monocrystalline silicon thin film (1) is formed by groove type structure outside
The overhead surface of the inner surface and bottom portion of groove horizontal component of side surface and groove two sides vertical component forms grid electrode insulating
Layer (7)；
Step 3: depositing dielectric above SOI wafer, is planarized to surface and exposes monocrystalline silicon thin film (1), preliminarily forms absolutely
Edge dielectric barrier (13)；
Step 4: by etching technics, to being located at monocrystalline silicon thin film (1) groove structure bottom level portion formed in step 3
The SI semi-insulation dielectric barrier (13) for the front and rear surfaces divided is performed etching to grid electrode insulating layer (7) are exposed, and is further formed
Insulating medium barrier layer (13)；
Step 5: by depositing technics, depositing metal or polysilicon above SOI wafer, and planarization surface is to exposing monocrystalline silicon
Film (1) preliminarily forms conduction type regulation grid (2)；
Step 6: it first passes through etching technics and etches away monocrystalline silicon thin film (1) and be formed by the upper of groove structure bottom horizontal portion
The insulating medium barrier layer (13) of side is depositing gold by depositing technics to grid electrode insulating layer (7) are exposed above SOI wafer
Belong to or polysilicon, planarization surface are further formed conduction type regulation grid (2) to monocrystalline silicon thin film (1) is exposed；
Step 7: the upper area that step 6 is formed by conduction type regulation grid (2) is etched away by etching technics, further
Form conduction type regulation grid (2)；
Step 8: by depositing technics, depositing dielectric above SOI wafer, and planarization surface is to exposing monocrystalline silicon thin film
(1), insulating medium barrier layer (13) are further formed；
Step 9: by photoetching or etching technics, the SI semi-insulation dielectric barrier (13) formed in step 8 is carried out
Partial etching, then metal or polysilicon are deposited above SOI wafer, planarization surface forms H to exposing monocrystalline silicon thin film (1)
Shape gate electrode (8)；
Step 10: the two sides vertical component upper surface of groove structure is formed by monocrystalline silicon thin film (1) by etching technics
Intermediate exterior portion performs etching, then deposits metal above SOI wafer by depositing technics, and planarization surface is to exposing monocrystalline
Silicon thin film (1), so as to form the interchangeable area a(5 of metal source and drain) and the interchangeable area b(6 of metal source and drain), keep metal source and drain interchangeable
Area a(5) and the interchangeable area b(6 of metal source and drain) be located at monocrystalline silicon thin film (1) be formed by groove structure the left and right sides hang down
The intermediate exterior portion of straight upper, and by the interchangeable intrinsic region a(3 of source and drain) and the interchangeable intrinsic region b(4 of source and drain) three bread
Wrap up in, make the interchangeable area a(5 of metal source and drain) lateral wall and the interchangeable intrinsic region b(3 of source and drain) between contact portion, metal source and drain can
Exchange area a(5) contact portion, the interchangeable area b(6 of metal source and drain between lower surface bottom sidewall and monocrystalline silicon thin film (1)) outside
Wall and the interchangeable intrinsic region b(4 of source and drain) between contact portion and the interchangeable area b(6 of metal source and drain) lower surface bottom sidewall and list
Between polycrystal silicon film (1) contact portion formed Schottky contacts, formed the interchangeable area a(5 of metal source and drain) and metal source and drain can be mutual
Change area b(6)；
Step 11: by depositing technics, depositing dielectric above SOI wafer, forms the dielectric resistance of rest part
Barrier (13)；The interchangeable area a(5 of metal source and drain is removed by etching technics behind planarization surface) and the interchangeable area b of metal source and drain
(6) insulating medium barrier layer (13) above is to the exposing interchangeable area a's of metal source and drain) and the interchangeable area b(6 of metal source and drain)
Upper surface, then by depositing technics, into the through-hole of etching formation, injection metal to through-hole is completely filled, and finally puts down surface
Smoothization processing, forms the interchangeable electrode a(9 of source and drain) and the interchangeable electrode b(10 of source and drain).
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|---|---|---|---|
| CN201711050861.0A CN107819028B (en) | 2017-10-31 | 2017-10-31 | H-shaped grid-control source and drain resistive formula conduction type is adjustable transistor npn npn and its manufacturing method |
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| CN107819028B true CN107819028B (en) | 2019-11-22 |
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| CN1851903A (en) * | 2005-04-22 | 2006-10-25 | 韩国科学技术院 | Multi-bit non-volatile memory device having a dual-gate and method of manufacturing the same, and method of multi-bit cell operation |
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| 具有辅助栅的新型低泄露U沟道无结场效应晶体管;杨光锐等;《科技创新导报》;20170610(第16期);第46-50页 * |
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