CN107799606B - The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method - Google Patents
The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method Download PDFInfo
- Publication number
- CN107799606B CN107799606B CN201711046294.1A CN201711046294A CN107799606B CN 107799606 B CN107799606 B CN 107799606B CN 201711046294 A CN201711046294 A CN 201711046294A CN 107799606 B CN107799606 B CN 107799606B
- Authority
- CN
- China
- Prior art keywords
- drain
- source
- interchangeable
- thin film
- monocrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 61
- 230000005669 field effect Effects 0.000 claims abstract description 21
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 115
- 239000010409 thin film Substances 0.000 claims description 112
- 239000002184 metal Substances 0.000 claims description 104
- 229910052751 metal Inorganic materials 0.000 claims description 104
- 239000000758 substrate Substances 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000009471 action Effects 0.000 claims description 16
- 239000007769 metal material Substances 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 9
- 235000008429 bread Nutrition 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 230000005641 tunneling Effects 0.000 abstract description 21
- 238000005516 engineering process Methods 0.000 abstract description 15
- 230000008901 benefit Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 10
- 230000005611 electricity Effects 0.000 description 8
- 238000004891 communication Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 230000035508 accumulation Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000002146 bilateral effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Abstract
The present invention relates to a kind of discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method, the transistor has the function of that achievable P-type conduction type and N-type conduction type can free switching and two-way switch functions.Have the advantages that low speed paper tape reader static power disspation, low reverse leakage current, stronger grid control ability and low subthreshold swing.With the discrete control structure feature of double square grid.In contrast to common MOSFETs type device, more excellent Sub-Threshold Characteristic and switching characteristic are realized using Schottky barrier tunneling effect, reduces the quiescent dissipation of transistor；In contrast to common tunneling field-effect transistor, the present invention has the symmetrically interchangeable two-way switch characteristic of source and drain not available for common tunneling field-effect transistor, realizing P-type conduction type that various existing transistor technologies cannot achieve and N-type conduction type can free switching function, therefore it provides more for IC design unit extensively with various logic function, is suitble to promote and apply.
Description
Technical field
The present invention relates to super large-scale integration manufacturing fields, and in particular to one kind is suitable for low power consumption integrated circuit system
The discrete double square grid-control source and drain resistive transistor of double conduction types with low current leakage and its manufacturing method made.
Background technique
Commonly wear utilized when field effect transistor is used as switching-type device be carrier tunneling mechanism, can make general
The subthreshold swing of logical tunneling field-effect transistor is better than the 60mV/dec limit of MOSFETs type device.However, being based on silicon substrate
The tunneling field-effect transistor of material, since forbidden bandwidth limits, tunnelling probability is limited, compares MOSFETs type device, it is difficult to produce
The conducting electric current of raw same order, more seriously, the miscellaneous of different conduction-types is respectively adopted in source electrode and drain electrode
Matter is doped, and being formed by unsymmetric structure feature causes it source electrode and drain electrode can not real tunnel be existing exchanges mutually, because
This can not functionally replace the MOSFETs type device with symmetrical structure feature completely.It is with N-type tunneling field-effect transistor
Example, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunneling field-effect crystal at this time
Pipe, always belongs to forward bias condition since source and drain is formed by PN junction, then gate electrode can not well control conducting electric current at this time
Size so that the failure of entire tunneling field-effect transistor.
Schottky barrier field effect transistor, using Schottky barrier tunnelling as conducting mechanism, due to tunneling barrier height
Degree lower than tunnel field-effect transistor forbidden bandwidth, it can be achieved that bigger tunnelling probability, and using metal as incidence end, In
Electron impact amounts more more than semiconductor conduction band or valence band can be achieved under same area size, and then obtain bigger tunnel-effect
Current density, therefore conducting current density more higher than tunneling field-effect transistor can be obtained.However common Schottky gesture
Building the gate electrode switching characteristic that field effect transistor is realization device, (gate electrode forward conduction reversely ends or reverse-conducting is positive
Cut-off), source region to device or drain region carry out the impurity doping of specific conductivity type, this to be difficult in technique in source electricity
Between pole and source region, good Schottky contacts are realized between drain electrode and drain region, and the doping to source region and drain region is so that grid
Electrode reduces the control ability in drain region and source region, and the switch performance of device is caused to decline.If not to the semiconductor regions of device
Doping, though the Schottky barrier between source electrode and source region, drain electrode and drain region is then easily achieved in technique, however this can make
It obtains device and generates different types of carrier conducting in forward and reverse, i.e., can make under gate electrode forward bias and reverse biased
It is in the conductive state to obtain device, so that grid loses the control action as devices switch device.
In addition to this, it is based on existing transistor technology, once the structure of transistor is established, conduction type is according to doping
The difference of impurity conduction type, conduction type are also established therewith, and manufactured transistor is only P-type transistor or N-type
Transistor is one such, and conduction type not can be switched at work.That is, can not pass through in the transistor course of work
Certain control method changes its conduction type.
Summary of the invention
Goal of the invention
In contrast to current MOSFETs technology, tunneling transistor technology and Schotthy barrier transistor technology, work as to make up
Various above-mentioned disadvantages of preceding MOSFETs, tunneling transistor and Schotthy barrier transistor technology, and realize mutual supplement with each other's advantages, and
Enabling transistor its conduction type of free switching in the course of work is N type or P type, and the present invention proposes that one kind has
The working characteristics of low subthreshold swing, high forward conduction electric current, and have source electrode, drain electrode be interchangeable, conduction type can be mutual
Change the discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method of function.Its core purpose is to make device
While part is functionally fully compatible with MOSFETs technology, there is low subthreshold swing, high conducting electric current, low current leakage
The working characteristics such as the forward and reverse electric current ratio of height, while transistor being made to have conduction type not available for the technologies such as MOSFETs can
Switch new logic function, which can increase the logic function of integrated circuit, expand the design method of integrated circuit.
Summary of the invention
Goal of the invention
In contrast to current MOSFETs technology, tunneling transistor technology and Schotthy barrier transistor technology, work as to make up
Various above-mentioned disadvantages of preceding MOSFETs, tunneling transistor and Schotthy barrier transistor technology, and realize mutual supplement with each other's advantages, and
Enabling transistor its conduction type of free switching in the course of work is N type or P type, and the present invention proposes that one kind has
The working characteristics of low subthreshold swing, high forward conduction electric current, and have source electrode, drain electrode be interchangeable, conduction type can be mutual
Change the discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method of function.Its core purpose is to make device
While part is functionally fully compatible with MOSFETs technology, there is low subthreshold swing, high conducting electric current, low current leakage
The working characteristics such as the forward and reverse electric current ratio of height, while transistor being made to have conduction type not available for the technologies such as MOSFETs can
Switch new logic function, which can increase the logic function of integrated circuit, expand the design method of integrated circuit.
Technical solution
The present invention is achieved through the following technical solutions:
A kind of discrete double square grid-control source and drain resistive transistor of double conduction types, the silicon substrate comprising SOI wafer, feature
It is: is the substrate insulating layer of SOI wafer above the silicon substrate of SOI wafer, the top of the substrate insulating layer of SOI wafer is monocrystalline
The partial region of silicon thin film, rectangular conductive type selection grid and insulating medium barrier layer；Wherein, monocrystalline silicon thin film is impurity concentration
Lower than 1016cm-3Single-crystal semiconductor material, have U-shaped groove structure feature；Monocrystalline silicon thin film is formed by U-shaped groove knot
Be grid electrode insulating layer on the outside of the left and right sides vertical component of structure, U-shaped groove middle section by insulating medium barrier layer part
Area filling；Grid electrode insulating layer is insulating material, is formed by inside U-shaped groove to monocrystalline silicon thin film and monocrystalline silicon thin film
The four sides outer surface all around in the cube shaped region that the partial region of the insulating medium barrier layer of filling is collectively constituted
It forms four sides to surround, overlooks wafer, grid electrode insulating layer feature in rectangular configuration；Rectangular conductive type selection grid is by metal material
Or polycrystalline silicon material is constituted, and the surrounding of U-shaped groove structure lower horizontal part is formed by positioned at monocrystalline silicon thin film, to monocrystalline silicon
Film is formed by U-shaped groove structure lower horizontal part formation four sides and surrounds, and thin by grid electrode insulating layer and monocrystalline silicon
Wafer, rectangular conductive type selection grid feature in rectangular configuration, rectangular conductive type selection grid pair are overlooked in film isolation insulated from each other
Monocrystalline silicon thin film, which is formed by U-shaped groove bottom horizontal portion, control action, and is formed by U-shaped groove to monocrystalline silicon thin film
Structure two sides vertical component does not have obvious control action；The interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain are located at
Monocrystalline silicon thin film is formed by the intermediate inside region of vertical component upper end at left and right sides of U-shaped groove structure；Metal source and drain can be mutual
Changing area a is metal material, and lower surface and side are formed by groove knot with monocrystalline silicon thin film and composition monocrystalline silicon thin film respectively
Schottky contacts are formed between the interchangeable intrinsic region a of the source and drain of the lateral area of structure left vertical part upper end；Metal source and drain can
Exchanging area b is also metal material, and lower surface and side are formed by with monocrystalline silicon thin film and composition monocrystalline silicon thin film recessed respectively
Schottky contacts are formed between the interchangeable intrinsic region b of the source and drain of the lateral area of slot structure Right vertical part upper end；Source and drain can
The exchange intrinsic region a and interchangeable intrinsic region b of source and drain is located at monocrystalline silicon thin film and is formed by vertical component at left and right sides of groove structure
Upper end lateral area, area a interchangeable to the metal source and drain and interchangeable area b of metal source and drain forms three bread and wraps up in respectively；Rectangular conductive
The top of type selection grid is the partial region of insulating medium barrier layer, and by insulating medium barrier layer and rectangular gate electrode that
This is dielectrically separated from；Rectangular gate electrode is made of metal material or polycrystalline silicon material, above the outer surface of grid electrode insulating layer
Part contacts with each other, and forms four sides to the upper section of grid electrode insulating layer and surround, and overlooks viewing and rectangular configuration feature is presented,
The upper section of the two sides vertical component of U-shaped groove structure is formed by monocrystalline silicon thin film, i.e., intrinsic region a interchangeable to source and drain
There is apparent field-effect control action with the interchangeable intrinsic region b of source and drain；The interchangeable electrode a of the source and drain and interchangeable electrode b of source and drain
For metal material composition, it is located at the top of the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain, source and drain is interchangeable
The upper-end contact of electrode a and the interchangeable area a of metal source and drain, the upper termination of the interchangeable electrode b of source and drain and the interchangeable area b of metal source and drain
Touching；The outer surface of the interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain contact with each other with gate insulation dielectric barrier respectively,
The interchangeable electrode a of source and drain, the interchangeable electrode b of source and drain, rectangular gate electrode and rectangular conductive type selection grid are each other by gate insulation
The isolation of dielectric barrier mutually insulated.
A kind of manufacturing method of double discrete double square grid-control source and drain resistive transistors of conduction type, it is characterised in that:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate of SOI wafer, and the upper surface of silicon substrate is substrate insulation
Layer, the upper surface of substrate insulating layer are monocrystalline silicon thin film, part monocrystalline silicon thin film are removed by photoetching, etching technics, in SOI crystalline substance
Monocrystalline silicon thin film is further formed on circle；
Step 2: dielectric is deposited above SOI wafer and planarizes surface to monocrystalline silicon thin film is exposed, is preliminarily formed
Insulating medium barrier layer；
Step 3: by photoetching, etching technics by four circumference all around of the monocrystalline silicon thin film above substrate insulating layer
Point and step 2 be formed by insulating medium barrier layer front and rear sides be etched to expose substrate insulating layer；
Step 4: dielectric is deposited above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film, then passes through light
It carves, the dielectric of monocrystalline silicon thin film and insulating medium barrier layer all around surrounding is carried out partial etching to revealing by etching technics
Substrate insulating layer out forms the grid electrode insulating layer surrounded to monocrystalline silicon thin film four sides；
Step 5: depositing metal or polysilicon above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film, then leads to
Over etching technique etches away the metal or polysilicon for being centered around grid electrode insulating layer upper section all around surrounding, forms rectangle
Conduction type selection grid；
Step 6: dielectric is deposited above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film, then passes through quarter
Etching technique etches away the metal or polysilicon for being centered around grid electrode insulating layer upper section all around surrounding, is further formed
Insulating medium barrier layer；
Step 7: depositing metal or polysilicon above SOI wafer and planarizes surface to monocrystalline silicon thin film is exposed, and is formed
Rectangular gate electrode；
Step 8: monocrystalline silicon thin film is etched away by etching technics on the monocrystalline silicon thin film of two sides and is formed by groove knot
Intermediate inboard portion above the left and right sides vertical component of structure, then metal is deposited in crystal column surface by depositing technics, it is flat
Change surface to monocrystalline silicon thin film is exposed, so as to form the interchangeable area a of metal source and drain and the interchangeable area b of metal source and drain, makes source metal
Leak the interchangeable area a and interchangeable area b of metal source and drain be located at monocrystalline silicon thin film be formed by groove structure the left and right sides hang down
The intermediate inboard portion of straight upper, and wrapped up in by the interchangeable intrinsic region a of source and drain and interchangeable tri- bread of intrinsic region b of source and drain, make
Contact portion, the interchangeable area a following table of metal source and drain between the interchangeable area a lateral wall of metal source and drain and the interchangeable intrinsic region a of source and drain
The interchangeable area b lateral wall of contact portion, metal source and drain and the interchangeable intrinsic region b of source and drain between face bottom sidewall and monocrystalline silicon thin film
Between between contact portion and metal source and drain interchangeable area b lower surface bottom sidewall and monocrystalline silicon thin film contact portion formed Xiao Te
Base contact；
Step 9: dielectric is deposited in crystal column surface, and the interchangeable area a of metal source and drain and gold are removed by etching technics
Belong to the dielectric above the interchangeable area b of source and drain, is further formed insulating medium barrier layer and source and drain through-hole, then to table on wafer
Face deposits metal or polysilicon, planarizes surface to insulating medium barrier layer is exposed, forms the interchangeable electrode a of source and drain in through-holes
With the interchangeable electrode b of source and drain.
Advantage and effect
The invention has the following advantages and beneficial effects:
1. the realization that N-type conduction and P-type conduction can arbitrarily switch function:
Once existing transistor structure is established, conduction type is also established simultaneously, and device of the present invention is double conductive-types
The discrete double square grid-control source and drain resistive transistor of type and its manufacturing method, by the voltage that rectangular conductive type selection grid 2 is arranged
For high potential, to source and drain both ends, in the work of rectangular gate electrode 8, the generated tunneled holes under low potential form potential barrier blocking, right
In the work of rectangular gate electrode 8, the generated tunelling electrons under high potential form communication channel at source and drain both ends, and pass through the mode
Make transistor work in N-type state；It similarly, is low potential by the voltage that rectangular conductive type selection grid 2 is arranged, to source and drain two
In the work of rectangular gate electrode 8, the generated tunelling electrons under high potential form potential barrier blocking at end, to source and drain both ends in rectangle grid
The work of electrode 8 generated tunneled holes under low potential form communication channel, and make transistor work in p-type by the mode
State；
2. the symmetrical interchangeable two-way switch characteristic of source and drain:
Device of the present invention is double discrete double square grid-control source and drain resistive transistors of conduction type and its manufacturing method, list
The left and right ends of polycrystal silicon film 1 are respectively provided with tunneling structure independent of each other close to the part of grid electrode insulating layer 7, due to device
With bilateral symmetry, under the control action of rectangular gate electrode 8,1 left and right ends of monocrystalline silicon thin film with grid electrode insulating
Nearby simultaneously tunnelling occurs for the surface of 7 contact of layer, in conjunction with rectangular conductive type selection grid to 1 center portion potential of monocrystalline silicon thin film
Adjustment effect, make device formed forward conduction and it is reversed stop, it is interchangeable by adjusting the interchangeable electrode a 9 of source and drain and source and drain
Voltage control metal the source and drain interchangeable area a 5 and the interchangeable area b 6 of metal source and drain of electrode b 10 is used as source region or drain region, therefore
Changeable tunnelling current direction, realizes source and drain of the invention symmetrically interchangeable two-way switch characteristic.
3. low subthreshold swing and high conducting electric current characteristic:
Due to the present invention be by the change of 8 voltage of rectangular gate electrode, to control the power of Schottky barrier tunnel-effect,
And then realize that the resistance value in transistor source region and drain region changes, the source region caused by Schottky barrier tunnel-effect and drain region
Carrier concentration variation will be significantly larger than common MOSFETs device accumulation caused by channel to the sensibility of gate electrode voltage
Layer or inversion-layer electrons concentration change the sensibility to gate electrode voltage, therefore may be implemented than common MOSFETs type device more
Low subthreshold swing.And since the height of Schottky barrier is less than the forbidden bandwidth of semiconductor, and the incoming particle of metal is dense
Degree is higher than the incoming particle concentration of semiconductor energy gap, while using rectangular gate electrode structure, since rectangular gate electrode 8 is three sides
Upward intrinsic region a 3 interchangeable to the source and drain respectively and interchangeable intrinsic region b 4 of source and drain forms three bread and wraps up in, with outstanding grid electricity
Pole control ability makes it possible to band and is easier to bend under identical gate voltage under the control action of rectangular gate electrode 8,
Bigger electric field strength is obtained, higher forward conduction electric current may be implemented in comparison tunneling field-effect transistor.
4. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio:
By taking device works in N-type state as an example, when between the interchangeable area a 5 of metal source and drain, the interchangeable area b 6 of metal source and drain
There are when potential difference, and when rectangular gate electrode 8 is in subthreshold value or reverse-biased, always due to rectangular conductive type selection grid 2
The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain to work in positively biased state, positioned at 1 two sides of monocrystalline silicon thin film
Potential lower than 1 center portion of monocrystalline silicon thin film by 2 control section of rectangular conductive type selection grid potential, by rectangular gate electrode
The control of 8 field-effect passes through Schottky barrier tunnel in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain
The hole that effect is accumulated can not by by rectangular conductive type selection grid 2 control in 1 center portion institute shape of monocrystalline silicon thin film
At potential barrier, that is, due to the control action of rectangular conductive type selection grid 2, be formed by potential barrier in 1 center portion of monocrystalline silicon thin film
It can effectively be blocked between the interchangeable area a 5 of metal source and drain and the interchangeable area b 6 of metal source and drain, in the interchangeable intrinsic region a of source and drain
The formation of hole current between 3 and the interchangeable intrinsic region b 4 of source and drain.Therefore the present invention has low speed paper tape reader static power disspation, low reverse leakage
The advantages of electric current and high forward and reverse electric current ratio.
Detailed description of the invention
Fig. 1 is the top view of the discrete double square grid-control source and drain resistive transistor of the double conduction types of the present invention；
Fig. 2 is top view the cuing open along dotted line A of the discrete double square grid-control source and drain resistive transistor of the double conduction types of the present invention
Face figure；
Fig. 3 is top view the cuing open along dotted line B of the discrete double square grid-control source and drain resistive transistor of the double conduction types of the present invention
Face figure；
Fig. 4 is the top view of step 1；
Fig. 5 is the sectional view along dotted line A of step 1；
Fig. 6 is the sectional view along dotted line B of step 1；
Fig. 7 is the top view of step 2；
Fig. 8 is the sectional view along dotted line A of step 2；
Fig. 9 is the sectional view along dotted line B of step 2；
Figure 10 is the top view of step 3；
Figure 11 is the sectional view along dotted line A of step 3；
Figure 12 is the sectional view along dotted line B of step 3；
Figure 13 is the sectional view along dotted line C of step 3；
Figure 14 is the top view of step 4；
Figure 15 is the sectional view along dotted line A of step 4；
Figure 16 is the sectional view along dotted line B of step 4；
Figure 17 is the sectional view along dotted line C of step 4；
Figure 18 is the top view of step 5；
Figure 19 is the sectional view along dotted line A of step 5；
Figure 20 is the sectional view along dotted line B of step 5；
Figure 21 is the sectional view along dotted line C of step 5；
Figure 22 is the top view of step 6；
Figure 23 is the sectional view along dotted line A of step 6；
Figure 24 is the sectional view along dotted line B of step 6；
Figure 25 is the sectional view along dotted line C of step 6；
Figure 26 is the top view of step 7；
Figure 27 is the sectional view along dotted line A of step 7；
Figure 28 is the sectional view along dotted line B of step 7；
Figure 29 is the sectional view along dotted line C of step 7；
Figure 30 is the top view of step 8；
Figure 31 is the sectional view along dotted line A of step 8；
Figure 32 is the sectional view along dotted line B of step 8；
Figure 33 is the top view of step 9；
Figure 34 is the sectional view along dotted line A of step 9；
Figure 35 is the sectional view along dotted line B of step 9.
Description of symbols:
1, monocrystalline silicon thin film；2, rectangular conductive type selection grid；3, the interchangeable intrinsic region a of source and drain；4, interchangeable of source and drain
Levy area b；5, the interchangeable area a of metal source and drain；6, the interchangeable area b of metal source and drain；7, grid electrode insulating layer；8, rectangular gate electrode；9,
The interchangeable electrode a of source and drain；10, the interchangeable electrode b of source and drain；11, substrate insulating layer；12, silicon substrate；13, insulating medium barrier layer.
Specific embodiment
Following further describes the present invention with reference to the drawings:
As shown in Figure 1, Figure 2 and Figure 3, the discrete double square grid-control source and drain resistive transistor of a kind of double conduction types includes SOI
The silicon substrate 12 of wafer is the substrate insulating layer 11 of SOI wafer, the substrate insulation of SOI wafer above the silicon substrate 12 of SOI wafer
The top of layer 11 is the partial region of monocrystalline silicon thin film 1, rectangular conductive type selection grid 2 and insulating medium barrier layer 13；Wherein,
Monocrystalline silicon thin film 1 is that impurity concentration is lower than 1016cm-3Single-crystal semiconductor material, have U-shaped groove structure feature；Monocrystalline silicon
It is grid electrode insulating layer 7, U-shaped groove middle section on the outside of the left and right sides vertical component of U-shaped groove structure that film 1, which is formed by,
It is filled by the partial region of insulating medium barrier layer 13；Grid electrode insulating layer 7 is insulating material, to monocrystalline silicon thin film 1 and list
Polycrystal silicon film 1 is formed by cube that the partial region for the insulating medium barrier layer 13 filled inside U-shaped groove is collectively constituted
The outer surface of four sides all around in bodily form region forms four sides and surrounds, and overlooks wafer, the spy in rectangular configuration of grid electrode insulating layer 7
Sign；Rectangular conductive type selection grid 2 is made of metal material or polycrystalline silicon material, and it is recessed to be formed by U-shaped positioned at monocrystalline silicon thin film 1
The surrounding of slot structure lower horizontal part is formed by U-shaped groove structure lower horizontal part to monocrystalline silicon thin film 1 and forms four sides
Surround, and by grid electrode insulating layer 7 with monocrystalline silicon thin film 1 is insulated from each other is isolated, vertical view wafer, rectangular conductive type selection grid
2 features in rectangular configuration, rectangular conductive type selection grid 2, which is formed by U-shaped groove bottom horizontal portion to monocrystalline silicon thin film 1, to be had
Control action, and being formed by U-shaped groove structure two sides vertical component to monocrystalline silicon thin film 1 does not have obvious control action；Metal
The interchangeable area a 5 of the source and drain and interchangeable area b 6 of metal source and drain is located at monocrystalline silicon thin film 1 and is formed by a U-shaped groove structure left side
The intermediate inside region of right two sides vertical component upper end；The interchangeable area a 5 of metal source and drain is metal material, lower surface and side
The lateral area of groove structure left vertical part upper end is formed by with monocrystalline silicon thin film 1 and composition monocrystalline silicon thin film 1 respectively
The interchangeable intrinsic region a 3 of source and drain between form Schottky contacts；The interchangeable area b 6 of metal source and drain is also metal material, under
Surface and side are formed by groove structure Right vertical part upper end with monocrystalline silicon thin film 1 and composition monocrystalline silicon thin film 1 respectively
Lateral area the interchangeable intrinsic region b 4 of source and drain between form Schottky contacts；The interchangeable intrinsic region a 3 of source and drain and source and drain can
Exchange intrinsic region b 4 is located at monocrystalline silicon thin film 1 and is formed by vertical component upper end lateral area at left and right sides of groove structure, respectively
Area a 5 interchangeable to the metal source and drain and interchangeable area b 6 of metal source and drain forms three bread and wraps up in；Rectangular conductive type selection grid 2
Top is the partial region of insulating medium barrier layer 13, and insulated from each other by insulating medium barrier layer 13 and rectangular gate electrode 8
Isolation；Rectangular gate electrode 8 is made of metal material or polycrystalline silicon material, the outer surface upper section with grid electrode insulating layer 7
It contacts with each other, and four sides is formed to the upper section of grid electrode insulating layer 7 and is surrounded, overlook viewing and rectangular configuration feature is presented, it is right
Monocrystalline silicon thin film 1 is formed by the upper section of the two sides vertical component of U-shaped groove structure, i.e., intrinsic region a interchangeable to source and drain
The 3 and interchangeable intrinsic region b 4 of source and drain has apparent field-effect control action；When transistor work, the choosing of rectangular conductive type
The operating voltage for selecting grid 2 is arranged on particular value, when the operating voltage of rectangular conductive type selection grid 2 is high potential, transistor
Work is in N-type conduction type mode；When the operating voltage of rectangular conductive type selection grid 2 is low potential, transistor works in p-type
Conduction type mode, by changing the operating voltage of rectangular conductive type selection grid 2 come the conduction type of switching transistor；Pass through
The field-effect of potential added by control rectangle gate electrode 8 controls interchangeable 5 lateral wall of area a of metal source and drain and source and drain interchangeable
It levies contact portion between area a 3 and contact portion forms tunnel-effect caused by Schottky barrier between monocrystalline silicon thin film 1
Size, interchangeable 6 lateral wall of area b of metal source and drain is equally controlled by the field-effect of potential added by control rectangle gate electrode 8
Contact portion and the contact portion formation Schottky barrier institute between monocrystalline silicon thin film 1 between the interchangeable intrinsic region b 4 of source and drain
The size of the tunnel-effect of generation adjusts the current-carrying in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain with this
The size of sub- concentration and resistance value；The interchangeable electrode a 9 of the source and drain and interchangeable electrode b 10 of source and drain is metal material composition, respectively position
In the top of the interchangeable area a 5 of metal source and drain and the interchangeable area b 6 of metal source and drain, the interchangeable electrode a 9 of source and drain and metal source and drain
The upper-end contact of interchangeable area a 5, the upper-end contact of the interchangeable electrode b 10 and interchangeable area b 6 of metal source and drain of source and drain；Source and drain
The outer surface of interchangeable electrode a 9 and the interchangeable electrode b 10 of source and drain contact with each other with gate insulation dielectric barrier 13 respectively,
The interchangeable electrode a 9 of source and drain, the interchangeable electrode b 10 of source and drain, rectangular gate electrode 8 and rectangular conductive type selection grid 2 each other by
The isolation of 13 mutually insulated of gate insulation dielectric barrier.
The present invention provides a kind of discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method, has
N-type conduction and P-type conduction state can arbitrarily switch functional characteristic, and the voltage by the way that rectangular conductive type selection grid 2 is arranged is height
Current potential, to source and drain both ends, in the work of rectangular gate electrode 8, the generated tunneled holes under low potential form potential barrier blocking, to source and drain
In the work of rectangular gate electrode 8, the generated tunelling electrons under high potential form communication channel at both ends, and make crystalline substance by the mode
Body pipe works in N-type state；Similarly, it is low potential by the voltage that rectangular conductive type selection grid 2 is arranged, exists to source and drain both ends
The work of rectangular gate electrode 8 generated tunelling electrons under high potential, which form potential barrier, to be stopped, to source and drain both ends in rectangular gate electrode 8
Work generated tunneled holes under low potential form communication channel, and make transistor work in p-type state by the mode.
The present invention provides a kind of discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method, has
Symmetrical structure, source region and drain region may be implemented that the function of exchange can be exchanged.Since device has a left side on source and drain direction
Right symmetrical structure feature, therefore adjusting can only be passed through as the tunneling field-effect transistor of single-way switch different from common
The voltage of the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain control the interchangeable area a 5 of metal source and drain and metal source and drain
Interchangeable area b 6 is used as source region or drain region, changes the flow direction of Schottky barrier tunnelling current, and device is made to realize bidirectional tunneling
The symmetrical interchangeable characteristic of the source and drain of conducting, even if device realizes two-way switch characteristic.
When applying positive voltage to rectangular conductive type selection grid 2, the interchangeable area a 5 of metal source and drain, metal source and drain are interchangeable
There are when potential difference between area b 6, rectangular gate electrode 8 is such as in reverse-biased, the interchangeable area a 5 of metal source and drain and source and drain can
Xiao for exchanging between intrinsic region a 3, being respectively formed between the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Obvious tunnel-effect occurs for special base potential barrier, so that the interchangeable intrinsic region a trivalent having electronic of source and drain is flowed to by Schottky barrier
The interchangeable area a 5 of metal source and drain, interchangeable 4 valence-band electrons of intrinsic region b of source and drain flow to metal source and drain by Schottky barrier can be mutual
Area b 6 is changed, therefore can generate hole in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain and accumulate, so that source
It leaks interchangeable intrinsic region a 3 and shows p-type feature at this time, although Schottky barrier tunnel-effect makes source and drain interchangeable intrinsic at this time
Area a 3 and the interchangeable intrinsic region b 4 of source and drain resistance value under the action of rectangular gate electrode 8 are remarkably decreased, but due at this time to rectangle
Conduction type selection grid 2 applies positive voltage, is formed by U-shaped by the monocrystalline silicon thin film 1 for being controlled in rectangular conductive type selection grid 2
Groove structure lower horizontal part can be accumulated in intrinsic region a 3 interchangeable to the two sides source and drain and interchangeable intrinsic region b 4 of source and drain
Hole form potential barrier, and be not by rectangle grid electricity since monocrystalline silicon thin film 1 is formed by U-shaped groove structure lower horizontal part
What pole 8 controlled, will not because of 8 voltage of rectangular gate electrode change and change its barrier height, transistor is in rectangle grid electricity
Pole 8 is under reverse-biased and high resistant blocking state is integrally presented；The voltage being applied with rectangular gate electrode 8 from negative voltage gradually
Rise near flat-band voltage, between the interchangeable area a 5 of metal source and drain and the interchangeable intrinsic region a 3 of source and drain, metal source and drain can be mutual
Apparent Schottky will not be occurred by changing the Schottky barrier being respectively formed between area b 6 and the interchangeable intrinsic region b 4 of source and drain
Potential barrier tunnel-effect, therefore both can not form a large amount of hole heaps in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain
Product also can not form a large amount of electronics accumulations, and the interchangeable intrinsic region a 3 of the source and drain of transistor and the interchangeable intrinsic region b 4 of source and drain locate
In high-impedance state, therefore entire transistor does not have obvious electric current and flows through, and device has outstanding turn-off characteristic and subthreshold at this time
It is worth characteristic；The voltage being applied with rectangular gate electrode 8 further rises to forward bias condition, metal source and drain by flat-band voltage
Between interchangeable area a 5 and the interchangeable intrinsic region a 3 of source and drain, the interchangeable area b 6 of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
Between the Schottky barrier that is respectively formed apparent tunnel-effect can occur again, by the forward voltage of rectangular gate electrode 8
Effect, the electrons of the interchangeable area a 5 of metal source and drain pass through the conduction band of tunnel-effect tunnelling to the interchangeable intrinsic region a 3 of source and drain,
The electrons of the interchangeable area b 6 of metal source and drain pass through the conduction band of tunnel-effect tunnelling to the interchangeable intrinsic region b 4 of source and drain, so that source
Leak the interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain and form the accumulation of a large amount of electronics, and the electron concentration accumulated with
The voltage that rectangular gate electrode 8 is applied rises and gradually rises, since rectangular conductive type selection grid 2 is constantly in high electricity at this time
Position, therefore can be upwardly formed good electronic conduction channel in source and drain side, when electron concentration increase to a certain extent when, transistor
Forward conduction state is transitted to by sub-threshold status.Make device work in N type state mode by the above method, similarly, leads to
It crosses and negative voltage is applied to rectangular conductive type selection grid 2, device work can be made in P type state mode.
To reach device function of the present invention, the present invention proposes a kind of discrete double square grid-control source and drain of double conduction types
Resistive transistor and its manufacturing method, nuclear structure feature are as follows:
Voltage by the way that rectangular conductive type selection grid 2 is arranged is high potential, is worked in rectangular gate electrode 8 source and drain both ends
Generated tunneled holes form potential barrier and stop under low potential, are worked under high potential in rectangular gate electrode 8 source and drain both ends
Generated tunelling electrons form communication channel, and make transistor work in N-type state by the mode；Similarly, pass through setting
The voltage of rectangular conductive type selection grid 2 is low potential, to source and drain both ends produced by rectangular gate electrode 8 works under high potential
Tunelling electrons formed potential barrier stop, to source and drain both ends rectangular gate electrode 8 work under low potential generated tunneled holes
Communication channel is formed, and makes transistor work in p-type state by the mode；The left and right ends of monocrystalline silicon thin film 1 are close to grid electricity
The part of pole insulating layer 7 is respectively provided with tunneling structure independent of each other, since device has bilateral symmetry, in rectangle grid electricity
Under the control action of pole 8, near the surface contacted with grid electrode insulating layer 7 tunnel occurs simultaneously for 1 left and right ends of monocrystalline silicon thin film
It wears, U-shaped groove structural base horizontal component potential is formed by monocrystalline silicon thin film 1 in conjunction with rectangular conductive type selection grid 2
Adjustment effect makes device form forward conduction and reversed blocking, passes through and adjusts the interchangeable electrode a 9 of source and drain and the interchangeable electricity of source and drain
Voltage control metal the source and drain interchangeable area a 5 and the interchangeable area b 6 of metal source and drain of pole b 10 is used as source region or drain region, therefore can
Change tunnelling current direction, realizes source and drain of the invention symmetrically interchangeable two-way switch characteristic.The difference position of rectangular gate electrode 8
In the part in 1 or so source of monocrystalline silicon thin film and leakage two sides, intrinsic region a 3 interchangeable to source and drain and source and drain can be mutual in three directions
It changes three bread of formation of intrinsic region b 4 to wrap up in, electric field can be formed in angle part and reinforced, therefore control energy with outstanding gate electrode
Power makes it possible to band and is easier to bend under identical gate voltage under the control action of rectangular gate electrode 8, obtains bigger
Electric field strength, comparison tunneling field-effect transistor higher forward conduction electric current may be implemented.
A kind of unit of double discrete double square grid-control source and drain resistive transistors of conduction type proposed by the invention is in SOI crystalline substance
Specific manufacturing technology steps on circle are as follows:
Step 1: as shown in Figure 4, Figure 5 and Figure 6, providing a SOI wafer, and bottom is the silicon substrate 12 of SOI wafer,
The upper surface of silicon substrate is substrate insulating layer 11, and the upper surface of substrate insulating layer 11 is monocrystalline silicon thin film 1, passes through photoetching, etching work
Skill removes part monocrystalline silicon thin film 1, and monocrystalline silicon thin film 1 is further formed in SOI wafer；
Step 2: as shown in Figure 7, Figure 8 and Figure 9, dielectric is deposited above SOI wafer and planarizes surface to exposing
Monocrystalline silicon thin film 1 preliminarily forms insulating medium barrier layer 13；
Step 3:, will the top of substrate insulating layer 11 by photoetching, etching technics as shown in Figure 10, Figure 11, Figure 12 and Figure 13
Monocrystalline silicon thin film 1 peripheral portion all around and step 2 be formed by the front and rear sides of insulating medium barrier layer 13
It is etched to and exposes substrate insulating layer 11；
Step 4: as shown in Figure 14, Figure 15, Figure 16 and Figure 17, dielectric is deposited above SOI wafer and planarizes table
Face to exposing monocrystalline silicon thin film 1, then by photoetching, etching technics will monocrystalline silicon thin film 1 and the front and back of insulating medium barrier layer 13 it is left
The dielectric of right surrounding carries out partial etching to substrate insulating layer 11 is exposed, and forms the grid surrounded to 1 four sides of monocrystalline silicon thin film
Electrode dielectric layer 7；
Step 5: as shown in Figure 18, Figure 19, Figure 20 and Figure 21, metal or polysilicon and flat are deposited above SOI wafer
Change surface and extremely expose monocrystalline silicon thin film 1, then is etched away by etching technics and be centered around 7 upper section of a grid electrode insulating layer front and back left side
The metal or polysilicon of right surrounding form rectangular conductive type selection grid 2；
Step 6: as shown in Figure 22, Figure 23, Figure 24 and Figure 25, dielectric is deposited above SOI wafer and planarizes table
Monocrystalline silicon thin film 1 is extremely exposed in face, then by etching technics, etches away and be centered around 7 upper section of grid electrode insulating layer all around
The metal or polysilicon of surrounding, are further formed insulating medium barrier layer 13；
Step 7: as shown in Figure 26, Figure 27, Figure 28 and Figure 29, metal or polysilicon and flat are deposited above SOI wafer
Change surface to monocrystalline silicon thin film 1 is exposed, forms rectangular gate electrode 8；
Step 8: it as shown in Figure 30, Figure 31 and Figure 32, is etched away on the monocrystalline silicon thin film 1 of two sides by etching technics
Monocrystalline silicon thin film 1 is formed by the intermediate inboard portion above the left and right sides vertical component of groove structure, then passes through deposit work
Skill deposits metal in crystal column surface, and planarization surface is to monocrystalline silicon thin film 1 is exposed, so as to form the interchangeable area a 5 of metal source and drain
With the interchangeable area b 6 of metal source and drain, the interchangeable area a 5 of metal source and drain and the interchangeable area b 6 of metal source and drain is made to be located at monocrystalline
Silicon thin film 1 is formed by the intermediate inboard portion above the left and right sides vertical component of groove structure, and by source and drain interchangeable
Sign area a 3 and interchangeable 4 three bread of intrinsic region b of source and drain are wrapped up in, and keep interchangeable 5 lateral wall of area a of metal source and drain and source and drain interchangeable
It is contacted between the interchangeable 5 lower surface bottom sidewall of area a of contact portion, metal source and drain and monocrystalline silicon thin film 1 between intrinsic region a 3
Partially, contact portion and metal source and drain can be mutual between interchangeable 6 lateral wall of area b of metal source and drain and the interchangeable intrinsic region b 4 of source and drain
It changes contact portion between 6 lower surface bottom sidewall of area b and monocrystalline silicon thin film 1 and forms Schottky contacts；
Step 9: as shown in Figure 33, Figure 34 and Figure 35, dielectric is deposited in crystal column surface, and remove by etching technics
The dielectric for removing the interchangeable area a 5 of metal source and drain and interchangeable 6 top area b of metal source and drain, is further formed dielectric resistance
Barrier 13 and source and drain through-hole, then metal or polysilicon are deposited to wafer upper surface, planarization surface stops to dielectric is exposed
Layer 13 forms the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain in through-holes.
Claims (2)
1. a kind of discrete double square grid-control source and drain resistive transistor of double conduction types, the silicon substrate (12) comprising SOI wafer is special
Sign is: being the substrate insulating layer (11) of SOI wafer, the substrate insulating layer of SOI wafer above the silicon substrate (12) of SOI wafer
(11) top is the part area of monocrystalline silicon thin film (1), rectangular conductive type selection grid (2) and insulating medium barrier layer (13)
Domain；Wherein, monocrystalline silicon thin film (1) is that impurity concentration is lower than 1016cm-3Single-crystal semiconductor material, have U-shaped groove structure
Feature；It is grid electrode insulating layer (7) on the outside of the left and right sides vertical component of U-shaped groove structure that monocrystalline silicon thin film (1), which is formed by,
It is filled by the partial region of insulating medium barrier layer (13) U-shaped groove middle section；Grid electrode insulating layer (7) is insulator material
Material is formed by the insulating medium barrier layer (13) filled inside U-shaped groove to monocrystalline silicon thin film (1) and monocrystalline silicon thin film (1)
The outer surface of four sides all around in cube shaped region that is collectively constituted of partial region form four sides and surround, overlook brilliant
Circle, grid electrode insulating layer (7) feature in rectangular configuration；Rectangular conductive type selection grid (2) is by metal material or polycrystalline silicon material
It constitutes, is located at the surrounding that monocrystalline silicon thin film (1) is formed by U-shaped groove structure lower horizontal part, to monocrystalline silicon thin film (1) institute
The U-shaped groove structure lower horizontal part of formation forms four sides and surrounds, and passes through grid electrode insulating layer (7) and monocrystalline silicon thin film
(1) wafer, rectangular conductive type selection grid (2) feature in rectangular configuration are overlooked in isolation insulated from each other；The selection of rectangular conductive type
Grid (2), which are formed by U-shaped groove bottom horizontal portion to monocrystalline silicon thin film (1), control action, and to monocrystalline silicon thin film (1) institute
The U-shaped groove structure two sides vertical component of formation does not have obvious control action；The interchangeable area a(5 of metal source and drain) and metal source and drain
Interchangeable area b(6) it is located at monocrystalline silicon thin film (1) and is formed by left and right sides of U-shaped groove structure in vertical component upper end
Between inside region；The interchangeable area a(5 of metal source and drain) be metal material, lower surface and side respectively with monocrystalline silicon thin film (1) and
Constitute the interchangeable intrinsic region of source and drain that monocrystalline silicon thin film (1) is formed by the lateral area of groove structure left vertical part upper end
A(3 Schottky contacts are formed between)；The interchangeable area b(6 of metal source and drain) be also metal material, lower surface and side respectively with
Monocrystalline silicon thin film (1) and composition monocrystalline silicon thin film (1) are formed by the lateral area of groove structure Right vertical part upper end
The interchangeable intrinsic region b(4 of source and drain) between form Schottky contacts；The interchangeable intrinsic region a(3 of source and drain) and the interchangeable intrinsic region of source and drain
B(4) it is located at monocrystalline silicon thin film (1) and is formed by vertical component upper end lateral area at left and right sides of groove structure, respectively to metal
The interchangeable area a(5 of source and drain) and the interchangeable area b(6 of metal source and drain) formed three bread wrap up in；Rectangular conductive type selection grid (2) it is upper
Side is the partial region of insulating medium barrier layer (13), and each other by insulating medium barrier layer (13) and rectangular gate electrode (8)
It is dielectrically separated from；Rectangular gate electrode (8) is made of metal material or polycrystalline silicon material, the outer surface with grid electrode insulating layer (7)
Upper section contacts with each other, and forms four sides to the upper section of grid electrode insulating layer (7) and surround, and overlooks viewing and rectangle knot is presented
Structure feature is formed by the upper section of the two sides vertical component of U-shaped groove structure to monocrystalline silicon thin film (1), i.e., can to source and drain
Exchange intrinsic region a(3) and the interchangeable intrinsic region b(4 of source and drain) there is apparent field-effect control action；The interchangeable electrode a of source and drain
(9) and the interchangeable electrode b(10 of source and drain) be that metal material is constituted, be located at the interchangeable area a(5 of metal source and drain) and metal source and drain
Interchangeable area b(6) top, the interchangeable electrode a(9 of source and drain) with the interchangeable area a(5 of metal source and drain) upper-end contact, source and drain can
Staggered poles b(10) with the interchangeable area b(6 of metal source and drain) upper-end contact；The interchangeable electrode a(9 of source and drain) and source and drain it is interchangeable
Electrode b(10) outer surface contact with each other respectively with gate insulation dielectric barrier (13), the interchangeable electrode a(9 of source and drain), source and drain
Interchangeable electrode b(10), rectangular gate electrode (8) and rectangular conductive type selection grid (2) be each other by gate insulation dielectric barrier
(13) mutually insulated is isolated.
2. a kind of manufacturing method of the discrete double square grid-control source and drain resistive transistor of double conduction types as described in claim 1,
It is characterized in that:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate (12) of SOI wafer, and the upper surface of silicon substrate is substrate insulation
Layer (11), the upper surface of substrate insulating layer (11) are monocrystalline silicon thin film (1), remove part monocrystalline silicon by photoetching, etching technics
Film (1) is further formed monocrystalline silicon thin film (1) in SOI wafer；
Step 2: dielectric is deposited above SOI wafer and planarizes surface to monocrystalline silicon thin film (1) is exposed, is preliminarily formed
Insulating medium barrier layer (13)；
Step 3: by photoetching, etching technics by the surrounding all around of the monocrystalline silicon thin film (1) above substrate insulating layer (11)
Partially and step 2 be formed by insulating medium barrier layer (13) front and rear sides be etched to expose substrate insulating layer (11)；
Step 4: dielectric is deposited above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film (1), then passes through light
It carves, etching technics is by the dielectric progress part of monocrystalline silicon thin film (1) and insulating medium barrier layer (13) all around surrounding
It is etched to and exposes substrate insulating layer (11), form the grid electrode insulating layer (7) surrounded on four sides to monocrystalline silicon thin film (1)；
Step 5: depositing metal or polysilicon above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film (1), then leads to
Over etching technique etches away the metal or polysilicon for being centered around grid electrode insulating layer (7) upper section all around surrounding, is formed
Rectangular conductive type selection grid (2)；
Step 6: dielectric is deposited above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film (1), then passes through quarter
Etching technique etches away the metal or polysilicon for being centered around grid electrode insulating layer (7) upper section all around surrounding, further shape
At insulating medium barrier layer (13)；
Step 7: depositing metal or polysilicon above SOI wafer and planarizes surface to exposing monocrystalline silicon thin film (1), is formed
Rectangular gate electrode (8)；
Step 8: monocrystalline silicon thin film (1) is etched away by etching technics on the monocrystalline silicon thin film (1) of two sides and is formed by groove
Intermediate inboard portion above the left and right sides vertical component of structure, then metal is deposited in crystal column surface by depositing technics, it puts down
Smoothization surface is to monocrystalline silicon thin film (1) is exposed, so as to form the interchangeable area a(5 of metal source and drain) and the interchangeable area b of metal source and drain
(6), make the interchangeable area a(5 of metal source and drain) and the interchangeable area b(6 of metal source and drain) be located at monocrystalline silicon thin film (1) and be formed by
Intermediate inboard portion above the left and right sides vertical component of groove structure, and by the interchangeable intrinsic region a(3 of source and drain) and source and drain can
Exchanging intrinsic region b(4) three bread wrap up in, make the interchangeable area a(5 of metal source and drain) lateral wall and the interchangeable intrinsic region a(3 of source and drain) between
Contact portion, the interchangeable area a(5 of metal source and drain) contact portion, source metal between lower surface bottom sidewall and monocrystalline silicon thin film (1)
Leak interchangeable area b(6) lateral wall and the interchangeable intrinsic region b(4 of source and drain) between contact portion and the interchangeable area b(6 of metal source and drain)
Contact portion forms Schottky contacts between lower surface bottom sidewall and monocrystalline silicon thin film (1)；
Step 9: dielectric is deposited in crystal column surface, and the interchangeable area a(5 of metal source and drain is removed by etching technics) and gold
Belong to the interchangeable area b(6 of source and drain) above dielectric, be further formed insulating medium barrier layer (13) and source and drain through-hole, then right
Wafer upper surface deposits metal or polysilicon, planarizes surface to insulating medium barrier layer (13) are exposed, forms source in through-holes
Leak interchangeable electrode a(9) and the interchangeable electrode b(10 of source and drain).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711046294.1A CN107799606B (en) | 2017-10-31 | 2017-10-31 | The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711046294.1A CN107799606B (en) | 2017-10-31 | 2017-10-31 | The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107799606A CN107799606A (en) | 2018-03-13 |
| CN107799606B true CN107799606B (en) | 2019-11-22 |
Family
ID=61547779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711046294.1A Active CN107799606B (en) | 2017-10-31 | 2017-10-31 | The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107799606B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113793871B (en) * | 2021-08-31 | 2023-09-12 | 沈阳工业大学 | Transistor for low on-resistance reconfigurable computing chip and manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005002739B4 (en) * | 2005-01-20 | 2010-11-25 | Infineon Technologies Ag | Method for producing a field effect transistor, tunnel field effect transistor and integrated circuit arrangement with at least one field effect transistor |
| CN104393033B (en) * | 2014-12-08 | 2018-05-22 | 沈阳工业大学 | Gate insulation tunnelling groove base bipolar transistor with breakdown protection function |
| CN104538443B (en) * | 2014-12-08 | 2018-02-16 | 沈阳工业大学 | The high-performance SOI nodeless mesh body pipes of non-single insulated substrate thickness degree |
-
2017
- 2017-10-31 CN CN201711046294.1A patent/CN107799606B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107799606A (en) | 2018-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107819027B (en) | A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacturing method | |
| CN110164958B (en) | Asymmetric reconfigurable field effect transistor | |
| CN110459602A (en) | Device and its manufacturing method with longitudinal floating field plate | |
| KR101919148B1 (en) | Field effect thin film transistor with reconfigurable characteristics, and manufacturing method thereof | |
| CN104409487A (en) | Bidirectional breakdown protection double-gate insulation tunneling enhancement transistor on bulk silicon and manufacture method of transistor | |
| CN107785436B (en) | Source and drain resistive formula rectangular grid control U-shaped channel bidirectional transistor and its manufacturing method | |
| CN107799607B (en) | Conduction type is adjustable, and source and drain resistive formula bilateral folds gate transistor and its manufacturing method | |
| CN214848639U (en) | Cell structure of semiconductor device and semiconductor device | |
| CN107833925B (en) | A kind of source and drain resistive formula two-way switch field effect transistor and its manufacturing method | |
| CN107799606B (en) | The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method | |
| CN107706235B (en) | A kind of rectangular grid control U-shaped channel two-way switch tunneling transistor and its manufacturing method | |
| CN107808905B (en) | Bilateral folds the double tunnelling type bidirectionally conductive transistors of grid-control source and drain and its manufacturing method | |
| CN107731913B (en) | The double tunneling transistors of discrete double square grid-control U-shaped channel source and drain and its manufacturing method | |
| CN107731914B (en) | The grid of falling U auxiliary control bilateral grid master control bidirectional tunneling transistor and its manufacturing method | |
| CN107819036B (en) | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method | |
| CN110459541A (en) | Planar complementary type tunneling field effect transistor inverter | |
| CN107785437A (en) | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method | |
| CN107681005B (en) | The interchangeable transistor of the optional source and drain of source and drain resistive formula conduction type and its manufacturing method | |
| CN107819028B (en) | H-shaped grid-control source and drain resistive formula conduction type is adjustable transistor npn npn and its manufacturing method | |
| CN104409508A (en) | SOI substrate two-way breakdown protection and double-gate insulated tunneling enhanced transistor and making method thereof | |
| CN104282754B (en) | High integration L-shaped grid-control Schottky barrier tunneling transistor | |
| CN104393033B (en) | Gate insulation tunnelling groove base bipolar transistor with breakdown protection function | |
| CN107799589B (en) | H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and its manufacturing method | |
| CN107863388B (en) | Double-selection conductive type double-bracket grid-control source-drain resistance variable transistor and manufacturing method thereof | |
| CN107768430B (en) | Source and drain symmetrically interchangeable bidirectional tunneling field effect transistor and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201222 Address after: Susong Xinqu Photoelectric Technology Co., Ltd., Jiumiao village, Qianling Township, Susong County, Anqing City, Anhui Province Patentee after: Susong Xinqu Photoelectric Technology Co., Ltd Address before: 110870 No. 111 Shenyang West Road, Shenyang economic and Technological Development Zone, Liaoning Patentee before: SHENYANG University OF TECHNOLOGY |