CN208400855U - A kind of separation grid MOSFET component structure - Google Patents
A kind of separation grid MOSFET component structure Download PDFInfo
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Abstract
The utility model belongs to the manufacturing technology field of semiconductor devices, it is related to a kind of separation grid MOSFET component structure, including active area, it include several device cellular units parallel with one another in active area, device cellular unit includes the first conductivity type substrate and the first conduction type drift region, the second conduction type well region is equipped on the top of the first conduction type drift region, first kind groove is equipped in the second conductive type of trap section and positioned at the second class groove of first kind groove two sides, and groove extends to inside it from the first conduction type drift region surface, filled with separation gate polysilicon in first kind groove, thick oxide layer and oxidation masking layer, grid polycrystalline silicon and gate oxide are filled in the second class groove, the inside of grid polycrystalline silicon and thick oxide layer are adjacent；The manufacture craft of the device is simple, and photoetching number is few, and cost is relatively low, while separated bar part groove width and depth are easy to control, and device pressure resistance performance is more preferable, has lower conducting resistance.
Description
Technical field
The utility model relates to a kind of power semiconductor and manufacturing method, especially a kind of separation grid MOSFET component
Structure belongs to the manufacturing technology field of semiconductor devices.
Background technique
Groove power MOSFET is a kind of efficient switch device that new development is got up after plane VDMOS, since it has
The advantages that input impedance is high, and driving current is small, and switching speed is fast, and hot properties is good is widely used in field of power electronics.It is high
Breakdown voltage, high current, low on-resistance are the most key index of power MOSFET, breakdown voltage and the direct phase of conducting resistance
It closes, in MOSFET design process, high-breakdown-voltage and low on-resistance cannot be obtained simultaneously, need mutually to put down therebetween
Weighing apparatus.
As shown in Figure 1, in order to obtain higher breakdown voltage and lower conducting resistance, a kind of novel separation as far as possible
Grid structure MOSFET element is come into being, and is compared conventional trench MOSFET structure, is mainly characterized by increasing one and source electrode
Then the deep trench separate gate of short circuit plays the effect for improving device pressure resistance using the transverse electric field between separate gate.
But this separate gate structures MOSFET element has the disadvantage that
1) 7 photoetching are generallyd use, trench lithography version, separate gate polycrystalline reticle, active area reticle, source are respectively as follows:
Pole injection reticle, grid polycrystalline silicon reticle, hole reticle, metal layer lithography version, cost of manufacture are higher；
2) gate polycrystalline silicon trench is formed by corroding thick oxide layer, and thick oxide layer needs the oxidation of a long period
Layer growth course, the process time is long, at high cost.And the too thick separation gate polysilicon that will affect of oxide layer is to the anti-of N-type epitaxy layer
Type effect, to influence the foundation of transverse electric field, the resistance to voltage levels of device also will receive influence.
3) as can be seen that the both sides of grid gate oxide, are on one side monocrystalline silicon, are on one side polysilicon, work as system from structure
When making low Vth device, the gate oxide used is very thin, it is easy to because oxidation layer defects cause grid and source electrode to leak electricity.
Summary of the invention
The purpose of the utility model is to overcome the deficiencies in the prior art, propose a kind of separation grid MOSFET component
The manufacture craft of structure and its manufacturing method, the device is simple, and photoetching number is few, and separated bar part groove width and depth are easy
Control, device pressure resistance performance is more preferable, and has lower conducting resistance.
To realize the above technical purpose, the technical solution of the utility model is: a kind of separation grid MOSFET component structure, packet
It includes active area, includes several device cellular units parallel with one another in the active area, the device cellular unit includes the
One conductivity type substrate and the first conduction type drift region in the first conductivity type substrate, in first conduction type
The top of drift region is equipped with the second conduction type well region, which is characterized in that is equipped with first in second conductive type of trap section
Type groove and the second class groove positioned at first kind groove two sides, and the first kind groove and the second class groove
It is extended to inside it from the first conduction type drift region surface, separate gate polycrystalline is filled in the first kind groove
The thick oxide layer and lid of silicon, package the separation gate polysilicon are enclosed in the oxidation masking layer on the separation gate polysilicon, in institute
It states and is filled with grid polycrystalline silicon and the gate oxide on the outside of grid polycrystalline silicon in the second class groove, the grid polycrystalline silicon
Inside and thick oxide layer are adjacent.
Further, insulating medium layer, the dielectric are covered on the first kind groove and the second class groove
It is covered with source metal on layer, the top in the second conduction type well region is equipped with the first conductive type source area, described
Source metal is filled in the contact hole between the first conductive type source area, point in the source metal and first kind groove
It is electrically connected from gate polysilicon.
Further, first conductive type source area and the second class groove are adjacent, and the source metal passes through insulation
Dielectric layer is isolated with the grid polycrystalline silicon in the second class groove.
Further, the depth of the first kind groove is greater than the second class trench depth, the depth of the second class groove
Degree is not less than the junction depth of the second conduction type well region.
Further, drain metal, the drain metal and the are set in the lower surface of first conductivity type substrate
One conductivity type substrate Ohmic contact.
In order to further realize the above technical purpose, the utility model also proposes a kind of separation grid MOSFET component structure
Manufacturing method, characterized in that include the following steps:
Step 1 chooses the first conductivity type substrate, one conduction type of growth regulation in first conductivity type substrate
Drift region, the upper surface of first conduction type drift region are the first interarea, the lower surface of first conductivity type substrate
For the second interarea；
Step 2 deposits one layer of silicon nitride on the first interarea, deposits layer of oxide layer on the silicon nitride；
Step 3 performs etching silicon nitride, oxide layer and the first conduction type drift region under the blocking of photoresist,
First kind groove is formed, and removes photoresist；
Step 4 continued growth oxide layer in first kind groove, forms thick oxide layer in first kind groove；
Step 5 depositing polysilicon in the groove that oxidation layer surface and thick oxide layer are formed, and polysilicon is carved
Erosion forms separation gate polysilicon in the first kind groove；
Step 6 obtains oxidation masking layer by thermal oxide growth at the top of the separation gate polysilicon；
Step 7 carries out wet etching under the blocking of oxide layer, to silicon nitride, only retains oxide layer section below nitrogen
Then SiClx removes oxide layer；
Step 8 only carves the first conduction type drift region under the blocking of the silicon nitride and oxidation masking layer
Erosion forms Second Type groove, and removes silicon nitride；
Step 9 forms gate oxide in the Second Type groove by thermal oxide；
Step 10 depositing polysilicon in Second Type groove and on the first interarea, and polysilicon is performed etching,
Grid polycrystalline silicon is obtained in the Second Type groove；
Step 11 injects the first conductive type ion on the first interarea, and anneals, in adjacent Second Type groove
Between form the first conductive type source area；
Step 12 injects the second conductive type ion on the first interarea, and pushes away trap, in adjacent Second Type groove
Between form the second conduction type well region；
Step 13 deposits one layer of dielectric layer on first interarea, obtains insulating medium layer；
Step 14 performs etching the insulating medium layer, obtains contact hole under the blocking of photoresist, wherein wearing
The contact hole of logical N-type source region extends in P type trap zone,
It can also include grid polycrystalline silicon contact hole and separate gate polysilicon contact hole；
Step 15 deposited metal on the insulating medium layer and in contact hole, performs etching metal layer, obtains
To source metal, gate metal, source metal and 9 Ohmic contact of N-type source region, and pass through grid polycrystalline silicon contact hole and grid
Polysilicon electrical connection, the gate metal are electrically connected by separate gate polysilicon contact hole with gate polysilicon is separated；
Six, of step 10 deposits metal on the second interarea, obtains drain metal.
Further, for N-type MOSFET element structure, first conduction type is that N-type is conductive, and described second is conductive
Type is P-type conduction；For p-type MOSFET element structure, first conduction type is P-type conduction, second conductive-type
Type is that N-type is conductive.
Further, the contact hole in the step 14 further includes grid polycrystalline silicon contact hole and separation gate polysilicon
Contact hole；
Metal layer is performed etching in step 15, also obtains gate metal, the gate metal passes through grid polycrystalline silicon
Contact hole is electrically connected with grid polycrystalline silicon, and the source metal is electrically connected by separate gate polysilicon contact hole with gate polysilicon is separated
It connects.
Compared with traditional separate gate MOSFET semiconductor devices, the utility model is had the advantage that
1) with it is existing separate grid MOSFET component structure compared with, gate groove and gate trench are separated in Fig. 1 and is produced on
In the same big groove, therefore the width of gate trench is limited, the first kind groove in the utility model structure (separates
Gate groove) and Second Type groove (i.e. gate trench) be separately fabricated separately, gate trench width compared to existing structure more
Width, such grid polycrystalline silicon and separation gate polysilicon can directly do fairlead in the trench, and the width of gate trench can
Any setting；
2) 4 photoetching are used only in the utility model process, can be omitted 3 photoetching compared to prior art method
Journey, respectively trench lithography version, active area reticle, contact hole reticle, metal layer lithography version, and not complicated technique mistake
Journey, structure and technique are all fairly simple, low manufacture cost；
3) the utility model gate trench is the appurtenant grooves for separating gate groove two sides, is covered by lateral encroaching silicon nitride
Layer formation is covered, groove width and depth are easily controllable, and production is simple；
4) the utility model gate trench is isolated between gate groove with separating by thick oxide layer, when making low Vth device,
Due to the isolation of thick oxide layer, even if gate oxide is very thin, will not occur grid polycrystalline silicon and separation gate polysilicon conducting and
The problem of leading to electric leakage；
5) when device pressure resistance, since the thickness of the thick oxide layer in separation gate groove can be adjusted freely, so that device
The effect of having lateral depletion between adjacent separation gate polysilicon is more preferable, and device pressure resistance performance is more excellent, such the utility model device
In same resistance to pressure, epitaxial wafer (drift region) can select the smaller specification of resistivity, and the conducting resistance of corresponding device can be shown
Writing reduces；That is, the power MOSFET device that the utility model structure fabrication comes out, under same current processing capacity,
Its chip area is smaller.
Detailed description of the invention
Fig. 1 is the schematic cross-sectional view that the prior art separates grid MOSFET component.
Fig. 2 is the schematic cross-sectional view that the utility model separates grid MOSFET component.
Fig. 3 is that the utility model forms the schematic cross-sectional view after N-type substrate and N-type drift region.
Fig. 4 is that the schematic cross-sectional view after silicon nitride layer and oxide layer is formed in the utility model embodiment.
Fig. 5 is that the schematic cross-sectional view after first kind groove is formed in the utility model embodiment.
Fig. 6 is that the schematic cross-sectional view after thick oxide layer is formed in the utility model embodiment.
Fig. 7 is the schematic cross-sectional view formed after separation gate polysilicon in the utility model embodiment.
Fig. 8 is that the schematic cross-sectional view after oxidation masking layer is formed in the utility model embodiment.
Fig. 9 is the schematic cross-sectional view in the utility model embodiment after silicon nitride etch.
Figure 10 is to go the schematic cross-sectional view after removing oxide layer in the utility model embodiment.
Figure 11 is that the schematic cross-sectional view after Second Type groove is etched in the utility model embodiment.
Figure 12 is that the schematic cross-sectional view after silicon nitride layer is removed in the utility model embodiment.
Figure 13 is that the schematic cross-sectional view after gate oxide is formed in the utility model embodiment.
Figure 14 is that the schematic cross-sectional view after grid polycrystalline silicon is formed in the utility model embodiment.
Figure 15 is that the schematic cross-sectional view after N-type source region is formed in the utility model embodiment.
Figure 16 is that the schematic cross-sectional view after P type trap zone is formed in the utility model embodiment.
Figure 17 is that the schematic cross-sectional view after insulating medium layer and contact hole is formed in the utility model embodiment.
Figure 18 is that the schematic cross-sectional view after source metal and gate metal is formed in the utility model embodiment.
Description of symbols: 1-N type substrate, 2-N type drift region, 3- first kind groove, the second class of 4- groove, 5- separation
Gate polysilicon, 6- thick oxide layer, 7- oxidation masking layer, 8- P type trap zone, 9- N-type source region, 10- grid polycrystalline silicon, 11- grid
Oxide layer, 12- insulating medium layer, 13- source metal, 14- drain metal, 01- silicon nitride, 02- oxide layer, 001- first are main
Face, the second interarea of 002-.
Specific embodiment
Below with reference to specific drawings and examples, the utility model is described in further detail.
As shown in Fig. 2, reducing cost in order to effectively improve the high pressure resistant property of device, adaptation range is improved, this is practical
It is novel to propose a kind of semiconductor structure and manufacturing method suitable for deep groove device, with partly leading for N-type deep trench MOSFET
For separate gate power MOSFET in body device, first conduction type is that N-type is conductive, and second conduction type is P
Type is conductive, a kind of separation grid MOSFET component structure, including active area, includes several devices parallel with one another in the active area
Part cellular unit, the device cellular unit includes N-type substrate 1 and the N-type drift region 2 in N-type substrate 1, in the N-type
The top of drift region 2 is equipped with P type trap zone 8, and first kind groove 3 is equipped between the P type trap zone 8 and is located at the first kind
Second class groove 4 of 3 two sides of groove, and the first kind groove 3 and the second class groove 4 extend from 2 surface of N-type drift region
Thick oxygen inside to it, in the first kind groove 3 filled with separation gate polysilicon 5, the package separation gate polysilicon 5
Change layer 6 and lid is enclosed in the oxidation masking layer 7 separated on gate polysilicon 5, it is more filled with grid in the second class groove 4
Crystal silicon 10 and the gate oxide 11 on the outside of grid polycrystalline silicon 10, the inside of the grid polycrystalline silicon 10 and thick oxide layer 6 are adjacent
It connects；
Insulating medium layer 12, the insulating medium layer 12 are covered on the first kind groove 3 and the second class groove 4
On be covered with source metal 13, the top in the P type trap zone 8 is equipped with N-type source region 9, and the source metal 13 is filled in N
In contact hole between type source area 9, and with 9 Ohmic contact of N-type source region, the source metal 13 in first kind groove 3
Separation gate polysilicon 5 be electrically connected；In the lower surface of the N-type substrate 1, drain metal 14, the drain metal 14 and N are set
1 Ohmic contact of type substrate；
The N-type source region 9 and the second class groove 4 are adjacent, and the source metal 13 passes through insulating medium layer 12 and second
Grid polycrystalline silicon 10 in class groove 4 is isolated.
The depth of first kind groove 3 is greater than 4 depth of the second class groove, the second class ditch in the utility model embodiment
The depth of slot 4 is not less than the junction depth of P type trap zone 8.
In order to further realize the above technical purpose, the utility model also proposes separate gate MOSFET device in embodiment as above
The manufacturing method of part structure, includes the following steps:
As shown in figure 3, step 1 chooses N-type substrate 1, N-type drift region 2, the N-type are grown in the N-type substrate 1
The upper surface of drift region 2 is the first interarea 001, and the lower surface of the N-type substrate 1 is the second interarea 002；
As shown in figure 4, step 2 deposits one layer of silicon nitride 01 on the first interarea 001, form sediment on the silicon nitride 01
Product layer of oxide layer 02；
As shown in figure 5, step 3 goes out figure to photoresist developing by photoetching, under the blocking for having figure photoresist,
Silicon nitride 01, oxide layer 02 and N-type drift region 2 are performed etching, form first kind groove 3, and remove photoresist；
As shown in fig. 6, step 4 continued growth oxide layer in first kind groove 3, the shape in first kind groove 3
At thick oxide layer 6；
As shown in fig. 7, step 5 depositing polysilicon in the groove that 02 surface of oxide layer and thick oxide layer 6 are formed, and
Polysilicon is performed etching, forms separation gate polysilicon 5 in the first kind groove 3；
As shown in figure 8, step 6 obtains oxidation masking layer by thermal oxide growth at the top of the separation gate polysilicon 5
7；
Then active area photoetching is carried out, figure is gone out to photoresist developing by photoetching, so that photoresist is sheltered from termination environment, has
Source region exposes；
As shown in Figure 9 and Figure 10, step 7 carries out wet etching to silicon nitride 01, only under the blocking of oxide layer 02
Retain 02 section below silicon nitride 01 of oxide layer, then removes oxide layer 02；
As is illustrated by figs. 11 and 12, step 8 floats N-type under the blocking of remaining silicon nitride 01 and oxidation masking layer 7
It moves area 2 to perform etching, forms Second Type groove 4 in N-type drift region 2, and remove silicon nitride 01；
Then the photoresist of termination environment is blocked in removal；
As shown in figure 13, step 9 forms gate oxide 11 by thermal oxide in the Second Type groove 4；
As shown in figure 14, step 10 depositing polysilicon in Second Type groove 4 and on the first interarea 001, and to more
Crystal silicon performs etching, and obtains grid polycrystalline silicon 10 in the Second Type groove 4；
As shown in figure 15, step 11 injects N-type ion on the first interarea 001, and anneals, in adjacent second class
N-type source region 9 is formed between type groove 4；
Then the silicon nitride 01 on termination environment surface is shelled entirely, exposes termination environment；
As shown in figure 16, for step 12 on the first interarea 001, injecting p-type ion (is herein general note, termination environment
Have injection), and trap is pushed away, P type trap zone 8 is formed between adjacent Second Type groove 4；Here the junction depth of P type trap zone 8 is greater than N-type source
The junction depth of polar region 9, and N-type source region 9 is located at the top in P type trap zone 8；
As shown in figure 17, step 13 deposits one layer of dielectric layer on first interarea 001, obtains insulating medium layer
12；
Step 14 performs etching the insulating medium layer 12, is contacted under the blocking of graphical photoresist
Hole, wherein the contact hole of break-through N-type source region 9 extends in P type trap zone 8,
It can also include grid polycrystalline silicon contact hole and separate gate polysilicon contact hole；
As shown in figure 18, step 15 deposited metal on the insulating medium layer 12 and in contact hole, to metal
Layer performs etching, and obtains source metal 13, gate metal, source metal 13 and 9 Ohmic contact of N-type source region, and pass through grid
Polysilicon contact hole is electrically connected with grid polycrystalline silicon 10, and the gate metal is more by separate gate polysilicon contact hole and separate gate
Crystal silicon 5 is electrically connected；
Gate metal, grid polycrystalline silicon contact hole and separate gate polysilicon contact hole are not drawn into the present embodiment, this is
Well-known to those skilled in the art, details are not described herein again；
As shown in Fig. 2, six, of step 10 deposits metal on the second interarea 002, drain metal 14, drain metal 14 are obtained
With 1 Ohmic contact of N-type substrate.
The working principle of the utility model is, since separation gate polysilicon 5 gos deep into N-type drift region 2, when device bears high electricity
When pressure, adjacent separation gate polysilicon 5 and N-type drift region 2 can mutually exhaust, and transverse electric field be formed, due to the thickness of thick oxide layer 6
It can freely adjust, so that the effect of device having lateral depletion is more preferable, device pressure resistance performance is more excellent, and such the utility model device exists
Same resistance to pressure, epitaxial wafer (i.e. N-type drift region 2) can select the smaller specification of resistivity, the conducting resistance of corresponding device
It can significantly reduce；That is, the power MOSFET device that the utility model structure fabrication comes out, in same current processing capacity
Under, chip area is smaller, has better market application prospect.
The utility model and embodiments thereof are described above, description is not limiting, shown in the drawings
It also is one of the embodiments of the present invention, practical structures are not limited thereto.All in all if this field it is common
Technical staff is enlightened by it, without deviating from the purpose of the present invention, is not inventively designed and the skill
The similar frame mode of art scheme and embodiment, all should belong to the protection range of the utility model.
Claims (6)
1. a kind of separation grid MOSFET component structure, including active area, the interior active area includes several devices parallel with one another
Part cellular unit, the device cellular unit include the first conductivity type substrate (1) and are located on the first conductivity type substrate (1)
The first conduction type drift region (2), first conduction type drift region (2) top be equipped with the second conduction type well region
(8), which is characterized in that be equipped with first kind groove (3) between the second conduction type well region (8) and be located at the first kind
The second class groove (4) of type groove (3) two sides, and the first kind groove (3) and the second class groove (4) are from the first conduction
Type drift region (2) surface extends to inside it, filled with separation gate polysilicon (5), packet in the first kind groove (3)
The thick oxide layer (6) and lid of wrapping up in separation gate polysilicon (5) are enclosed in the oxidation masking layer on separation gate polysilicon (5)
(7), filled with grid polycrystalline silicon (10) and the gate oxidation being located on the outside of grid polycrystalline silicon (10) in the second class groove (4)
Layer (11), the inside and thick oxide layer (6) of the grid polycrystalline silicon (10) are adjacent.
2. a kind of separation grid MOSFET component structure according to claim 1, it is characterised in that: the first kind groove
(3) and on the second class groove (4) it is covered with insulating medium layer (12), is covered with source metal on the insulating medium layer (12)
(13), the top in the second conduction type well region (8) is equipped with the first conductive type source area (9), the source metal
(13) it is filled in the contact hole between the first conductive type source area (9), the source metal (13) and first kind groove (3)
Interior separation gate polysilicon (5) electrical connection.
3. a kind of separation grid MOSFET component structure according to claim 2, it is characterised in that: first conduction type
Source area (9) and the second class groove (4) are adjacent, and the source metal (13) passes through insulating medium layer (12) and the second class groove
(4) grid polycrystalline silicon (10) isolation in.
4. a kind of separation grid MOSFET component structure according to claim 1, it is characterised in that: the first kind groove
(3) depth is greater than second class groove (4) depth, and the depth of the second class groove (4) is not less than the second conduction type well region
(8) junction depth.
5. a kind of separation grid MOSFET component structure according to claim 1, it is characterised in that: in first conductive-type
Drain metal (14) are arranged in the lower surface of type substrate (1), and the drain metal (14) connects with the first conductivity type substrate (1) ohm
Touching.
6. a kind of separation grid MOSFET component structure according to claim 1, it is characterised in that: for N-type MOSFET device
Part structure, first conduction type are that N-type is conductive, and second conduction type is P-type conduction；For p-type MOSFET element
Structure, first conduction type are P-type conduction, and second conduction type is that N-type is conductive.
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| CN201821247697.2U CN208400855U (en) | 2018-08-03 | 2018-08-03 | A kind of separation grid MOSFET component structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108767004A (en) * | 2018-08-03 | 2018-11-06 | 江苏捷捷微电子股份有限公司 | A kind of separation grid MOSFET component structure and its manufacturing method |
| CN117153885A (en) * | 2023-09-15 | 2023-12-01 | 陕西亚成微电子股份有限公司 | Split gate trench MOSFET device and method of making |
-
2018
- 2018-08-03 CN CN201821247697.2U patent/CN208400855U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108767004A (en) * | 2018-08-03 | 2018-11-06 | 江苏捷捷微电子股份有限公司 | A kind of separation grid MOSFET component structure and its manufacturing method |
| CN108767004B (en) * | 2018-08-03 | 2024-02-09 | 江苏捷捷微电子股份有限公司 | Split gate MOSFET device structure and manufacturing method thereof |
| CN117153885A (en) * | 2023-09-15 | 2023-12-01 | 陕西亚成微电子股份有限公司 | Split gate trench MOSFET device and method of making |
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Address after: No.3000 Qiantangjiang Road, Qidong Economic Development Zone, Nantong City, Jiangsu Province Patentee after: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd. Address before: 226200, No. 8, Xinglong Road, Qidong science and Technology Pioneer Park, Nantong, Jiangsu Patentee before: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd. |