CN111276394B - Manufacturing method of split gate MOSFET - Google Patents

Manufacturing method of split gate MOSFET Download PDF

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CN111276394B
CN111276394B CN202010100261.6A CN202010100261A CN111276394B CN 111276394 B CN111276394 B CN 111276394B CN 202010100261 A CN202010100261 A CN 202010100261A CN 111276394 B CN111276394 B CN 111276394B
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oxide layer
silicon
layer
polysilicon
separation gate
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CN111276394A (en
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顾昀浦
黄健
孙闫涛
宋跃桦
吴平丽
樊君
张丽娜
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Jiejie Microelectronics Shanghai Technology Co ltd
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Abstract

The invention discloses a manufacturing method of a separation grid MOSFET, which comprises the following steps: selecting a silicon substrate with a silicon epitaxial layer formed on the surface, and sequentially depositing a first oxide layer, a silicon nitride layer and a second oxide layer; etching the surface of the silicon epitaxial layer to form a groove; step three, removing the second oxide layer; step four, forming a separation gate oxide layer; fifthly, forming separation gate polysilicon in the groove; sixthly, exposing the separation gate polycrystalline silicon outside the separation gate oxide layer; removing the part of the polysilicon of the separation gate, which is higher than the oxide layer of the separation gate; eighthly, removing the silicon nitride layer and the first oxide layer; step nine, forming a grid oxide layer by thermal oxidation, and simultaneously forming an inter-polysilicon isolation oxide layer on the top of the polysilicon of the separation grid; step ten, forming grid polysilicon. The shape of the isolation oxide layer between the polycrystalline silicon is optimized, the thickness of the isolation oxide layer is increased, good isolation can be formed between the grid polycrystalline silicon and the separation grid polycrystalline silicon, and the effects of reducing electric leakage and parasitic capacitance are achieved.

Description

Manufacturing method of split gate MOSFET
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a separation gate MOSFET.
Background
The trench power MOSFET is a high-efficiency switching device newly developed after a planar VDMOS, and is widely applied to the field of power electronics due to the advantages of high input impedance, small driving current, high switching speed, good high-temperature characteristics and the like. The high breakdown voltage, the large current and the low on-resistance are the most critical indexes of the power MOSFET, the breakdown voltage is related to the on-resistance value, and the high breakdown voltage and the low on-resistance cannot be obtained simultaneously in the MOSFET design process, so that the breakdown voltage and the low on-resistance need to be mutually balanced.
Compared with the common trench MOSFET structure, the novel split gate MOSFET device has the main characteristic that a deep trench split gate which is in short circuit with a source electrode is added, and then the effect of improving the withstand voltage of the device is achieved by utilizing a transverse electric field between the split gates.
As shown in fig. 1, the MOSFET device with the current split gate structure has the following disadvantages:
1. inter-poly oxide (IPO) insulation between the source and the gate is poor, resulting in increased gate source leakage current Igss;
2. the overlap area between the source and the gate is too large, and the thickness of the inter-polysilicon isolation oxide layer is insufficient, so that the capacitance Cgs between the source and the gate is greatly increased.
The main reason for the above disadvantage is that, in the prior art manufacturing process, as shown in fig. 2A to 2D, after the wet etching is performed to remove the separation gate oxide layer on the sidewall of the trench, the surface of the separation gate polysilicon is higher than the separation gate oxide layer, and recessed structures are formed on both sides of the separation gate polysilicon, so that when the gate oxide layer and the inter-polysilicon isolation oxide layer are formed in the subsequent process, the formed inter-polysilicon isolation oxide layer has a very thin thickness, and thus a "u" shape is formed, so that the source and the gate are poorly insulated and the overlapping area is too large, thereby causing the above disadvantage.
Disclosure of Invention
The invention aims to provide a manufacturing method of a separation gate MOSFET, which increases the thickness of the separation gate MOSFET by optimizing the shape of an inter-polysilicon isolation oxide layer between the polysilicon of the separation gate and the polysilicon of a grid electrode so as to improve the performance and the reliability of the separation gate MOSFET.
In order to solve the above technical problem, the present invention provides a method for manufacturing a split gate MOSFET, comprising the following steps:
the method comprises the following steps of firstly, selecting a silicon substrate with a silicon epitaxial layer formed on the surface, and sequentially depositing a first oxide layer, a silicon nitride layer and a second oxide layer on the silicon epitaxial layer;
etching the second oxide layer, the silicon nitride layer, the first oxide layer and the silicon epitaxial layer by adopting a photoetching process to form a groove;
step three, removing the second oxide layer;
growing an oxide layer in the groove in a thermal oxidation mode, and forming a separation gate oxide layer at the bottom and the side wall of the groove; the thermal oxidation process consumes silicon from the trench sidewalls, increasing the width of the trench.
Depositing polycrystalline silicon in the groove formed by the separated gate oxide layer, and back-etching the polycrystalline silicon to form separated gate polycrystalline silicon in the groove;
removing the separation gate oxide layer on the surface of the silicon nitride layer and the separation gate oxide layer on the side wall of the groove on the top of the separation gate polycrystalline silicon in a wet etching mode so as to expose the separation gate polycrystalline silicon outside the separation gate oxide layer;
removing the part of the separation gate polycrystalline silicon higher than the separation gate oxide layer in a dry etching mode; the surface of the silicon epitaxial layer is protected by the silicon nitride layer, so that the shapes of the surface of the silicon epitaxial layer and the side wall of the groove cannot be influenced when dry etching is carried out;
step eight, removing the silicon nitride layer and the first oxide layer;
growing an oxide layer in the trench in a thermal oxidation mode, forming a gate oxide layer on the side wall of the trench, and simultaneously forming an inter-polysilicon isolation oxide layer on the top of the polysilicon of the separation gate;
and step ten, depositing polycrystalline silicon in the groove formed by the grid oxide layer and the inter-polycrystalline silicon isolation oxide layer, back-etching the polycrystalline silicon, and forming grid polycrystalline silicon in the groove.
Further, the silicon substrate is heavily doped with the first conduction type, the back surface of the silicon substrate is used for forming a drain electrode, the silicon epitaxial layer is lightly doped with the first conduction type, and the silicon epitaxial layer is used for forming a drift region of the split-gate MOSFET.
Further, a well region of a second conductivity type is formed in the silicon epitaxial layer, the gate polysilicon passing through the well region, the gate polysilicon laterally covering the well region and being for forming a channel laterally of the well region.
Further, in the fourth step, the separation gate oxide layer extends to the surface of the silicon nitride layer outside the trench.
Further, the fourth step further comprises: and depositing an oxide layer on the separation gate oxide layer by a Chemical Vapor Deposition (CVD) mode to increase the thickness of the separation gate oxide layer.
Further, in step five and/or step ten, polysilicon is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) manner.
Further, in the eighth step, the silicon nitride layer and the first oxide layer are removed by wet etching.
Further, in the ninth step, the thermal oxidation mode is a low-temperature wet oxidation mode, and the temperature is lower than 850 ℃. The low-temperature wet oxygen mode with the temperature lower than 850 ℃ can ensure that the thickness ratio of the oxide layer grown on the polysilicon and the monocrystalline silicon is more than 4:1, namely the ratio of the thickness of the inter-polysilicon isolation oxide layer grown on the top of the polysilicon of the separation gate to the thickness of the gate oxide layer grown on the side wall of the groove is more than 4:1, the thickness of the isolation oxide layer between the polysilicon is obviously increased, and the structure between the polysilicon of the separation gate and the polysilicon of the grid electrode is optimized.
Further, the thickness of the first oxide layer is
Figure BDA0002386695280000031
And/or the thickness of the silicon nitride layer is
Figure BDA0002386695280000032
And/or the thickness of the second oxide layer is
Figure BDA0002386695280000033
Further, the depth of the groove is 2-6 μm
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention adopts a low-temperature wet oxidation mode with the temperature lower than 850 ℃ to ensure that the thickness ratio of the oxide layer grown on the polycrystalline silicon and the monocrystalline silicon is more than 4:1, so that the thickness of the isolation oxide layer between the polycrystalline silicon is more than four times of the thickness of the grid oxide layer, the shape of the isolation oxide layer between the polycrystalline silicon is optimized, the thickness of the isolation oxide layer between the polycrystalline silicon is increased, good isolation can be formed between the grid polycrystalline silicon and the separation grid polycrystalline silicon, and the effects of reducing electric leakage and reducing parasitic capacitance are achieved.
(2) According to the method, after the part of the separation gate polycrystalline silicon higher than the separation gate oxide layer is removed, the inter-polycrystalline silicon isolation oxide layer and the gate oxide layer are simultaneously grown in a thermal oxidation mode, so that the phenomenon that holes are generated between the inter-polycrystalline silicon isolation oxide layer and the gate oxide layer to reduce the reliability of a device and influence the process parameters of the device can be avoided.
(3) The method can form the inter-polysilicon isolation oxide layer and the grid oxide layer meeting the process requirements at one time, does not need to further process the inter-polysilicon isolation oxide layer or the grid oxide layer, and effectively simplifies the process steps.
(4) The oxide-nitride-oxide (ONO) structure of the first oxide layer-silicon nitride layer-second oxide layer is arranged on the surface of the silicon epitaxial layer, so that the mask can be used as a hard mask to improve the mask strength, the side wall of the groove and the surface of the silicon epitaxial layer can be protected from being influenced by etching, the stability of the process is improved, and the yield of devices is ensured. When the separation gate oxide layer grows in the trench in a thermal oxidation mode, silicon of the silicon epitaxial layer on the side wall of the trench is consumed in the thermal oxidation process, so that the side wall of the trench is blocked by the silicon nitride layer at the top of the trench, the side wall of the trench is protected, and when the part of the separation gate polycrystalline silicon higher than the separation gate oxide layer is removed in subsequent dry etching, the silicon nitride layer can protect the side wall of the trench and the surface of the silicon epitaxial layer from being influenced by etching.
Drawings
FIG. 1 is a schematic diagram of a prior art split-gate MOSFET structure;
FIGS. 2A to 2D are schematic views of the device structure in the steps of the method for manufacturing the prior art split-gate MOSFET;
FIGS. 3A-3J are schematic views of device structures at various steps of a method according to an embodiment of the invention;
fig. 4 is a schematic diagram of the device structure when step seven is not executed.
In the figure: 1. a silicon substrate; 2. a silicon epitaxial layer; 3. a first oxide layer; 4. a silicon nitride layer; 5. a second oxide layer; 6. a trench; 7. separating the gate oxide layer; 8. separating the gate polysilicon; 9. a gate oxide layer; 10. an inter-polysilicon isolation oxide layer; 11. grid polysilicon; 12. a front metal layer; 13. a back metal layer; 14. a well region; 15. a source region; 16. an interlayer film; 17. and (4) holes.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 3A to 3E, which are schematic device structure diagrams of steps of the method according to the embodiment of the present invention, the method for manufacturing the split-gate MOSFET according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a silicon substrate 1 with a silicon epitaxial layer 2 formed on the surface is selected, and a first oxide layer 3, a silicon nitride layer 4 and a second oxide layer 5 are sequentially deposited on the silicon epitaxial layer. Preferably, the thickness of the first oxide layer is
Figure BDA0002386695280000051
And/or the thickness of the silicon nitride layer is
Figure BDA0002386695280000052
And/or the thickness of the second oxide layer is
Figure BDA0002386695280000053
The silicon substrate 1 is heavily doped with the first conductivity type, the back surface of the silicon substrate 1 is used for forming a drain electrode, the silicon epitaxial layer 2 is lightly doped with the first conductivity type, and the silicon epitaxial layer 2 is used for forming a drift region of a split gate MOSFET.
Step two, as shown in fig. 3B, the second oxide layer 5, the silicon nitride layer 4, the first oxide layer 3 and the silicon epitaxial layer 2 are etched by using a photolithography process to form a trench 6. Preferably, the depth of the groove is 2-6 μm.
And step three, as shown in fig. 3C, removing the second oxide layer 5 by dry etching or wet etching.
Step four, as shown in fig. 3D, growing an oxide layer in the trench 6 by thermal oxidation, and forming a thick separation gate oxide layer 7 on the bottom and the sidewall of the trench 6. The thermal oxidation process consumes silicon of the silicon epitaxial layer 2 at the sidewalls of the trench 6, so that the width of the trench 6 is increased. It is noted that an oxide layer may be deposited on the separation gate oxide layer 7 by CVD to increase the thickness of the separation gate oxide layer 7, and the separation gate oxide layer 7 extends to the surface of the silicon nitride layer 4 outside the trench 6.
And step five, as shown in fig. 3E, depositing polycrystalline silicon in the trench 6 formed by the separation gate oxide layer 7, and etching back the polycrystalline silicon to form separation gate polycrystalline silicon 8 in the trench 6. Preferably, the polysilicon is deposited by LPCVD.
Sixthly, as shown in fig. 3F, removing the separation gate oxide layer 7 on the surface of the silicon nitride layer 4 and the separation gate oxide layer 7 on the side wall of the trench 6 on the top of the separation gate polysilicon 8 by wet etching, so that the separation gate polysilicon 8 is exposed out of the separation gate oxide layer 7.
And seventhly, as shown in fig. 3G, removing the part of the separation gate polysilicon 8 higher than the separation gate oxide layer 7 in a dry etching mode. In the sixth step, the oxide layer on the surface of the silicon epitaxial layer 2 and the oxide layer on the upper side wall of the trench 6 are removed by wet etching, and the monocrystalline silicon parts of the silicon epitaxial layer 2 and the trench 6 are exposed outside, so that in the conventional process, if the part of the separation gate polycrystalline silicon 8 higher than the separation gate oxide layer 7 is removed by dry etching, the inner wall of the trench 6 is easily damaged, and the device structure is damaged. In this embodiment, by depositing an oxide-nitride-oxide (ONO) structure on the surface of the silicon epitaxial layer 2, after the thermal oxidation treatment in the fourth step, the thermal oxidation process consumes silicon on the sidewall of the trench 6, and the width of the trench 6 is increased, so that the silicon nitride layer 4 blocks the sidewall of the trench 6 at the top of the trench 6 to protect the sidewall of the trench 6; and after the wet etching treatment in the sixth step, the silicon nitride layer 4 is still arranged on the surface of the silicon epitaxial layer 2 and the top of the groove 6 to be used as protection, and the shape of the surface of the silicon epitaxial layer 2 and the shape of the side wall of the groove 6 are not influenced during the dry etching.
And step eight, as shown in fig. 3H, removing the silicon nitride layer 4 and the first oxide layer 3 by wet etching.
Step nine, as shown in fig. 3I, an oxide layer is grown in the trench 6 in a low-temperature wet oxidation manner at a temperature lower than 850 ℃, a gate oxide layer 9 is formed on the sidewall of the trench 6, and an inter-polysilicon isolation oxide layer 10 is formed on the top of the split gate polysilicon 8. The low temperature wet oxygen mode with the temperature lower than 850 ℃ can ensure that the thickness ratio of the oxide layer grown on the polysilicon and the monocrystalline silicon is more than 4:1, namely the ratio of the thickness of the inter-polysilicon isolation oxide layer 10 grown on the top of the separation gate polysilicon 8 to the thickness of the gate oxide layer 9 grown on the side wall of the groove 6 is more than 4:1, the thickness of the inter-polysilicon isolation oxide layer 10 is obviously increased, and the appearance of the inter-polysilicon isolation oxide layer 10 is improved. In the growth process, the surface of the polysilicon 8 of the split gate gradually changes into an arc shape due to consumption, so that the inter-polysilicon isolation oxide layer 10 also has a relatively smooth arc shape, and the inverted U-shaped inter-polysilicon isolation oxide layer 10 formed by the traditional process is obviously improved.
It should be noted that, if step seven is not executed, the portion of the separation gate polysilicon 8 higher than the separation gate oxide layer 7 is removed, and when step nine is executed, since the thickness of the inter-polysilicon isolation oxide layer 10 is more than 4 times of the thickness of the gate oxide layer 9, the situation shown in fig. 4 may be caused, and a hole 17 is easily generated between the bottom of the inter-polysilicon isolation oxide layer 10 and the gate oxide layer 9, so that the hole 17 cannot be filled with the gate polysilicon 11 when the gate polysilicon 11 is filled subsequently, which reduces the reliability of the device and affects the process parameters of the device.
Step ten, as shown in fig. 3J, depositing polysilicon in the trench 6 formed by the gate oxide layer 9 and the inter-polysilicon isolation oxide layer 10, and etching back the polysilicon to form a gate polysilicon 11 in the trench 6. Preferably, the polysilicon is deposited by LPCVD.
Other structures of the split-gate MOSFET are formed by the conventional method, such as forming a well region 14 of the second conductivity type in the silicon epitaxial layer 2, forming a source region 15 in the well region 14, the gate polysilicon 11 passing through the well region, the gate polysilicon 11 laterally covering the well region 14 and being used for forming a channel laterally of the well region 14. The gate polysilicon 11 laterally covers the source region 15 and the well region 14, and the surface of the well region 14 laterally covered by the gate polysilicon 11 is used to form a channel connecting the source region 15 and the bottom silicon epitaxial layer 2.
Forming an interlayer film 16 to cover the device, forming a contact hole and a front metal layer 12, leading out a source electrode by contacting the front metal layer 12 with the source region 15 through the contact hole, and leading out a grid electrode by contacting the front metal layer 12 with the grid polysilicon 11 through the contact hole; a back metal layer 13 is formed to lead out the drain.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. A manufacturing method of a split gate MOSFET is characterized by comprising the following steps:
selecting a silicon substrate with a silicon epitaxial layer formed on the surface, and sequentially depositing a first oxide layer, a silicon nitride layer and a second oxide layer on the silicon epitaxial layer;
etching the second oxide layer, the silicon nitride layer, the first oxide layer and the silicon epitaxial layer by adopting a photoetching process to form a groove;
step three, removing the second oxide layer;
growing an oxide layer in the groove in a thermal oxidation mode, and forming a separation gate oxide layer at the bottom and the side wall of the groove;
depositing polycrystalline silicon in the groove formed by the separation gate oxide layer, back-etching the polycrystalline silicon, and forming separation gate polycrystalline silicon in the groove;
removing the separation gate oxide layer on the surface of the silicon nitride layer and the separation gate oxide layer on the side wall of the groove on the top of the separation gate polycrystalline silicon in a wet etching mode so as to expose the separation gate polycrystalline silicon outside the separation gate oxide layer;
removing the part of the separation gate polycrystalline silicon higher than the separation gate oxide layer in a dry etching mode;
eighthly, removing the silicon nitride layer and the first oxide layer;
growing an oxide layer in the trench in a low-temperature wet oxidation mode, forming a gate oxide layer on the side wall of the trench, and simultaneously forming an inter-polysilicon isolation oxide layer on the top of the polysilicon of the separation gate;
and step ten, depositing polycrystalline silicon in the groove formed by the grid oxide layer and the inter-polycrystalline silicon isolation oxide layer, back-etching the polycrystalline silicon, and forming grid polycrystalline silicon in the groove.
2. The method of claim 1, wherein in step one, the silicon substrate has a heavy doping of the first conductivity type, the back surface of the silicon substrate is used for forming a drain, the silicon epitaxial layer has a light doping of the first conductivity type, and the silicon epitaxial layer is used for forming a drift region of a split-gate MOSFET.
3. The method of claim 2, wherein a well region of the second conductivity type is formed in the epitaxial layer of silicon, the gate polysilicon passing through the well region, the gate polysilicon laterally overlying the well region and being configured to form a channel laterally of the well region.
4. The method of claim 1, wherein in step four, the separate gate oxide layer extends to the surface of the silicon nitride layer outside the trench.
5. The method of claim 1, wherein step four further comprises: and depositing an oxide layer on the separation gate oxide layer in a chemical vapor deposition mode to increase the thickness of the separation gate oxide layer.
6. The method of claim 1, wherein in step five and/or step ten, the polysilicon is deposited by low pressure chemical vapor deposition.
7. The method according to claim 1, wherein in step eight, the silicon nitride layer and the first oxide layer are removed by wet etching.
8. The manufacturing method according to claim 1, wherein in the ninth step, the temperature of the low-temperature wet oxidation mode is lower than 850 ℃.
9. The method of claim 1, wherein the first oxide layer has a thickness of
Figure FDA0002386695270000021
And/or the silicon nitride layer has a thickness of
Figure FDA0002386695270000022
And/or the thickness of the second oxide layer is
Figure FDA0002386695270000023
10. The method of claim 1, wherein the trench has a depth of 2-6 μm.
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