CN108364870A - Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality - Google Patents

Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality Download PDF

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Publication number
CN108364870A
CN108364870A CN201810062556.1A CN201810062556A CN108364870A CN 108364870 A CN108364870 A CN 108364870A CN 201810062556 A CN201810062556 A CN 201810062556A CN 108364870 A CN108364870 A CN 108364870A
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grid
oxide layer
polysilicon
deposit
source
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CN108364870B (en
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周宏伟
杨乐
刘挺
岳玲
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Longteng Semiconductor Co.,Ltd.
Xi'an Longxiang Semiconductor Co.,Ltd.
Xusi semiconductor (Shanghai) Co.,Ltd.
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XI'AN LONTEN RENEWABLE ENERGY TECHNOLOGY Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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Abstract

The present invention relates to a kind of shield grid groove MOSFET manufacturing methods improving grid oxic horizon quality, by being filled in deep trouth and being etched back to polysilicon, the mutual charge balance of two deep trouths is set to complete superjunction function, again using oxide layer between oxide layer deposit thickening gate-source above deep trouth, finally by grid thermal oxide and polycrystalline silicon deposit, shield grid trench device is collectively formed.By the specific condition high-density plasma chemical vapor deposition of once energy oxide layer anisotropy deposit, oxidated layer thickness and pattern between gate-source are adjusted the present invention, oxide layer between high quality gate-source can be formed, it can be realized with traditional semiconductor fabrication process, the quality of oxide layer between technology difficulty not increased improvement source polysilicon and grid polycrystalline silicon, optimize the parameter of product, yield rate and reliability are improved, reduction chip cost is finally reached.

Description

Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality
Technical field
The present invention relates to semiconductor power device technology fields, and in particular to a kind of shielding improving grid oxic horizon quality Gate groove MOSFET manufacturing methods.
Background technology
For traditional power MOSFET device, there are certain foldings with source and drain breakdown voltage for device on-resistance (Ron) Middle relationship（Ron∝BV2.5）, the development of power MOSFET device is limited for a long time.Shield grid groove MOSFET utilizes Charge balance concept so that N-type drift region can realize the higher breakdown potential of device in the case of higher-doped concentration Pressure, to obtain low conducting resistance, has broken the silicon limit of conventional power MOSFET.Such as Figure 21, standard process flow is highly doped It is uneven that miscellaneous polysilicon forms the oxidated layer thickness between quality of oxide layer is not high and grid source polarity, to device parameters and reliability Bring greater risk.
Invention content
The object of the present invention is to provide it is a kind of improve grid oxic horizon quality shield grid groove MOSFET manufacturing method, Under the premise of process costs are basically unchanged, it can be realized with traditional semiconductor fabrication process, before not increasing technology difficulty It puts and generates that thickness is adjustable, the preferable grid source electrode oxide layer of quality.
The technical solution adopted in the present invention is：
Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality, it is characterised in that：
By the way that polysilicon is filled and be etched back in deep trouth, the mutual charge balance of two deep trouths is set to complete superjunction function, then in depth Using oxide layer between oxide layer deposit thickening gate-source above slot, finally by grid thermal oxide and polycrystalline silicon deposit, jointly Constitute shield grid trench device.
Include the following steps：
Step 1：The n+ substrates of n type heavy doping are provided, and form N-shaped epitaxial layer on n+ substrates；
Step 2：Thick oxide layer is formed in epi-layer surface, row is at hard mask；
Step 3：The deep trench of the deep trench and termination environment of active area, termination environment deep trench packet are formed by photoetching, dry etching It is with source region deep trench, finally removes oxide film dissolving；
Step 4：Using wet thermal oxidation process field oxide is grown in the deep trench bottom and side wall；
Step 5：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 6：Polysilicon is carried out by dry corrosion process and returns quarter, makes to obtain a shallow trench above active area deep trench, eventually The first polysilicon and field oxide in petiolarea deep trench do not return quarter under the protection of photoresist；
Step 7：Thick oxide layer is removed by photoetching, wet etching；
Step 8：Continue back the polysilicon in ditch slot using etching technics；
Step 9：Utilize the specific condition high-density plasma chemical vapor deposition (HDP of energy oxide layer anisotropy deposit CVD) oxidated layer thickness and pattern are adjusted between gate-source；
Step 10：Side wall residue field oxide is removed using wet-etching technology；
Step 11：Grid oxic horizon is formed using dry oxidation；
Step 12：Second of polycrystalline silicon deposit, and second of polysilicon dry back is carved, form shallow slot MOSFET element grid Pole；
Step 13：Surface oxide layer is removed before trap injection；
Step 14：P-BODY injects, and forms p-well；
Step 15：Pass through injection, making devices active area；
Step 10 six：Dielectric layer deposited, contact hole etching；
Step 10 seven：Contact hole etching injects to form Ohmic contact；
Step 10 eight：Complete surface metal structure；
Step 10 nine：Thinning back side simultaneously completes back metal structure.
The manufacturing method shield grid trench MOSFET structure obtained for improving grid oxic horizon quality as mentioned.
The present invention has the following advantages：
The specific condition high-density plasma chemical vapor deposition that the present invention passes through once energy oxide layer anisotropy deposit (HDP CVD) oxidated layer thickness and pattern between gate-source is adjusted, and can form oxide layer between high quality gate-source, can To be realized with traditional semiconductor fabrication process, in the not increased improvement source polysilicon of technology difficulty and gate polycrystalline Quality of oxide layer between silicon optimizes the parameter of product, improves yield rate and reliability, is finally reached reduction chip cost.
Description of the drawings
Fig. 1 is the schematic diagram of step 1 of the present invention；
Fig. 2 is the schematic diagram of step 2 of the present invention；
Fig. 3 is the schematic diagram of step 3 of the present invention；
Fig. 4 is the schematic diagram of step 4 of the present invention；
Fig. 5 is the schematic diagram of step 5 of the present invention；
Fig. 6 is the schematic diagram of step 6 of the present invention；
Fig. 7 is the schematic diagram of step 7 of the present invention；
Fig. 8 is the schematic diagram of step 8 of the present invention；
Fig. 9 is the schematic diagram of step 9 of the present invention；
Figure 10 is the schematic diagram of step 10 of the present invention；
Figure 11 is the schematic diagram of step 11 of the present invention；
Figure 12 is the schematic diagram of step 12 of the present invention；
Figure 13 is the schematic diagram of step 13 of the present invention；
Figure 14 is the schematic diagram of step 14 of the present invention；
Figure 15 is the schematic diagram of step 15 of the present invention；
Figure 16 is the schematic diagram of step 10 six of the present invention；
Figure 17 is the schematic diagram of step 10 seven of the present invention；
Figure 18 is the schematic diagram of step 10 eight of the present invention；
Figure 19 is the schematic diagram of step 10 nine of the present invention；
Figure 20 is the sectional view of device of the present invention.
Figure 21 is the sectional view of existing old technique resulting devices.
Specific implementation mode
The present invention will be described in detail With reference to embodiment.
The present invention relates to the shield grid groove MOSFET manufacturing methods for improving grid oxic horizon quality, by being filled out in deep trouth Polysilicon is filled and be etched back to, so that the mutual charge balance of two deep trouths is completed superjunction function, then form sediment using oxide layer above deep trouth Oxide layer collectively forms shield grid trench device finally by grid thermal oxide and polycrystalline silicon deposit between product thickeies gate-source.
Specifically include following steps：
Step 1：The n+ substrates of n type heavy doping are provided, and form N-shaped epitaxial layer on n+ substrates；
Step 2：Thick oxide layer is formed in epi-layer surface, row is at hard mask；
Step 3：The deep trench of the deep trench and termination environment of active area, termination environment deep trench packet are formed by photoetching, dry etching It is with source region deep trench, finally removes oxide film dissolving；
Step 4：Using wet thermal oxidation process field oxide is grown in the deep trench bottom and side wall；
Step 5：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 6：Polysilicon is carried out by dry corrosion process and returns quarter, makes to obtain a shallow trench above active area deep trench, eventually The first polysilicon and field oxide in petiolarea deep trench do not return quarter under the protection of photoresist；
Step 7：Thick oxide layer is removed by photoetching, wet etching；
Step 8：Continue back the polysilicon in ditch slot using etching technics；
Step 9：Utilize the specific condition high-density plasma chemical vapor deposition (HDP of energy oxide layer anisotropy deposit CVD) oxidated layer thickness and pattern are adjusted between gate-source；
Step 10：Side wall residue field oxide is removed using wet-etching technology；
Step 11：Grid oxic horizon is formed using dry oxidation；
Step 12：Second of polycrystalline silicon deposit, and second of polysilicon dry back is carved, form shallow slot MOSFET element grid Pole；
Step 13：Surface oxide layer is removed before trap injection；
Step 14：P-BODY injects, and forms p-well；
Step 15：Pass through injection, making devices active area；
Step 10 six：Dielectric layer deposited, contact hole etching；
Step 10 seven：Contact hole etching injects to form Ohmic contact；
Step 10 eight：Complete surface metal structure；
Step 10 nine：Thinning back side simultaneously completes back metal structure.
The present invention is by the high-density plasma chemical vapor deposition (HDP CVD) of a specific condition to gate-source Between oxidated layer thickness and pattern be adjusted, old-fashioned scheme grid in the low quality oxide layer and Figure 21 that avoid polysilicon oxidation from being formed Root oxide layer is uneven between source, and pressure resistance is inadequate between causing grid source, component failure.
Method has the characteristics that：
One:One time the secondary of polysilicon is etched back to；
Two：The once specific condition high-density plasma chemical vapor deposition (HDP CVD) of energy oxide layer anisotropy deposit Oxidated layer thickness and pattern are adjusted between gate-source；
Three:It is poor using great corrosion rate between dry oxidation layer and deposited oxide layer, to device surface before trap injection Oxide layer is removed.
Present disclosure is not limited to cited by embodiment, and those of ordinary skill in the art are by reading description of the invention And to any equivalent transformation that technical solution of the present invention is taken, it is that claim of the invention is covered.

Claims (3)

1. improving the shield grid groove MOSFET manufacturing method of grid oxic horizon quality, it is characterised in that：
By the way that polysilicon is filled and be etched back in deep trouth, the mutual charge balance of two deep trouths is set to complete superjunction function, then in depth Using oxide layer between oxide layer deposit thickening gate-source above slot, finally by grid thermal oxide and polycrystalline silicon deposit, jointly Constitute shield grid trench device.
2. the shield grid groove MOSFET manufacturing method according to claim 1 for improving grid oxic horizon quality, feature It is：
Include the following steps：
Step 1：The n+ substrates of n type heavy doping are provided, and form N-shaped epitaxial layer on n+ substrates；
Step 2：Thick oxide layer is formed in epi-layer surface, row is at hard mask；
Step 3：The deep trench of the deep trench and termination environment of active area, termination environment deep trench packet are formed by photoetching, dry etching It is with source region deep trench, finally removes oxide film dissolving；
Step 4：Using wet thermal oxidation process field oxide is grown in the deep trench bottom and side wall；
Step 5：Using polycrystalline silicon deposition process, first time polycrystalline silicon deposit is carried out；
Step 6：Polysilicon is carried out by dry corrosion process and returns quarter, makes to obtain a shallow trench above active area deep trench, eventually The first polysilicon and field oxide in petiolarea deep trench do not return quarter under the protection of photoresist；
Step 7：Thick oxide layer is removed by photoetching, wet etching；
Step 8：Continue back the polysilicon in ditch slot using etching technics；
Step 9：Utilize the specific condition high-density plasma chemical vapor deposition (HDP of energy oxide layer anisotropy deposit CVD) oxidated layer thickness and pattern are adjusted between gate-source；
Step 10：Side wall residue field oxide is removed using wet-etching technology；
Step 11：Grid oxic horizon is formed using dry oxidation；
Step 12：Second of polycrystalline silicon deposit, and second of polysilicon dry back is carved, form shallow slot MOSFET element grid Pole；
Step 13：Surface oxide layer is removed before trap injection；
Step 14：P-BODY injects, and forms p-well；
Step 15：Pass through injection, making devices active area；
Step 10 six：Dielectric layer deposited, contact hole etching；
Step 10 seven：Contact hole etching injects to form Ohmic contact；
Step 10 eight：Complete surface metal structure；
Step 10 nine：Thinning back side simultaneously completes back metal structure.
3. the manufacturing method as claimed in claim 1 or 2 shield grid groove MOSFET obtained for improving grid oxic horizon quality Structure.
CN201810062556.1A 2018-01-23 2018-01-23 Manufacturing method of shielded gate trench MOSFET (Metal-oxide-semiconductor field Effect transistor) for improving quality of gate oxide layer Active CN108364870B (en)

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111276394A (en) * 2020-02-18 2020-06-12 捷捷微电(上海)科技有限公司 Manufacturing method of split gate MOSFET
CN111446157A (en) * 2020-04-07 2020-07-24 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and method of forming the same
CN111463282A (en) * 2020-03-30 2020-07-28 南京华瑞微集成电路有限公司 Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method
CN112133637A (en) * 2020-11-30 2020-12-25 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device with shielded gate trench
CN112185816A (en) * 2020-08-14 2021-01-05 江苏东海半导体科技有限公司 High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof
CN112864248A (en) * 2019-11-28 2021-05-28 南通尚阳通集成电路有限公司 SGTMOSFET device and manufacturing method
CN112908841A (en) * 2021-03-24 2021-06-04 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device
CN113471078A (en) * 2021-06-11 2021-10-01 上海格瑞宝电子有限公司 SGT-MOSFET and manufacturing method thereof
CN113725078A (en) * 2021-09-11 2021-11-30 捷捷微电(上海)科技有限公司 Manufacturing method of split gate MOSFET
CN116053315A (en) * 2023-02-16 2023-05-02 捷捷微电(南通)科技有限公司 SGT device manufacturing method
CN116344622A (en) * 2023-05-25 2023-06-27 成都吉莱芯科技有限公司 SGT MOSFET device with low output capacitance and manufacturing method
CN117410173A (en) * 2023-12-15 2024-01-16 中晶新源(上海)半导体有限公司 Manufacturing method of trench semiconductor device with stepped dielectric layer
CN117457499A (en) * 2023-11-01 2024-01-26 中晶新源(上海)半导体有限公司 Technological method for improving HDP filling of shielded gate power semiconductor device
CN117524878A (en) * 2023-11-13 2024-02-06 中晶新源(上海)半导体有限公司 SGT-MOSFET manufacturing method
WO2024109192A1 (en) * 2022-11-22 2024-05-30 华润微电子（重庆）有限公司 Shielded gate power mosfet and manufacturing method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080138953A1 (en) * 2003-05-20 2008-06-12 Ashok Challa Methods of Making Power Semiconductor Devices with Thick Bottom Oxide Layer
CN101315893A (en) * 2007-05-30 2008-12-03 上海华虹Nec电子有限公司 Method for implementing groove type double-layer grid power MOS structure
CN105914234A (en) * 2016-06-28 2016-08-31 上海华虹宏力半导体制造有限公司 Separating gate power MOS transistor structure and manufacturing method therefor
CN106206322A (en) * 2016-08-30 2016-12-07 西安龙腾新能源科技发展有限公司 The manufacture method of autoregistration low pressure superjunction MOFET

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080138953A1 (en) * 2003-05-20 2008-06-12 Ashok Challa Methods of Making Power Semiconductor Devices with Thick Bottom Oxide Layer
CN101315893A (en) * 2007-05-30 2008-12-03 上海华虹Nec电子有限公司 Method for implementing groove type double-layer grid power MOS structure
CN105914234A (en) * 2016-06-28 2016-08-31 上海华虹宏力半导体制造有限公司 Separating gate power MOS transistor structure and manufacturing method therefor
CN106206322A (en) * 2016-08-30 2016-12-07 西安龙腾新能源科技发展有限公司 The manufacture method of autoregistration low pressure superjunction MOFET

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864248A (en) * 2019-11-28 2021-05-28 南通尚阳通集成电路有限公司 SGTMOSFET device and manufacturing method
CN111276394B (en) * 2020-02-18 2022-09-23 捷捷微电(上海)科技有限公司 Manufacturing method of split gate MOSFET
CN111276394A (en) * 2020-02-18 2020-06-12 捷捷微电(上海)科技有限公司 Manufacturing method of split gate MOSFET
CN111463282A (en) * 2020-03-30 2020-07-28 南京华瑞微集成电路有限公司 Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method
CN111463282B (en) * 2020-03-30 2023-09-26 南京华瑞微集成电路有限公司 Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method
CN111446157A (en) * 2020-04-07 2020-07-24 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and method of forming the same
CN112185816A (en) * 2020-08-14 2021-01-05 江苏东海半导体科技有限公司 High-energy-efficiency shielded gate trench MOSFET and manufacturing method thereof
CN112133637B (en) * 2020-11-30 2021-02-12 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device with shielded gate trench
CN112133637A (en) * 2020-11-30 2020-12-25 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device with shielded gate trench
CN112908841A (en) * 2021-03-24 2021-06-04 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device
CN112908841B (en) * 2021-03-24 2024-03-22 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device
CN113471078A (en) * 2021-06-11 2021-10-01 上海格瑞宝电子有限公司 SGT-MOSFET and manufacturing method thereof
CN113725078A (en) * 2021-09-11 2021-11-30 捷捷微电(上海)科技有限公司 Manufacturing method of split gate MOSFET
WO2024109192A1 (en) * 2022-11-22 2024-05-30 华润微电子（重庆）有限公司 Shielded gate power mosfet and manufacturing method therefor
CN116053315A (en) * 2023-02-16 2023-05-02 捷捷微电(南通)科技有限公司 SGT device manufacturing method
CN116344622A (en) * 2023-05-25 2023-06-27 成都吉莱芯科技有限公司 SGT MOSFET device with low output capacitance and manufacturing method
CN117457499A (en) * 2023-11-01 2024-01-26 中晶新源(上海)半导体有限公司 Technological method for improving HDP filling of shielded gate power semiconductor device
CN117524878A (en) * 2023-11-13 2024-02-06 中晶新源(上海)半导体有限公司 SGT-MOSFET manufacturing method
CN117410173A (en) * 2023-12-15 2024-01-16 中晶新源(上海)半导体有限公司 Manufacturing method of trench semiconductor device with stepped dielectric layer
CN117410173B (en) * 2023-12-15 2024-03-08 中晶新源(上海)半导体有限公司 Manufacturing method of trench semiconductor device with stepped dielectric layer

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