CN105845736A - LDMOS device structure and manufacture method thereof - Google Patents

LDMOS device structure and manufacture method thereof Download PDF

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Publication number
CN105845736A
CN105845736A CN201610325621.6A CN201610325621A CN105845736A CN 105845736 A CN105845736 A CN 105845736A CN 201610325621 A CN201610325621 A CN 201610325621A CN 105845736 A CN105845736 A CN 105845736A
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layer
ldmos device
metal
device structure
dielectric layer
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CN201610325621.6A
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Inventor
彭虎
张耀辉
莫海锋
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KUNSHAN HUATAI ELECTRONIC TECHNOLOGY Co Ltd
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KUNSHAN HUATAI ELECTRONIC TECHNOLOGY Co Ltd
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Priority to CN201610325621.6A priority Critical patent/CN105845736A/en
Priority to PCT/CN2016/091817 priority patent/WO2017197758A1/en
Publication of CN105845736A publication Critical patent/CN105845736A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses an LDMOS device structure which comprises a metal connection layer. Through the metal connection layer, an LDMOS device source electrode is connected with a substrate from the surface. An LDMOS device channel is a concentration gradient channel. The invention further discloses the manufacture method of the device structure. According to the invention, after polysilicon etching, a medium layer of high step coverage rate is deposited and is used as an injection barrier layer; the problem of photoetching alignment accuracy is solved; self-alignment injection of gate length below 0.25um is realized; through the metal connection layer, the source electrode is connected with the substrate from the surface; after a device is formed, a metal connection layer process is carried out, and gate length below 0.25um is realized; and the manufacture yield and the uniformity can be ensured.

Description

A kind of LDMOS device structure and manufacture method
Technical field
The present invention relates to a kind of LDMOS device structure and manufacture method, belong to semiconductor integrated circuit manufacture Field.
Background technology
RFLDMOS is the improved N-channel MOS FET designed for radio-frequency power amplifier, has Horizontal communication structure, drain electrode, source electrode and grid are all at chip surface.Source electrode is typically by internal high impurity concentration Passage and the also ground connection that is connected bottom substrate, have the N-type drift region of a low concentration between raceway groove and drain electrode. LDMOS uses double diffusion technique, in succession carries out twice diffusion of boron phosphorus at same photoetching window, by twice impurity The difference spreading horizontal junction depth can accurately determine channel length.Channel length L can be made very small and be not subject to The restriction of lithographic accuracy.Owing to LDMOS is easily achieved the channel length of submicron in technique, therefore mutual conductance, The MOSFET that drain current, maximum operating frequency and speed are the most general has and significantly improves；High resistant drifts about The existence in district improves breakdown voltage, and makes the dead resistance between drain-source the two poles of the earth be reduced, and this is conducive to Improve frequency characteristic.
LDMOS uses autoregistration injection and horizontal proliferation technique to form raceway groove, and length of effective channel depends on many Crystal silicon grid length, double diffusion boron phosphorus implantation dosage and thermal process.Reducing polysilicon gate length can make effective grid length contract Short, reduce Cgs and Cgd, improve device transconductance and characteristic frequency, thus realize more preferable radio-frequency performance.
Existing RFLDMOS technique typically uses polysilicon gate autoregistration to carry out boron diffusion, polysilicon gate length one As more than 0.35um, stop to avoid photoetching to cause to inject to local derviation.The denseest boron injects and long term annealing shape Becoming source electrode surface and substrate to connect, long-time high temperature can cause the warpage that silicon chip is bigger, it is impossible to realizes 0.25um Following is lithographic dimensioned.
Summary of the invention
In order to solve above-mentioned technical problem, the invention provides a kind of LDMOS device structure and manufacture method.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of LDMOS device structure, including metal connecting layer, described metal connecting layer is by LDMOS device Source electrode is connected to substrate from surface, and the raceway groove of described LDMOS device is concentration gradient raceway groove.
The a length of 90-250nm of grid of described LDMOS device.
Metal connecting layer material is tungsten or copper.
Raceway groove is P-type channel, and raceway groove is high near source electrode side concentration.
The manufacture method of a kind of LDMOS device structure, comprises the following steps,
Step 1, grid oxygen and grid deposit；
Step 2, after grid etching and N-type drift region are injected, at one layer of dielectric layer of surface deposition；
Step 3, autoregistration p-type is injected, and anneals and forms concentration gradient raceway groove；
Step 4, dense N-type is injected, and forms source electrode and drain electrode；
Step 5, dielectric layer etches, and forms side wall in grid both sides；
Step 6, the dense P of autoregistration injects, and forms p-type articulamentum；
Step 7, silicide makes and faraday shield layer makes；
Step 8, dielectric layer deposition and planarization, form metal level；
After step 9, dielectric layer fairlead and silicon via etch metal filled, form fairlead and metal respectively even Connect layer；
Step 10, deposits on the metal layer and etches, and forms metal electrode.
The thickness of dielectric layer is 500-2000 angstrom, dielectric layer step deposit step coverage > 90%, material is LPCVD SiO2 and or LPCVD SiN.
The beneficial effect that the present invention is reached: the present invention deposits one layer of step coverage after using etching polysilicon High dielectric layer, as implant blocking layer, solves photoetching aligning accuracy problem, it is possible to achieve below 0.25um The autoregistration of grid length is injected；Using metal connecting layer that source electrode is connected to substrate from surface, metal connects simultaneously Layer process is carried out after device is formed, such that it is able to the grid realizing below 0.25um are long, fine ratio of product is with uniform Property can be protected.
Accompanying drawing explanation
Fig. 1 is the structural representation of LDMOS device.
Fig. 2 is that polysilicon gate is formed.
Fig. 3 forms dielectric layer for deposit.
Fig. 4 is that N-skew district is injected.
Fig. 5 is that p-type is injected.
Fig. 6 is that N+ injects.
Fig. 7 is that dielectric layer etching forms side wall.
Fig. 8 is that p-type articulamentum is formed.
Fig. 9 is that silicide makes.
Figure 10 is that metal level is formed.
Figure 11 is fairlead and metal connecting layer formation.
Detailed description of the invention
The invention will be further described below in conjunction with the accompanying drawings.Following example are only used for clearly illustrating Technical scheme, and can not limit the scope of the invention with this.
As it is shown in figure 1, a kind of LDMOS device structure, including metal connecting layer 41, metal connecting layer 41 From surface, LDMOS device source electrode 24 is connected to substrate 11, and metal connecting layer 41 material is tungsten or copper, adopts With Ti/TiN as contact layer and barrier layer, raceway groove is concentration gradient raceway groove, and raceway groove is P-type channel, raceway groove High near source electrode 24 side concentration, a length of 90-250nm of grid of LDMOS device.
The manufacture method of a kind of LDMOS device structure, comprises the following steps:
Step 1, grid oxygen and grid deposit；
Step 2, after grid etching and N-type drift region are injected, at one layer of dielectric layer 34 ' of surface deposition, medium The thickness of layer 34 ' is 500-2000 angstrom, dielectric layer 34 ' step deposit step coverage > 90%, material is LPCVD SiO2 and or LPCVD SiN；
Step 3, autoregistration p-type is injected, and anneals and forms concentration gradient raceway groove；
Step 4, dense N-type is injected, and forms source electrode 24 and drain electrode 23；
Step 5, dielectric layer 34 ' etches, and forms side wall 34 in grid both sides；
Step 6, the dense P of autoregistration injects, and forms p-type articulamentum；
Step 7, silicide makes and faraday shield layer makes；
Step 8, dielectric layer 34 ' deposits and planarizes, and forms metal level 51；
After step 9, dielectric layer 34 ' fairlead and silicon via etch metal filled, respectively formed stem 42 With metal connecting layer 41；
Step 10, deposits on metal level 51 and etches, and forms metal electrode 61.
As shown in figs. 2-11, for the specific embodiment of manufacturing process；
Wherein, as in figure 2 it is shown, be p-type epitaxial layer 12 on substrate 11, on epitaxial layer 12, thermal oxide is raw Long one layer of gate oxide 31, gate oxide 31 deposits one layer of polysilicon, and chemical wet etching forms polysilicon gate 32.For reducing polysilicon gate 32 resistance, it is also possible to depositing polysilicon and silicide form gate electrode.
As it is shown on figure 3, polysilicon gate 32 deposits one layer of dielectric layer 34 ' after being formed, this dielectric layer 34 ' needs Having good step coverage, step coverage is more than 90%.
As shown in Figure 4, silicon chip surface injects phosphorus or arsenic, forms one layer of N-type layer 21 ', and implantation dosage is 5E11～5E12.
As it is shown in figure 5,23 regions that drain are blocked by photoresist 41, polysilicon gate 32 and dielectric layer 34 ' are made For autoregistration implant blocking layer, injecting B+, implantation dosage is 2E13-5E14, forms p-well 22 '.
As shown in Figure 6, at source electrode 24 and drain electrode 23 injection arsenic, dosage is 1E15-4E15, then anneals. P-well 22 ' and N-type layer 21 ' form p-well 22 and N-type drift region 21 after annealing respectively.
As it is shown in fig. 7, dielectric layer 34 ' etching forms side wall 34.
As shown in Figure 8,23rd district that drain are blocked by photoresist 41, and polysilicon 32 and side wall 34 are as from right Quasi-implant blocking layer, after injecting B+, short annealing forms p-type articulamentum 25.
As it is shown in figure 9, form silicide 33 at source electrode 24 and p-type articulamentum 25 surface.
As shown in Figure 10, field plate 35 makes, and deposits and planarize formation metal level 51
As shown in figure 11, fill after fairlead and silicon via etch, form stem 42 and metal connecting layer 41, general employing Ti/TiN, as contact layer and barrier layer, uses tungsten as metal filled.
Finally, metal level 51 deposit and etch formation metal electrode 61
The present invention deposits one layer of high dielectric layer of step coverage and stops as injecting after using etching polysilicon Layer, solves photoetching aligning accuracy problem, it is possible to achieve the autoregistration of below 0.25um grid length is injected；Simultaneously Using metal connecting layer that source electrode is connected to substrate from surface, metal connecting layer technique is carried out after device is formed, Such that it is able to the grid realizing below 0.25um are long, fine ratio of product and uniformity can be protected.
The above is only the preferred embodiment of the present invention, it is noted that common for the art For technical staff, on the premise of without departing from the technology of the present invention principle, it is also possible to make some improvement and change Shape, these improve and deformation also should be regarded as protection scope of the present invention.

Claims (6)

1. a LDMOS device structure, it is characterised in that: including metal connecting layer, described metal connects LDMOS device source electrode is connected to substrate by layer from surface, and the raceway groove of described LDMOS device is concentration gradient Raceway groove.
A kind of LDMOS device structure the most according to claim 1, it is characterised in that: described LDMOS The a length of 90-250nm of grid of device.
A kind of LDMOS device structure the most according to claim 1, it is characterised in that: metal connects Layer material is tungsten or copper.
A kind of LDMOS device structure the most according to claim 1, it is characterised in that: raceway groove is P Type raceway groove, raceway groove is high near source electrode side concentration.
5. manufacture method based on a kind of LDMOS device structure described in claim 1, it is characterised in that: Comprise the following steps,
Step 1, grid oxygen and grid deposit；
Step 2, after grid etching and N-type drift region are injected, at one layer of dielectric layer of surface deposition；
Step 3, autoregistration p-type is injected, and anneals and forms concentration gradient raceway groove；
Step 4, dense N-type is injected, and forms source electrode and drain electrode；
Step 5, dielectric layer etches, and forms side wall in grid both sides；
Step 6, the dense P of autoregistration injects, and forms p-type articulamentum；
Step 7, silicide makes and faraday shield layer makes；
Step 8, dielectric layer deposition and planarization, form metal level；
After step 9, dielectric layer fairlead and silicon via etch metal filled, form fairlead and metal respectively even Connect layer；
Step 10, deposits on the metal layer and etches, and forms metal electrode.
The most according to claim 5 based on a kind of LDMOS device structure described in claim 1 Manufacture method, it is characterised in that: the thickness of dielectric layer is 500-2000 angstrom, and dielectric layer step deposit step covers Lid rate > 90%, material is LPCVD SiO2 and or LPCVD SiN.
CN201610325621.6A 2016-05-17 2016-05-17 LDMOS device structure and manufacture method thereof Pending CN105845736A (en)

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PCT/CN2016/091817 WO2017197758A1 (en) 2016-05-17 2016-07-27 Ldmos device structure and manufacturing method thereof

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110379807A (en) * 2019-07-31 2019-10-25 厦门市三安集成电路有限公司 Microelectronic component and microelectronic component production method
CN110556402A (en) * 2018-06-01 2019-12-10 群创光电股份有限公司 Electronic device
CN112542444A (en) * 2020-12-03 2021-03-23 武汉新芯集成电路制造有限公司 Semiconductor device with a plurality of transistors
CN114497173A (en) * 2020-11-12 2022-05-13 苏州华太电子技术有限公司 Double-buried-channel RFLDMOS device applied to radio frequency power amplification
CN116169171A (en) * 2021-11-25 2023-05-26 苏州华太电子技术股份有限公司 SOI-LDMOS device and manufacturing method thereof

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CN104538441A (en) * 2014-07-03 2015-04-22 上海华虹宏力半导体制造有限公司 Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110556402A (en) * 2018-06-01 2019-12-10 群创光电股份有限公司 Electronic device
CN110556402B (en) * 2018-06-01 2022-04-12 群创光电股份有限公司 Electronic device
CN110379807A (en) * 2019-07-31 2019-10-25 厦门市三安集成电路有限公司 Microelectronic component and microelectronic component production method
CN110379807B (en) * 2019-07-31 2021-02-26 厦门市三安集成电路有限公司 Microelectronic device and method for manufacturing same
CN114497173A (en) * 2020-11-12 2022-05-13 苏州华太电子技术有限公司 Double-buried-channel RFLDMOS device applied to radio frequency power amplification
CN114497173B (en) * 2020-11-12 2023-10-31 苏州华太电子技术股份有限公司 Double-buried-channel RFLDMOS device applied to radio frequency power amplification
CN112542444A (en) * 2020-12-03 2021-03-23 武汉新芯集成电路制造有限公司 Semiconductor device with a plurality of transistors
CN116169171A (en) * 2021-11-25 2023-05-26 苏州华太电子技术股份有限公司 SOI-LDMOS device and manufacturing method thereof
CN116169171B (en) * 2021-11-25 2024-05-14 苏州华太电子技术股份有限公司 SOI-LDMOS device and manufacturing method thereof

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