CN103367444A

CN103367444A - Top drain ldmos

Info

Publication number: CN103367444A
Application number: CN2013100869027A
Authority: CN
Inventors: 雪克·玛力卡勒强斯瓦密; 陈军; 胡永中
Original assignee: Alpha and Omega Semiconductor Inc
Current assignee: Alpha and Omega Semiconductor Ltd; Alpha and Omega Semiconductor Inc
Priority date: 2012-03-30
Filing date: 2013-03-19
Publication date: 2013-10-23
Also published as: TWI493718B; TW201340327A

Abstract

This invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Description

The top-side drain Laterally Diffused Metal Oxide Semiconductor

Technical field

The present invention relates generally to semiconductor power device.More precisely, the invention relates to a kind of source electrode transverse diffusion metal oxide semiconductor field effect transistor (LDMOSFET) structure and preparation method thereof of the ground connection of reversing.

Background technology

Further reduce the traditional handicraft of the source inductance (comprising the source inductance in FET, MOSFET and the JFET device) of semiconductor power device, be subject to limitation and the challenge of many technical barriers.Especially, those skilled in the art will reduce the technical barrier that source inductance faces.Meanwhile, because increasing power device must have high efficiency, high-gain and high-frequency, the demand of source inductance that therefore reduces semiconductor power device is further strong.In general, by eliminating the combined leads in the semiconductor power device encapsulation, can reduce source inductance.Can attempt Semiconductor substrate is configured to source electrode, be used for connecting semiconductor power device, eliminate combined leads.Some difficult problems that exist in these methods come from typical vertical semiconductor power device connecting electrode are placed on the substrate.Vertical power device (trench-gate or planar gate DMOS device) is used as drain electrode with grid, electric current is from the source area that is arranged on the substrate top, flow to vertically downward the drain region that is arranged on the substrate bottom, in the device package process, the top source electrode needs combined leads to be used for being electrically connected usually, thereby has increased source inductance.

Original technology has proposed many lateral DMOSs with bottom source.Lateral dmos device structure contains a dark P+ decanting zone (injecting sedimentation or groove sedimentation) in source connection usually, in order to the top source electrode is connected to the P+ substrate, but the occupied area in decanting zone can produce very large cell pitch, perhaps dark P+ decanting zone is positioned at the structure cell outside, but this can produce higher source resistance.G. the people such as Cao has proposed the horizontal LDMOS device of a kind of bottom source in IEEE electronic device (1296-1303 page or leaf) " comparative study of drift region design among a RF LDMOSFET " literary composition in August, 2004, shown in Figure 1A, this horizontal LDMOS device comprises a dark sinker that spreads in source connection.

The people such as Ishiwaka O in the 1-12 month 4 in December, 1985 in international electronic device meeting that Washington, DC is held---in " connecting the source inductance that reduces 2.45GHz power Ld-MOSFET by the V-groove " literary composition of delivering in the technical digest (166-169 page or leaf), a kind of laterally two-diffusion MOS field-effect transistor (LD-MOSFET) with the connection of V-groove has been proposed, for reducing source inductance, gate leakage capacitance and passage length.The V-groove runs through P-type epitaxial loayer, touches P+ type substrate, is formed in the SiO2 district, near the active area outside.The N+ type source area of LD-MOSFET is direct-connected to the V-groove with metal, thereby has eliminated the combined leads of source electrode.

United States Patent (USP) 6,372 Leong) has proposed the horizontal LDMOS device of a kind of bottom source at 557(2002 April 16, at the interface place of P+ and P-epitaxial loayer, attempts using a buried layer, reduces horizontal proliferation, thereby reduces cell pitch.United States Patent (USP) 5,821,144(1998 October 13, the people such as D ' Anna) and United States Patent (USP) 5,869,875(1999 February 9, Hebert) lateral dmos device structure has been proposed also, this device contains a dark decanting zone (is injected sedimentation or groove sedimentation) in the outer peripheral areas of structure, to reduce cell pitch.

Yet, device in these specifications all is to use an independent metal, rather than source/body contact zone and grid cover district, independent metal very thick (3um or thicker), this thickness will make source metal become higher to the electric capacity of N-drift drain electrode, produce larger stress at grid, and also become larger to the distance of drain metal, thereby increased cell pitch.On the other hand, part of devices is that the source/body contact zone uses the first metal, for using the second metal in the drain and gate blind zone; then make the first metal thinner; therefore can twine grid, the protection grid is not subjected to the impact of low electric capacity and little stress, and can not affect cell pitch.Yet, use two metals just to need two extra masks---one is used for through hole, one and is used for top metal, thereby has increased cost.This structure spreads downwards by the top, usually form the P+ sinker, because the horizontal proliferation for the dark sinker that the top source electrode is connected to the heavy doping substrate downwards is more remarkable, therefore causes cell pitch larger, thereby has increased the overall dimensions of structure cell on horizontal plane.Conducting resistance is the function of resistance and device area, so the cell pitch conference also increases conducting resistance.The device size that large cell pitch causes increases and package dimension increases, and also can increase the cost of device.In addition, the cell pitch that reduces the bottom of these original technology-source electrode device can make the electric property of device produce drift.For example, to spread sinker (P+ of doping) near the source electrode limit of grid shown in Figure 1A, can produce higher threshold voltage, its reason is that the p+ sinker of diffusion is used for the top source electrode is connected to base substrate, and the channel region below the grid is occupied in its horizontal proliferation meeting, channel region also is the p-type, increased the doping content in the passage, thereby threshold voltage raise, this be we do not wish the result that sees.

Patent 7,554,154 have proposed a kind of modified form counter-rotating ground connection-source electrode FET on heavy doping substrate (for example heavy doping P+ substrate), as shown in Figure 1B, are used for reducing cell pitch with self aligned body-source connection.Modified form FET comprises an integrated body-source shorted structure, i.e. P+ sinker, and part place lower below passage is towards drain diffusion.The P+ sinker extends below surface channel, extends with the compensation drain electrode and mixes, thereby reduce Cgd, reduces cell pitch.In addition, suitably regulate the doping content of accumulation area, make the Cgd*Rdson image of peak value minimum.Rely on this top-side drain LDMOS structure, be body-embedded grid shielding of source connection configuration, to reduce gate leakage capacitance Cgd, the device structure cell is arranged in the enclosed construction, can further reduce the required exceptional space of termination.Yet for the dark P+ sinker that the top source electrode is connected to downwards on the heavy doping substrate, its significant horizontal proliferation has occupied larger space, can't further reduce and reduce cell pitch.

Therefore, extremely be necessary to propose a kind of new device structure and new preparation process of power semiconductor, thereby solve above-mentioned difficulties and limitation.

Summary of the invention

Therefore, one aspect of the present invention is, proposed a kind of top of novel, improvement-drain electrode laterally diffused MOS (TD-LDMOS) semiconductor power device, interconnects with groove source electrode-body, begin to pass this tagma from end face, extend downwardly into the bottom source electrode.The cell pitch of device architecture is very little, has reduced the wafer cost, thereby has solved above-mentioned technical barrier and limitation.

Exactly, one aspect of the present invention is, a kind of top-side drain laterally diffused MOS (TD-LDMOS) semiconductor power device of improvement has been proposed, with the groove source electrode of base substrate source connection-body interconnection, thereby significantly reduce source inductance, make power device obtain high efficiency, high-gain and high frequency of utilization.

Another aspect of the present invention is, a kind of top-side drain laterally diffused MOS (TD-LDMOS) semiconductor power device of improvement has been proposed, with groove source electrode-body interconnection, begin to pass this tagma from end face, extend downwardly into the bottom source electrode, with a narrow opening and high aspect ratio, thereby significantly reduce cell pitch and to the demand of mask, further reduce the preparation cost of high-quality reliable semiconductor power device.

Another aspect of the present invention is, a kind of top-side drain laterally diffused MOS (TD-LDMOS) semiconductor power device of improvement has been proposed, with groove source electrode-body interconnection, begin to pass this tagma from end face, extend downwardly into the bottom source electrode, with the groove of useful SEG P++ or SEG P++ SiGe or metal filled Material Filling.This groove is also surrounded by the P++ lining injection region below the trench bottom surfaces, around trenched side-wall, reduces that further body and the interconnection resistance between the source electrode on the bottom surface being set.

Another aspect of the present invention is, a kind of top-side drain laterally diffused MOS (TD-LDMOS) semiconductor power device of improvement has been proposed, with groove source electrode-body interconnection, begin to pass this tagma from end face, extend downwardly into the bottom source electrode, wherein insulating barrier and the end face in this tagma of formed grid cover Ti/TiN layer and self aligned polycide layer cover gate insulating barrier top, thus gate leakage capacitance further reduced.Therefore, the device described in the present invention is sturdy and durable, highly reliable, and this device architecture is fit to be applied in high pressure and the low-voltage device more.

A preferred embodiment of the present invention has mainly proposed a kind of top-side drain lateral diffused metal oxide field-effect semiconductor (TD-LDMOS) device that is formed on the Semiconductor substrate.This top-side drain LDMOS comprises a source electrode, is formed on the bottom surface of Semiconductor substrate.This top-side drain LDMOS also comprises a source electrode and drain region, be arranged on two opposite side of planar gate, planar gate is arranged on the end face of Semiconductor substrate, wherein source area is enclosed in this tagma, consist of drift region, between the source area and drain region below the planar gate, as a transverse current passage.This top-side drain LDMOS also comprises the groove that at least one is filled with electric conducting material, near this tagma the end face, extends vertically downward, in order to electrically contact the source electrode that is arranged on the Semiconductor substrate bottom surface.

In addition, the present invention proposes a kind of method for preparing semiconductor power device in Semiconductor substrate.The method comprises: 1) this tagma of preparation, surround source area and drain region, and grid is used for the transverse current path in this tagma between near the source area of control substrate end face and the drain region on the end face of Semiconductor substrate; 2) get through groove, begin to extend downwardly into the source electrode on the substrate bottom surface from this tagma, and use the electric conducting material filling groove, as body-source electrode interconnection.In one embodiment, the step with the electric conducting material filling groove comprises that usefulness contains the electric conducting material filling groove of silicon selective epitaxial growth (SEG) or SiGe (SiGe) SEG.In another embodiment, the method also is included in around channel bottom below and the trenched side-wall, injects the heavy doping linear zone.

Read following describe in detail and with reference to after the accompanying drawing, these and other characteristics and advantages of the present invention, for a person skilled in the art, undoubtedly will be apparent.

Description of drawings

Figure 1A represents the profile with the traditional laterally diffused MOS of bottom source (LDMOS) device for the RF base station.

The profile of a kind of bottom source LDMOS with spreading the decanting zone has been proposed in the described patent of Figure 1B table.

Fig. 2 A represents according to one embodiment of the present of invention, with the profile of the top-side drain LDMOS device of groove body-source shorted structure.

Fig. 2 B is illustrated in the profile of the whole top-side drain LDMOS device structure cell of arranging in the closed cell configuration.

Fig. 2 C is illustrated in the vertical view of the whole top-side drain LDMOS device structure cell of arranging in the closed cell configuration.

Fig. 3 represents according to an alternative embodiment of the invention, the profile of another top-side drain LDMOS device.

Fig. 4 A to 4L represents a series of profiles for the preparation of the preparation technology of top-side drain LDMOS device of the present invention.

Embodiment

Referring to Fig. 2 A, of the present invention with top-side drain and bottom source the counter-rotating top-drain electrode of N-passage and the profile of the plough groove type FET device of ground connection-source electrode.Counter-rotating top-grounded drain-source electrode N-passage FET device is positioned on the P+ substrate 105, as the bottom source electrode.Also can select, the P-passage device is formed on N+ silicon (Si) substrate top.P-epitaxial loayer 110 is positioned at substrate 105 tops.For the active cell region of substrate arrangement and termination area, usually be arranged on the substrate periphery.Get through the deep trench 120 of high aspect ratio, pass epitaxial loayer 110, extend downwardly into substrate 105.Selective epitaxial growth (SEG) silicon or SEG SiGe (SiGe) weigh P doping P++, fill deep trench 120, consist of self aligned source/body joint, as the local interconnect of super-low resistance, from the source electrode to the body and substrate.In order to improve joint, in groove, to fill before the P++ conductive trench packing material, the linear injection region 128 of preparation P++ is injected into the P++ of angle around the sidewall of the following and source electrode-body interconnection channel 120 of channel bottom.This tagma 115 is formed on epitaxial loayer 110 tops, and epitaxial loayer 110 extends transverse to drain electrode drift region 125.P-alloy in this tagma 115 surrounds the part N-alloy in the transistor accumulation, to be fit to the alloy structure of N-drift region 125, makes gate leakage capacitance minimum, keeps simultaneously lower drain-source resistance Rdson.Deep trench source-body interconnection 120 also extends to vertically downward bottom P+ substrate 105, extends up to this tagma 115.The end face place of this tagma 115 of part below gate oxide 135 forms a passage.Deep trench source-body interconnection 120 has a narrow opening and high aspect ratio, need not the decanting zone in order to reduce cell pitch, extends with horizontal proliferation because form the decanting zone, the decanting zone could be extended to the larger degree of depth, touches bottom source polar region 105.

Storehouse planar gate 140 is arranged on grid oxic horizon 135 tops, grid pad 165 surrounds storehouse planar gate 140, grid cover metal 170-G covers storehouse planar gate 140, and grid oxic horizon 135 is formed on the end face between source area 160 and the drain electrode drift region 125.Therefore, the electric current between grid 140 control source areas 10 and the drain electrode drift region 125 passes the passage that this tagma 115 consists of, below grid 140, as the lateral MOS device.Drain electrode drift region 125 is arranged on field oxide 130 belows, and bpsg layer 180 and passivation layer 185(are optional) covering field oxide 130.By passivation layer 185 and bpsg layer 180, etching drain electrode contact openings makes top-side drain metal 199 by contact N+ doped region 190, and contact drain region 125 is to reduce contact resistance.As shown in the figure, can utilize diverse ways to prepare stacked gate 140, below stacked gate 140 with oxide 130 and 135.The method comprises growth or deposition oxide, and at the channel region etching oxide, or utilizes the oxidation technology of LOCOS type.Stacked gate 140 has long grid length and the field plate above the drain electrode extension, and does not increase cell pitch.The path of stacked gate 140 control electric currents between the drain electrode below passage and gate oxide 135 and the field oxide 130 has lower gate leakage capacitance.Insulation spacer 165 and buried gate shielding 170-G surround stacked gate 140; stacked gate 140 also comprises the self aligned polycide part 170-S for body-source connection; in order to further reduce gate leakage capacitance Cgd, grid cover layer 170-G protection covers the drain metal 199 of top face.In order to obtain preferably machinery and electric property, the linear barrier layer 198 of Ti/TiN also is formed between drain contact region 190 and the drain metal 199.Since interconnection trench 120 usefulness selective epitaxial growth (SEG) P++ Si or SEG P++ SiGe, thus do not need the sedimentation diffusion, and therefore formed autoregistration source electrode-body interconnection makes the spacing of structure cell significantly reduce half.

Fig. 2 B represents that the whole structure cell of top-side drain LDMOS device of the present invention is arranged in a profile in the closed cell configuration.Shown in Fig. 2 B, because the source electrode ground connection all in half cell pitch needn't provide additional space for the termination area of top-side drain LDMOS device, thereby save the space.Fig. 2 C represents that the whole structure cell of top-side drain LDMOS device of the present invention is arranged in a vertical view in the closed cell configuration.

Fig. 3 represents another embodiment with the similar top-side drain LDMOS of device shown in Figure 2 device.Unique difference is that device is formed on the heavy doping N++ substrate 101, has significantly reduced series resistance.P+ epitaxial loayer 105 is formed on N++ substrate 101 tops, and is shorted to the N++ substrate as the bottom source electrode, has reduced the resistance of substrate.In addition, also can select dark resilient coating 115 to be formed on predefine depths in the P-epitaxial loayer 110, above P+ source layer 105, in order to regulate puncture voltage (BV), and utilize thermal cycle required among the preparation technology, stop the lower break-through in surface.In the present embodiment, get through deep trench 120, pass P-epitaxial loayer 110 and P+ source layer 105, extend downwardly into N++ substrate 101.Shown in Fig. 2 A, deep trench 120 has very high aspect ratio, and fills deep trench 120 with the P++ electric conducting material that the heavy P such as selective epitaxial growth (SEG) silicon or SEG SiGe (SiGe) mixes.Also can select, with metal filled deep trench 120 such as P++ polysilicon or tungsten, clad lining 129(is self aligned polycide for example) between drain electrode and source electrode, form the local interconnect of super-low resistance.In this device architecture, can ignore passivation layer 185.

Fig. 4 A to 4L represents a series of profiles for the preparation of the preparation method of the device architecture shown in Fig. 2 A and 3.By preparation technology's explanation, be appreciated that and utilize self-alignment structure that this technique only needs 6 mask step.Shown in Fig. 4 A, technique is from initial silicon substrate, and silicon substrate comprises that with boron doped P+ substrate 205, its resistivity is 3 to 5 mOhm-cm or lower.Substrate 205 is preferably along＜100〉crystal orientation, as the inceptive direction of standard.P-epitaxial loayer 210 is formed on the substrate 205, and thickness is 2 to 7 microns, and the dosage with 5E14 to 5E15 mixes usually, is used for the 20-60V device.In another embodiment, epitaxial loayer 210 can be the N-doped layer.

In Fig. 4 B, the cushion oxide layer 212 of growing is used for follow-up nitride technique is set.An optional treatment step is: under the Implantation Energy of 600KEV, implantation dosage with 1E14 injects dark resilient coating comprehensively, so that the dark resilient coating 215 of preparation in subsequent technique, be used for regulating puncture voltage (BV), and the sub-surface break-through between the prevention N-drift layer, when carrying out follow-up preparation technology, owing to need thermal cycle, therefore also to prepare P+ substrate 205.Comprehensively to inject can be lightly doped to P, mixes to increase P-, avoids break-through, perhaps for the N-epitaxial loayer, use be that lightly doped N-injects.

Above cushion oxide layer 212, carry out nitride deposition, then utilize active mask, the first mask (not expressing among the figure) to carry out etching, with the protection channel district, in subsequent technique, make the drain electrode extension area exposed out.When tilt angle of zero, in not by the zone of protecting nitride, carry out the N-drift and inject, make N-drift region 225, shown in Fig. 4 C.Can be in 60Kev to the 200Kev scope by Implantation Energy, dosage prepares N-drift region 225 from the phosphorus of 5E11 to 2E13, and in the practical application, dosage suitable under the 30V is 3E12.This step can in the drift drain electrode extension, regional 225 of LDMOS device, form self aligned n-type drift and inject (for NMOS).Then utilize the field oxidation technology (being called LOCOS) of standard, optional N2 drives technique, forms field oxide region 230 above N-drift region 225.Temperature is in 900 to 1100C scope, and growth thickness is 0.3 to 1 micron oxide, and suitable thickness is about 0.55 micron.

Peel off nitride (not expressing among the figure) and pad oxide 212, the sacrificial oxide layer and peel off (not expressing among the figure) of then growing is to clean the surface of this structure.In Fig. 4 D, then the grid oxic horizon 235 of growing deposits a polysilicon layer, and perhaps optimum situation is multicrystalline silicon compounds layer 240, and thickness reaches 2000 to 6000 dusts, to form grid.Subsequently, N+ is mixed Implantation to polysilicon layer, also can select to prepare up a WSix layer, with the very low contact layer of preparation resistance.Notice that polysilicon can be in-situ doped, perhaps also can utilize phosphorus oxychloride (POCl3) to mix.Utilize high-temperature oxydation (HTO) or low-temperature oxidation (LTO) technique, carry out oxidation cover deposition, thereby above polysilicon layer 240, deposit an oxidation cover layer 245.Above polysilicon layer 240, the thickness of oxidation cover layer 245 is about 500 to 4500 dusts.Utilize gate mask (i.e. the second mask (not expressing among the figure)) etching, and form the pattern of oxidation cover layer 245 and grid layer 240.At first carry out oxide etching, form the pattern of oxidation cover layer 245, then carry out polysilicon or multicrystalline silicon compounds etching.As shown in the figure, polysilicon or multicrystalline silicon compounds etching terminate in grid oxic horizon 235 and field oxide 230 tops.

In Fig. 4 E, carry out comprehensive shallow body high angle B Implanted (high angle is injected in order to introduce passage below grid), dosage range is between 1E12 to 1E14, and optimum dosage is 1E13, this tagma 250 of preparation P-.Also can select, under the body of zero angle and higher-energy injects, carry out comprehensive shallow body and inject, with this tagma 250 of preparation P-.Rely on the stack architecture of field oxide 230, grid 240 and oxidation cover 245, the boron ion only is injected in the source electrode edge of grid.Then, in 950 to 1150 degrees centigrade high temperature range (optimum temperature is 1050 degrees centigrade), carried out ontology-driven about 60 minutes.In Fig. 4 F, carry out comprehensive shallow-source electrode-injection, be (optimum dosage is 4E15) between the 1E15 to 1E16 at dosage range for example, inject As doping ion, with preparation N+ source area 260.Then, in 850 to 1000 degrees centigrade high temperature range (optimum temperature is 950 degrees centigrade), carried out the source electrode annealing operation about 30 minutes.In the source electrode annealing process, according to stack, can use partial oxidation, thereby form the polysilicon oxide sidewall at the edge of stacked gate 240.

In Fig. 4 G, deposition pad oxide layer 265, best conformal oxide layers, thickness range is 1000 to 4000 dusts, is preferably in more than 3000 dusts, as thick mask, be used for the body etching groove, (SEG) provides insulation for selective epitaxial growth, also in follow-up preparation technology, provides the passivation gate lateral wall.Then, utilize source electrode-body local interconnect trench mask (i.e. the 3rd mask (not expressing among the figure)), carry out oxide etching and silicon etching, get through groove 255, make groove 255 have a narrow opening and high aspect ratio, gash depth is to downward-extension, to touch P+ substrate 205.Then, remove photoresist (not expressing among the figure).Under 7 ° of inclination implant angles, can select to carry out comprehensive P++ and inject, inject heavy doping P++ at channel bottom and trenched side-wall (not expressing among the figure), thereby form lining injection region 258, be used for better contact.In Fig. 4 H, carry out selective epitaxy growth (SEG) Si or SiGe with heavy doping P++, the SEG SiGe of the P++ boron that preferably mixes from source electrode 260 to body layer 250 and dark resilient coating 215, and to substrate 205, forms the local interconnect 220 of super-low resistance.In Fig. 4 I, by reactive ion etching (RIE), carry out the oxide spacer etching, form grid pad 265, by the overetch of minimum, to the passivation gate lateral wall, to guarantee keeping

oxide

230 and 245 on polysilicon gate 240 belows and the drain electrode extension.

In Fig. 4 J, carry out slight wet oxygen compound etching, remove the oxide of N+ source area 260 tops.Then, depositing Ti or Co on the end face of silicon form Ti or Co layer 275 '.Then, utilize the first rapid thermal annealing (RTA) technique, carry out the first self aligned polycide preparation technology, thereby on the end face of the silicon above the oxide layer 265,245 and 230 and Ti/TiN layer 275, form TiSi or CoSi layer 275 '.Utilize grid cover mask (i.e. the 4th mask (not expressing among the figure)), and the erosion of Ti/TiN wet etching, proceed technique, with preparation grid cover 275.If do not need grid cover, so just do not need this mask yet.Then, by RTA, remove photoresist, utilize the preparation of the second self aligned polycide, on the end face of silicon, form TiSi2 or CoSi2 layer 275 '.The autoregistration body of silicification technics preparation-source electrode interconnection has good joint, very low resistance, and good grid cover metal, and good insulation is provided.

In Fig. 4 K, deposition contains the ILD0 material of oxide, nitride or oxidation-nitride, form insulating barrier 280, then utilize a drain and gate mask (i.e. the 5th mask (not expressing among the figure)), get through gate contact opening (not expressing among the figure) and the drain electrode contact openings 285 of insulating barrier 280 tops.Under the implantation dosage of phosphonium ion in 5E14 to 1E16 scope, carry out the low energy contact and inject, form low resistance contact district 290, then in 700-900 degree centigrade N2, carry out annealing process (preferably utilizing RTA), continue 20 seconds to 5 minutes (preferably 1 minute).In Fig. 4 L, by the thick metal deposition with the Ti/TiN lining, form the drain metal 295 with barrier metal layer 298.Then, utilize metal mask (i.e. the 6th mask (not expressing among the figure)), carry out metal etch, thereby form gate metal and drain metal at end face, then remove photoresist, cleaning is clean, carries out at last alloy technique, finishes preparation process.

In the embodiment that another is not expressed, from heavy doping N++ silicon substrate, form a P+ source electrode epitaxial loayer at the N++ substrate, then on P+ source electrode epitaxial loayer, the P-epitaxial loayer of growing.Following steps are removed groove 255 and are extended through P-epitaxial loayer and P+ source electrode epitaxial loayer downwards, touch outside the N++ substrate, and other are all similar with the processing step shown in Fig. 4 B-4K.

The above-mentioned device architecture of foundation owing to used little wafer, interconnects with the groove source-body, and does not have the horizontal proliferation of sedimentation contact zone, has reduced cell pitch, thereby has obtained lower effective wafer cost, has reduced preparation cost.The cost of this part reduction can the high preparation cost of compensate for slower.The more important thing is, use the substrate source connection, dispose simultaneously by the cingens source electrode in P++ lining injection region-body interconnection structure, make source resistance reach minimum, obtained very low source inductance.In addition, the little spacing of device has also reduced conduction resistance (Rsp) under the assigned work voltage as mentioned above.This device architecture can be adjusted easily, makes its design and operation need be applicable to high pressure and the interior device of low pressure range.

Therefore, the top-side drain LDMOS device with counter-rotating ground connection-source electrode allows vertical current to pass vertical channel as mentioned above, has disposed the controlled drift length of the drift region of vertical channel, so that can prepare cell pitch small, that can survey.Rely on the source connection of channel bottom directly to contact with the heavy doping substrate, reduced source resistance.Therefore, no longer as traditional bottom source FET device, must configuration dark resistance decanting zone or ditch trough connection.

Claims

1. top-side drain lateral diffused metal oxide field-effect semiconductor TD-LDMOS device that is formed on the Semiconductor substrate comprises:

A source electrode is arranged on the bottom surface of Semiconductor substrate;

A source area and a drain region are arranged on two opposite side of the planar gate on the end face of Semiconductor substrate, and wherein source area is enclosed in this tagma, and this tagma is between the source area and drain region below the planar gate, as the transverse current passage; And

At least one groove is filled with electric conducting material, and begins to extend vertically downward near this tagma the end face of Semiconductor substrate, electrically contacts with the source electrode that is arranged on the Semiconductor substrate bottom surface.

2. top-side drain LDMOS device claimed in claim 1, wherein:

Semiconductor substrate comprises a P+ substrate that is carrying the P epitaxial loayer, consists of source electrode and the drain region of N-type alloy near the end face of Semiconductor substrate.

3. claim 1 and 2 described top-side drain LDMOS devices, wherein:

The groove of filling with electric conducting material comprises selective epitaxial growth SEG silicon or SEG SiGe SiGe.

4. top-side drain LDMOS device claimed in claim 1 also comprises:

A heavy doping lining injection region is arranged on around channel bottom below and the trenched side-wall.

5. top-side drain LDMOS device claimed in claim 2 also comprises:

A P++ lining injection region is arranged on around channel bottom below and the trenched side-wall.

6. top-side drain LDMOS device claimed in claim 1, wherein:

With metal filled groove, metal is as the electric conducting material in the groove.

7. top-side drain LDMOS device claimed in claim 7, wherein:

With the groove that tungsten is filled, tungsten is as the electric conducting material in the groove.

8. top-side drain LDMOS device claimed in claim 7, wherein:

Groove also comprises a metal liner nexine, is formed on the bottom surface of groove.

9. top-side drain LDMOS device claimed in claim 1, wherein:

Groove is narrow, deep trench, and the degree of depth and Width are very high, from 10 to 25.

10. top-side drain LDMOS device claimed in claim 1, wherein:

Top-side drain LDMOS cell configuration is become closed cell layout.

11. top-side drain LDMOS device claimed in claim 1, wherein:

Semiconductor substrate also comprises a heavily doped layer, the conductivity type opposite in its conduction type and this tagma.

12. top-side drain LDMOS device claimed in claim 1, wherein:

Semiconductor substrate also comprises the dark resilient coating of a dopant implant thing, and the conduction type of alloy is identical with the conduction type of semiconductor region.

13. top-side drain LDMOS device claimed in claim 1, wherein:

Top-side drain LDMOS comprises a P-passage device, is formed in the N+Si substrate.

14. top-side drain LDMOS device claimed in claim 1, wherein:

Planar gate also comprises a stacking-type planar gate, and the below is lined with grid oxic horizon, is covered by the grid cover oxide, is also surrounded by the sidewall pad lamella.

15. the described top-side drain LDMOS of claim 14 device also comprises:

A grid cover layer that is consisted of by metal level, cover grid cover oxide and sidewall pad lamella top, wherein the grid cover layer also extends to the end face of source area top, is processed into the self aligned polycide layer, is used for conduction boundary between source area and top metal source electrode.

16. a semiconductor power device comprises:

A grid is arranged on the end face of Semiconductor substrate, is used for the current path between control source area and the drain region, and source area and drain region are arranged near the end face of substrate; And

A groove of filling with electric conducting material to downward-extension, is used for source area is shorted to the source electrode that is arranged on the substrate bottom surface.

17. one kind prepares the method for semiconductor power device in Semiconductor substrate, comprising:

Prepare this tagma and a drain region that surrounds source area, on the end face of Semiconductor substrate, with grid, be used near the source area of control Semiconductor substrate end face and the transverse current path in this tagma between the drain region; And

Get through groove, begin to extend downwardly into the source electrode on the Semiconductor substrate bottom surface from this tagma, and use the electric conducting material filling groove, as body-source electrode interconnection.

18. the described method of claim 18, wherein:

Step with the electric conducting material filling groove comprises, with the electric conducting material filling groove that contains selective epitaxial growth SEG silicon or SEG SiGe SiGe.

19. the described method of claim 18 also comprises:

Below the channel bottom and around the trenched side-wall, inject heavy doping lining district.