CN115458591A - SIC semiconductor power device with low on-resistance and low switching loss - Google Patents

SIC semiconductor power device with low on-resistance and low switching loss Download PDF

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CN115458591A
CN115458591A CN202211018776.7A CN202211018776A CN115458591A CN 115458591 A CN115458591 A CN 115458591A CN 202211018776 A CN202211018776 A CN 202211018776A CN 115458591 A CN115458591 A CN 115458591A
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trench
region
conductivity type
layer
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徐琳
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Shenzhen Dipu Electronics Co ltd
Nami Semiconductor Co ltd
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Shenzhen Dipu Electronics Co ltd
Nami Semiconductor Co ltd
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Abstract

A SiC trench MOSFET having first and second types of gate trenches for forming a gate electrode and a grounded P shield region located below the gate electrode for use as a gate oxide electric field reduction region is disclosed. The grid electrode is positioned in the first type grid groove with the thick oxidation layer at the bottom, and the grounding P shielding area surrounds the second type grid groove which is completely filled by the thick oxidation layer and is connected to the source metal through the grounding P area. The device further includes a current spreading layer surrounding the first type gate trench to reduce on-resistance.

Description

SIC semiconductor power device with low on-resistance and low switching loss
Technical Field
The present invention relates generally to semiconductor power devices and, more particularly, to a silicon carbide (SiC) trench MOSFET (metal oxide semiconductor field effect transistor) having first and second types of gate trench structures for forming a gate and a grounded P-shield region (PS) that serves as a gate oxide electric field reduction region (GOER). The device further includes a current spreading layer surrounding the first type gate trench under the body region to achieve lower gate oxide electric field strength, lower on-resistance, smaller gate-to-drain charge (Qgd), and lower switching loss.
Background
Due to the physical properties of SiC, siC-MOSFETs have higher breakdown voltages, lower on-resistances and faster switching speeds than Si-MOSFETs. However, siC-MOSFETs require a higher Vgs to fully open the channel of the device due to the poor interface state between SiC and gate oxide, and therefore have higher gate oxide electric field strength than Si-MOSFETs. For example, vgs =10V can fully open the device channel for Si devices, but Vgs =18V can fully open the device channel for SiC devices. The higher the Vgs, the higher the gate oxide field strength, leading to reliability issues.
Another problem is that the gate oxide layer grown at the bottom of the trench of the SiC device, as shown in fig. 1, is much thinner (by about 3-5 times) than the trench sidewalls, which not only results in a larger Qgd, but also greatly increases the electric field strength of the gate oxide layer at the bottom of the trench. The device structure shown in fig. 1 is similar to a conventional Si trench MOSFET, except that N + SiC substrate 101 and SiC epitaxial layer 102 have N + source regions 111 and P body regions 110. A gate trench 103 filling the gate electrode 105 is formed in the epitaxial layer 102, and the trench sidewalls and trench bottom of the gate trench 103 are thermally oxidized to grow gate oxide layers 109 and 106, respectively. The oxidation rate at the bottom of the trench of the Si face is the lowest in the SiC crystal face, so that the thickness of the gate oxide layer 106 is thinner than 109.
Therefore, in the field of designing and manufacturing semiconductor devices, especially in the field of designing and manufacturing SiC trench MOSFETs, there is still a need to provide a novel cell structure, device structure and manufacturing method that can solve the above-mentioned difficulties and limitations, so that the SiC trench MOSFET has a lower gate oxide electric field strength, achieves a lower on-resistance, a smaller Qgd and a lower switching loss.
Disclosure of Invention
The invention discloses a novel SiC trench MOSFET, which is provided with a first type gate trench and a second type gate trench, and a grounding P shielding region (PS) used as a gate oxide electric field reduction region, wherein the gate is positioned in the first type gate trench, the bottom of the first type gate trench is provided with a thick oxide layer, the grounding PS region surrounds the second type gate trench completely filled by the thick oxide layer, and is connected with a body region and a source metal through at least one grounding P region (GP). Since the second-type gate trench has a narrower trench width than the first-type gate trench, the PS region can be designed to have a narrower width than the first-type gate trench. Therefore, the pinch-off effect between two adjacent PS regions is reduced, thereby reducing the on-resistance. The device further comprises a Current Spreading Layer (CSL) surrounding the first type gate trench and positioned below the body region to further avoid a pinch-off effect between two adjacent PS regions so as to further reduce the on-resistance, wherein the doping concentration (Ncs) of the CSL is higher than that of the epitaxial layer (Nepi). Due to the existence of the thick bottom oxide layer of the device, compared with the traditional SiC MOSFET, the SiC MOSFET of the invention has smaller Qgd and can further reduce the switching loss.
In one aspect of the invention, a SiC power device is disclosed comprising a plurality of cells, wherein each cell is located within an active region, further comprising: an epitaxial layer having a first conductivity type and located over the substrate; at least one stripe-shaped gate trench surrounded by a source region having a first conductivity type, the source region being located in a body region having a second conductivity type and being close to an upper surface of the epitaxial layer; each strip-shaped gate trench comprises a first type gate trench and a second type gate trench; the first type gate groove is positioned above the second type gate groove, and the width of the first type gate groove is larger than that of the second type gate groove; the grid electrode is positioned in the first type grid groove and is surrounded by the first insulating layer positioned at the bottom of the first type grid groove and the second insulating layer positioned on the side wall of the first type grid groove; the first insulating layer has a thickness greater than the second insulating layer. A P shield region (PS) serving as a gate oxide electric field reduction region having the second conductivity type and surrounding the second-type gate trench, wherein the second-type gate trench is completely filled with the first insulating layer; at least one ground P region (GP) having a second conductivity type, surrounding sidewalls and a bottom of the first-type gate trench, and connecting the body region and the PS region; and a body region and a source region connected to the source metal through a plurality of source contact regions. Thus, the PS region and the source metal are grounded through the grounded GP region.
According to another aspect of the invention, in some preferred embodiments, the substrate has a first conductivity type. In other preferred embodiments, the substrate has a first conductivity type, and further comprising: a PS region having the second conductivity type is used as a gate oxide electric field reduction region adjacent to a lower surface of the body region and adjacent to the stripe-shaped gate trench. In other preferred embodiments, the device further comprises a super junction structure including a P-pillar region of the second conductivity type over the substrate.
According to another aspect of the invention, in some preferred embodiments, the substrate is of said first conductivity type and the epitaxial layer is a single epitaxial layer having a uniform doping concentration. In other preferred embodiments, the substrate has a first conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the trench semiconductor power device further includes a buffer layer with the first conductivity type and a resistivity of Rn, the buffer layer is located between the substrate and the epitaxial layer, where R > Rn. In other preferred embodiments, the substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and the trench type semiconductor power device further includes a buffer layer with the first conductivity type and resistivity Rn, the buffer layer is located between the substrate and the epitaxial layer, where R > Rn.
According to another aspect of the invention, in some preferred embodiments, the substrate has a second conductivity type, and further comprising: a buffer layer of a first conductivity type and located between the substrate and the epitaxial layer; and a plurality of heavily doped regions of the first conductivity type located in the substrate, forming a plurality of alternating P + regions and N + regions.
In accordance with another aspect of the present invention, there is also disclosed a SiC power device further comprising, a Current Spreading Layer (CSL) of a first conductivity type surrounding at least trench sidewalls of the first-type gate trench located in the active region, wherein the CSL is doped at a higher concentration than the epitaxial layer.
According to another aspect of the present invention, in some preferred embodiments, the P-pillar region of the super junction structure may be formed by a multi-epitaxy method. In other preferred embodiments, the P-pillar region of the super-junction structure may be formed by filling the deep trench with an epitaxial layer having the second conductivity type.
The invention also discloses a method for manufacturing the SiC power device, which comprises the following steps: growing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is lower than that of the substrate; forming a first type and a second type gate trench by performing the steps of:
(a) Forming a trench mask on the upper surface of the epitaxial layer for defining a plurality of first type gate trenches;
(b) Forming a first type gate trench in the epitaxial layer by etching the open region in the trench mask;
(c) Forming a dielectric layer on the side wall and the bottom of the first type gate groove;
(d) Removing the bottom of the first type gate trench by anisotropic etching;
(e) And carrying out anisotropic silicon etching to form a plurality of second-type gate trenches.
According to another aspect of the invention, in some preferred embodiments, the method for manufacturing a trench semiconductor power device further comprises the steps of: and performing angle ion implantation to implant second conductivity type dopants into the side walls and the bottom of the second-type gate trenches to form second conductivity type doped regions around the second-type gate trenches.
According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: a zero degree ion implantation of a second conductivity type dopant is performed.
According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: depositing a BSG layer into the trench after step (e) to form a second conductivity-type doped region surrounding a lower portion of the trench.
According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of: and forming a grounding P region (GP) mask, and injecting the second conductive type dopant into the side wall and the bottom of the first type gate groove by adopting a wet dielectric layer etching method and the angle ion implantation of the second conductive type dopant to form a second conductive type doped region surrounding the first type gate groove.
According to another aspect of the invention, in some preferred embodiments, a method for manufacturing a trench semiconductor power device further comprises the steps of:
(f) Removing the dielectric layer;
(g) Forming a first insulating layer along inner surfaces of the first-type and second-type gate trenches, wherein the second-type gate trenches are completely filled with the first insulating layer;
(h) Etching back the first insulating layer along the upper part of the first type gate groove;
(i) Forming a second insulating layer along the side wall of the groove to serve as a gate oxide layer;
(j) Depositing a doped polysilicon layer into the first type gate trench;
(k) The first doped polysilicon layer is etched back to serve as a gate electrode.
The above and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which is illustrated in the various drawing figures.
Drawings
Fig. 1 is a cross-sectional view of a conventional SiC semiconductor device having a trench-gate vertical double-diffused MOSFET as disclosed in the prior art.
Fig. 2 is a top view of a preferred super-junction trench MOSFETs with stripe shaped cells in accordance with the present invention.
Fig. 3A isbase:Sub>A preferred cross-sectional view of sectionbase:Sub>A-base:Sub>A' of fig. 2.
Figure 3B is a preferred cross-sectional view of section B-B' of figure 2.
Figure 4A is another preferred cross-sectional view of sectionbase:Sub>A-base:Sub>A' of figure 2.
Figure 4B is another preferred cross-sectional view of section B-B' of figure 2.
Fig. 5A is another preferred cross-sectional view of sectionbase:Sub>A-base:Sub>A' in fig. 2.
Fig. 5B is another preferred cross-sectional view of section B-B' of fig. 2.
Figure 6 is another preferred cross-sectional view of sectionbase:Sub>A-base:Sub>A' of figure 2.
Figure 7 is another preferred cross-sectional view of section B-B' of figure 2.
Fig. 8A is a cross-sectional view of another preferred embodiment according to the present invention.
Fig. 8B is a cross-sectional view of another preferred embodiment according to the present invention.
Fig. 9 is a cross-sectional view of a preferred IGBT embodiment according to the invention.
Fig. 10 is a cross-sectional view of a preferred IGBT embodiment with an integrated RC diode according to the present invention.
Fig. 11A to 11P are a series of cross-sectional views showing steps of manufacturing the SiC super junction trench MOSFET of fig. 4A and 4B.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, but need not, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. For example, the description herein makes more reference to an N-channel semiconductor integrated circuit, but it is apparent that other devices are possible. The following is a detailed description of preferred embodiments for practicing the invention, reference being made to the accompanying drawings. Some directional terms, such as "top," "bottom," "front," "back," "above," "below," and the like are described with reference to the orientation of the various figures. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used in the description above for purposes of illustration and is in no way limiting. It should be understood that various structural or logical substitutions and modifications in the embodiments are intended to be included within the true spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the inventive features of the various preferred embodiments described herein may be combined with each other, unless specifically noted otherwise.
Fig. 2 is a top view of a preferred trench MOSFETs having stripe shaped cells in accordance with the present invention. In each cell, a gate trench 201 surrounds a P shield region (PS) 202, wherein the gate trench 201 has a stripe shape, and the PS region 202 is connected to a ground P region (GP). The trenched source contact region 203 is located between every two adjacent gate trenches 201.
Figure 3A showsbase:Sub>A cross-sectional view of sectionbase:Sub>A-base:Sub>A' of the preferred embodiment shown in figure 2. The SiC power device comprises a super junction trench MOSFET formed on an N-type SiC epitaxial layer 302, wherein the epitaxial layer 302 is positioned on an N + SiC substrate 301, and a metal layer 320 is used as a drain metal after the back surface of the N + SiC substrate 301 is coated with Ti/Ni/Ag. In N epitaxial layer 302, a plurality of trenches are formed including a first type gate trench 303 and a second type gate trench 304 extending from an upper surface of epitaxial layer 302 down into epitaxial layer 302 without contacting an interface 316 of N epitaxial layer 302 and N + substrate 301, wherein first type gate trench 303 is located above second type gate trench 304 and first type gate trench 303 is wider than second type gate trench 304. The gate 305 is located at the upper portion of the first-type gate trench 303, and is surrounded by a thick bottom oxide layer as a first insulating layer 306 located at the bottom of the gate trench 303 and a second insulating layer 309 located at the sidewall of the gate trench 303, wherein the thickness of the second insulating layer 309 is smaller than that of the first insulating layer 306, and the second-type gate trench 304 is completely filled by the first insulating layer 306. Between each two adjacent first-type gate trenches 303, a p-body region 310 having an N + source region 311 is formed, which extends from near the upper surface of the N-epitaxial layer 302 and surrounds the gate electrode 305 lined with a second gate insulation layer 309. A dielectric spacer 321 is formed over the epitaxial layer 302 and a source metal 312 is formed over the dielectric spacer 321. The p-body region 310 and the n + source region 311 are further connected to the source metal 312 through a plurality of trench contact regions 323, wherein the trench contact regions 323 are filled with contact plugs 313, the contact plugs 313 and the source metal 312 are both Ti/TiN/Al alloy, and the bottom of the trench contact regions 323 are surrounded by the p + body contact regions 314 located under the n + source region 311. In accordance with the present invention, a P-shield region (PS) 315 is introduced into N-epi layer 202 adjacent to the sidewalls and bottom of second-type gate trench 304, and PS region 315 may be formed by performing an angled boron ion implantation, or a combination of angled and zero boron ion implantation, or a BSG layer deposition step on the sidewalls and bottom of second-type gate trench 304. Since the second-type gate trench 304 has a narrower trench width than the first-type gate trench 303, the width of the PS region 315 may be designed to be narrower than the first-type gate trench 303.
Fig. 3B is a cross-sectional view of section B-B ' of the preferred embodiment shown in fig. 2, the trench power device having a similar structure to the invention described in fig. 3A, except that in the structure of the present invention, there is also a grounded P region (GP) 317' surrounding the sidewalls and bottom of the first-type gate trench 303', the GP region 317' connecting the P body region 310' and the P shield region (PS) 315' and connecting to the source metal 312'. Since the second-type gate trench 304 'has a narrower trench width than the first-type gate trench 303', the PS region 315 'may be designed to have a narrower width than the first-type gate trench 303'. Accordingly, the pinch-off effect between two adjacent PS regions 315' is reduced, thereby reducing on-resistance.
Figure 4A isbase:Sub>A cross-sectional view ofbase:Sub>A sectionbase:Sub>A-base:Sub>A' of another preferred embodiment shown in figure 2. The trench semiconductor power device has a similar structure to the invention described in fig. 3A except that in the structure of the present invention, a p-type gate oxide electric field reduction region 418 (Pr, as shown) is further included as a second shielding region adjacent to the lower surface of the p-body region 410 and adjacent to the gate trench. The contact plug 413 filled in the trench source contact 423 in the structure of the present invention is Ti/TiN/W, and the source metal 412 is Al alloy.
Figure 4B is a cross-sectional view of a section B-B' of another preferred embodiment shown in figure 2. The trench semiconductor power device has a similar structure to the invention described in fig. 4A, except that in the structure of the present invention, there is also a grounded P region (GP) 417 'surrounding the sidewalls and bottom of the first type gate trench 403', the GP region 417 'connecting the P body region 410' and the P shield region (PS) 415 'and connecting to the source metal 412'.
Figure 5A isbase:Sub>A cross-sectional view ofbase:Sub>A sectionbase:Sub>A-base:Sub>A' of another preferred embodiment shown in figure 2. The trench semiconductor power device has a similar structure to the invention shown in fig. 3A, except that in the structure of the invention, P column regions 519 are introduced into the N epitaxial layer 502 to form super junction regions, and the super junction regions comprise a plurality of P column regions 519 and N regions 502 which are alternately arranged on the substrate 501. Wherein P-pillar regions 519 are located below the P-body regions 510 and above the bottom surface 516 of the N-epitaxial layer 502, which may be formed by multi-epitaxy or by filling deep trenches with an epitaxial layer having the second conductivity type. The contact plug 513 filled in the trench type source contact region 523 in the structure of the invention is Ti/TiN/Al, and the source metal 512 is Ti/TiN/Al alloy.
Figure 5B is a cross-sectional view of a section B-B' of another preferred embodiment shown in figure 2. The trench power device has a similar structure to the invention described in fig. 5A, except that in the structure of the present invention, there is a grounded P region (GP) 517 'surrounding the sidewalls and bottom of the first type gate trench 503', the GP region 517 'connecting the P body region 510' and the P shield region (PS) 515 'and connecting to the source metal 512'.
Figure 6 isbase:Sub>A cross-sectional view ofbase:Sub>A sectionbase:Sub>A-base:Sub>A' of another preferred embodiment shown in figure 2. The trench power device has a similar structure to the invention shown in fig. 3A, except that in the structure of the present invention, a current diffusion layer (CSL) 627 of the first conductivity type is further included below the P body region 610 and at a higher portion of the N epitaxial layer 602, so as to further prevent the PS region between two adjacent P shielding regions (PS) 615 from pinching off the current path, thereby further reducing the on-resistance, wherein the doping concentration (Ncs) of the current diffusion layer 627 is higher than the doping concentration (Nepi) of the N epitaxial layer 602. The contact plug 613 filled in the trench source contact 623 in the structure of the present invention is Ti/TiN/Al, and the source metal 612 is Ti/TiN/Al alloy.
Figure 7 isbase:Sub>A cross-sectional view ofbase:Sub>A sectionbase:Sub>A-base:Sub>A' of another preferred embodiment shown in figure 2. The trench power device has a similar structure to the invention shown in fig. 4A, except that in the structure of the invention, a current diffusion layer (CSL) 727 with a first conductivity type is further included below the P-body region 710 and at a higher portion of the N-epitaxial layer 702, so as to further avoid the formation of a current path pinched off by a P region between two adjacent P-shield regions (PS) 715, thereby further reducing the on-resistance, wherein the doping concentration (Ncs) of the current diffusion layer 727 is higher than the doping concentration (Nepi) of the N-epitaxial layer 702. The contact plug 713 filled in the trench-type source contact area 723 in the structure of the present invention is Ti/TiN/W, and the source metal 712 is Al alloy.
Fig. 8A shows another preferred embodiment according to the present invention. The trench power device has a similar structure to the invention shown in fig. 5A, except that in the structure of the invention, a current diffusion layer (CSL) 827 with a first conductivity type is further included below the P body region 810 and at a higher portion of the N epitaxial layer 802, so as to further prevent the PS region between the two P shielding regions (PS) 815 from pinching off the current path, thereby further reducing the on-resistance, wherein the doping concentration (Ncs) of the current diffusion layer 827 is higher than the doping concentration (Nepi) of the N epitaxial layer 802. The contact plug 813 filled in the trench type source contact area 823 in the structure of the invention is Ti/TiN/W, and the source metal 812 is Al alloy.
Fig. 8B shows another preferred embodiment according to the present invention. The trench power device has a similar structure to the invention shown in fig. 8A, except that in the structure of the invention, an N buffer layer 822' with resistivity of Rn is further included, the buffer layer 822' is located between the N + substrate 801' and the N epitaxial layer 802', the N epitaxial layer 802' is a single epitaxial layer with uniform doping concentration and resistivity of R, wherein R > Rn. In addition, a P-pillar region 819' is located below the P-body region 810' and contacts to a bottom surface 816' of the N-epitaxial layer 802', and the P-pillar region 819' may be formed by a multi-epitaxy method and also by filling an epitaxial layer having the second conductivity type in a deep trench.
Fig. 9 shows another preferred embodiment of the present invention, wherein the trench semiconductor power device is an IGBT (insulated gate bipolar transistor) device, and the present invention has a similar structure to the invention shown in fig. 8B, except that in the present invention, the IGBT device is formed on a P + substrate 901, and further includes an N buffer layer 922 with a resistivity of Rn located between the P + substrate 901 and an N epitaxial layer 902, and the N epitaxial layer 902 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, where R > Rn.
Fig. 10 shows another trench semiconductor power device according to another preferred embodiment of the present invention, which is another IGBT device, and the present invention has a similar structure to the invention of fig. 9, except that in the present invention, a plurality of heavily doped N + regions 1031 are further included in the P + substrate 1001 for forming a plurality of alternately arranged P + and N + regions as an integrated RC diode.
Fig. 11A-11P are a series of exemplary fabrication steps for forming the preferred embodiment of the present invention of fig. 4A and 4B. As shown in fig. 11A, an N epitaxial layer 1102 is first grown on an N + SiC substrate 1101, wherein the N epitaxial layer 1102 has a lower doping concentration than the N + substrate 1101. Subsequently, a p-body region 1110 and an N + source region 1111 are formed within the N-epitaxial layer 1102 in the active region. A hard mask 1113, such as an oxide layer, is formed on the top surface of the N epi layer 1102 to define a plurality of first-type gate trenches 1103. Subsequently, a plurality of first-type gate trenches 1103 are formed by dry oxide layer etching and dry silicon etching, and extend into the N-epi layer 1102 through the open regions in the hard mask, and the bottom of the first-type gate trenches does not contact the bottom surface 1116 of the N-epi layer 1102. A sacrificial oxide layer (not shown) is grown and removed to eliminate plasma damage introduced during the formation of the gate trench 1103.
As shown in fig. 11B, a dielectric layer 1117 is formed on the sidewalls and bottom of the first-type gate trench 1103 by an oxide layer deposition method or a thermal oxidation growth method.
As shown in fig. 11C, the dielectric layer 1117 at the bottom of the first-type gate trench 1103 is removed by dry oxide etching.
As shown in fig. 11D, a plurality of second-type gate trenches 1104 are formed using an anisotropic silicon etching method.
As shown in fig. 11E, an angled boron ion implantation and diffusion step is sequentially performed on the sidewall and the bottom of the second-type gate trench 1104 to form a p-region 1125 surrounding the second-type gate trench 1104. Furthermore, if the bottom of the gate trench 1104 is too narrow, a combination of zero and angled implants may be used to achieve the boron ion implant.
As shown in fig. 11F, depositing a BSG layer in the two types of trenches provides another method for forming p-regions 1125 surrounding the second type of gate trench 1104.
As shown in fig. 11G and 11H,base:Sub>A grounded P region (GP) mask, such as an oxide layer, is formed on the upper surface of the N epitaxial layer 1102, andbase:Sub>A second conductive type dopant is implanted into the sidewall and the bottom of the first type gate trench 1103 by usingbase:Sub>A wet dielectric etching method and an angled ion implantation withbase:Sub>A second conductive type dopant, so as to formbase:Sub>A second conductive type doped region surrounding the first type gate trench 1103, thereby forming cross-sectional structures ofbase:Sub>A-base:Sub>A 'section and B-B' section, respectively.
As shown in fig. 11I,base:Sub>A cross-sectional structure ofbase:Sub>A-base:Sub>A' section with P-shield region (PS) 1115 is formed, followed by removal of the grounded P-region (GP) mask and dielectric layer 1117. A thick oxide layer is grown as the first insulating layer 1106 along the inner walls of the two types of gate trenches 1103 and 1104 and the upper surface of the N epitaxial layer 1102 by thermal oxide growth or thick oxide deposition, wherein the second type gate trench 1104 is completely filled with the first insulating layer 1106.
As shown in fig. 11J, a cross-sectional structure of a B-B' section having a P-shield region (PS) 1115 and a grounded P-region (GP) 1117 is formed, followed by removal of the grounded P-region (GP) mask and dielectric layer 1117. A thick oxide layer is grown as the first insulating layer 1106 along the inner walls of the two types of gate trenches 1103 and 1104 and the upper surface of the N-epitaxial layer 1102 by thermal oxide growth or thick oxide deposition, wherein the second type of gate trench 1104 is completely filled with the first insulating layer 1106.
As shown in fig. 11K, which isbase:Sub>A cross-sectional structure ofbase:Sub>A-base:Sub>A', the first insulating layer 1106 is etched back from the upper surface of the N-epitaxial layer 1102 and the upper portion of the first-type gate trench 1103.
As shown in fig. 11L, which is a cross-sectional structure of section B-B', the first insulating layer 1106 is etched back from the upper surface of the N-epitaxial layer 1102 and the upper portion of the first-type gate trench 1103.
As shown in fig. 11M, which isbase:Sub>A cross-sectional structure ofbase:Sub>A sectionbase:Sub>A-base:Sub>A',base:Sub>A second insulating layer 1109 is formed asbase:Sub>A gate oxide layer along sidewalls of the first-type gate trenches 1103 and an upper surface of the N epitaxial layer 1102 by usingbase:Sub>A thermal growth method orbase:Sub>A deposition method, wherebase:Sub>A thickness of the second insulating layer 1109 is thinner than that of the first insulating layer 1106. Subsequently, a first doped polysilicon layer is deposited on the first gate insulating layer 1106, filling the upper portion of the first-type gate trench 1103, and then etched back by using a CMP method (chemical mechanical polishing method) or a plasma etching method to be used as the single gate electrode 1105.
As shown in fig. 11N, which is a cross-sectional structure of a section B-B', a second insulating layer 1109 is formed along sidewalls of the first-type gate trench 1103 and an upper surface of the N epitaxial layer 1102 by using a thermal growth method or a deposition method as a gate oxide layer, where a thickness of the second insulating layer 1109 is thinner than that of the first insulating layer 1106. Subsequently, a first doped polysilicon layer is deposited on the first gate insulating layer 1106, filling the upper portion of the first-type gate trench 1103, and then etched back by using a CMP method (chemical mechanical polishing method) or a plasma etching method to be used as the single gate electrode 1105.
Referring to fig. 11O, which showsbase:Sub>A cross-sectional structure ofbase:Sub>A-base:Sub>A',base:Sub>A second dielectric layer, which is an undoped oxide layer andbase:Sub>A BPSG layer, is formed on the upper surface of the entire structure by usingbase:Sub>A conventional technique. A mask (not shown) is covered on the upper surface of the second dielectric layer and etched back to form the dielectric spacer layer 1121. A contact region mask (not shown) is applied over the spacer layer 1121 to form a plurality of trenched contact regions 1123 by a sequential dry oxide etch and dry silicon etch. The trench contact 1123 extends into the p-body 1110 through the dielectric spacers 1121, n + source 1111, forming a trench source-body contact. By performing a boron ion implantation, a p-type gate oxide electric field reduction region 1118 (Pr, as shown) is formed adjacent to the lower surface of the p-body region 1110 and adjacent to the trench 1103. Subsequently, BF2 ion implantation is performed to form p + body contact doped regions 1114 within the p body regions 1110, which surround at least the bottom of the trenched source-body contact regions 1123. A Ti/TiN barrier metal layer is then deposited on the sidewalls and bottom of the trench contact regions 1123, followed by an RTA operation for silicide formation. A W metal layer is deposited over the barrier metal layer, and the W metal layer and the barrier metal layer are etched back to form Ti/TiN/W contact metal plugs 1113 in the trench source-body contact regions 1123. Depositing an Al alloy metal layer on the upper surface of the dielectric interlayer 1121, and lining the lower side of the Al alloy metal layer with a Ti or Ti/TiN resistance reducing layer. Subsequently, a metal mask (not shown) is covered, and the metal layer is etched to form a source metal 1112.
Referring to fig. 11P, which shows a cross-sectional structure of B-B', a second dielectric layer, which is an undoped oxide layer and a BPSG layer, is formed on the upper surface of the entire structure by a conventional technique. A mask (not shown) is covered on the upper surface of the second dielectric layer and etched back to form the dielectric spacer layer 1121. A contact region mask (not shown) is applied over the spacer layer 1121 to form a plurality of trenched contact regions 1123 by a sequential dry oxide etch and dry silicon etch. The trench contact 1123 extends into the p-body region 1110 through the dielectric spacers 1121, n + source region 1111, forming a trench source-body contact. By performing a boron ion implantation, a p-type gate oxide electric field reduction region 1118 (Pr, as shown) is formed adjacent to the lower surface of the p-body region 1110 and adjacent to the trench 1103. Subsequently, BF2 ion implantation is performed to form a p + body contact doped region 1114 within the p body region 1110, which surrounds at least the bottom of the trenched source-body contact region 1123. A Ti/TiN barrier metal layer is then deposited on the sidewalls and bottom of the trench contact regions 1123, followed by an RTA operation for silicide formation. A W metal layer is deposited over the barrier metal layer and the W metal layer and barrier metal layer are etched back to form Ti/TiN/W contact metal plugs 1113 in the trench source-body contact regions 1123. Depositing an Al alloy metal layer on the upper surface of the dielectric interlayer 1121, and lining the lower portion of the Al alloy metal layer with a Ti or Ti/TiN resistance reducing layer. Subsequently, a metal mask (not shown) is covered, and the metal layer is etched to form a source metal 1112.
While the invention has been described in terms of preferred embodiments, it is to be understood that the above disclosure is not to be considered as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Therefore, the appended claims should be construed to cover all such alternatives and modifications as fall within the true spirit and scope of the invention.

Claims (17)

1. A SiC power device comprising a plurality of cells, wherein each cell is located within an active region, further comprising:
an epitaxial layer having a first conductivity type and located over the substrate;
at least one stripe-shaped gate trench surrounded by a source region having the first conductivity type, the source region being located in a body region having a second conductivity type and being close to an upper surface of the epitaxial layer;
each strip-shaped gate trench comprises a first type gate trench and a second type gate trench; the first type gate groove is positioned above the second type gate groove, and the width of the first type gate groove is larger than that of the second type gate groove;
a gate electrode located in said first-type gate trench and surrounded by a first insulating layer located at the bottom of said first-type gate trench and a second insulating layer located at the sidewall of said first-type gate trench; the first insulating layer has a thickness greater than the second insulating layer.
A P shield region, serving as a gate oxide electric field reduction region, having a second conductivity type and surrounding said second type gate trench, wherein said second type gate trench is completely filled with said first insulating layer;
at least one grounded P region of a second conductivity type surrounding sidewalls and a bottom of the first-type gate trench and connecting the body region and the P shield region;
the body region and the source region are connected to a source metal through a plurality of source contact regions.
2. The SiC power device of claim 1 wherein the substrate is of the first conductivity type.
3. The SiC power device of claim 1 wherein the substrate has the first conductivity type, and further comprising: a P-shield region of said second conductivity type, serving as a gate oxide field-reduction region, adjacent a lower surface of said body region and adjacent said stripe-shaped gate trench.
4. The SiC power device of claim 1 further comprising a super junction structure including P-pillar regions of the second conductivity type overlying the substrate.
5. The SiC power device of claim 4 wherein the substrate is of the first conductivity type and the epitaxial layer is a single epitaxial layer having a uniform doping concentration.
6. The SiC power device of claim 4 wherein the substrate is of the first conductivity type, the epitaxial layer is a single epitaxial layer of uniform doping concentration and having a resistivity of R, and the trench semiconductor power device further comprises a buffer layer of the first conductivity type and having a resistivity of Rn, the buffer layer being located between the substrate and the epitaxial layer, wherein R > Rn.
7. The SiC power device of claim 4 wherein the substrate is of the second conductivity type, the epitaxial layer is a single epitaxial layer having a uniform doping concentration and a resistivity of R, and the trench semiconductor power device further comprises a buffer layer of the first conductivity type and a resistivity of Rn, the buffer layer being located between the substrate and the epitaxial layer, wherein R > Rn.
8. The SiC power device of claim 4 wherein the substrate has the second conductivity type, further comprising: a buffer layer of said first conductivity type and located between said substrate and said epitaxial layer; and a plurality of heavily doped regions of the first conductivity type located in the substrate, forming a plurality of alternating P + and N + regions.
9. The SiC power device of claim 1 further comprising a Current Spreading Layer (CSL) of said first conductivity type surrounding at least trench sidewalls of a first type gate trench located in said active region, wherein said CSL is doped at a higher concentration than said epitaxial layer.
10. The SiC power device of claim 4 wherein the P-pillar region of the super-junction structure is formed by multi-epitaxy.
11. The SiC power device of claim 4, wherein the P-pillar region of the super-junction structure is formable by filling a deep trench with an epitaxial layer having the second conductivity type.
12. A method for fabricating a SiC power device having a two-step gate trench structure, comprising the steps of:
growing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is lower than that of the substrate; forming a first type and a second type gate trench by performing the steps of:
(a) Forming a groove mask on the upper surface of the epitaxial layer for defining a plurality of first type gate grooves;
(b) Forming the first type gate trench in the epitaxial layer by etching an open region in a trench mask;
(c) Forming a dielectric layer on the side wall and the bottom of the first type gate groove;
(d) Removing the bottom of the first type gate trench by anisotropic etching;
(e) And carrying out anisotropic silicon etching to form a plurality of second-type gate trenches.
13. The method of manufacturing the SiC power device of claim 12, further comprising performing an angled ion implantation to implant the second conductivity type dopants into the sidewalls and bottom of the second type gate trench to form a second conductivity type doped region surrounding the second type gate trench.
14. The method of manufacturing a SiC power device of claim 13, further comprising performing a zero degree ion implantation of the second conductivity type dopant.
15. The method of manufacturing a SiC power device of claim 12, further including depositing a BSG layer into the trench after step (e) to form a second conductivity type doped region surrounding a lower portion of the trench.
16. The method of claim 12, further comprising forming a ground P-region mask, implanting dopants of the second conductivity type into the sidewalls and bottom of the first-type gate trench using wet dielectric etch and angled ion implantation of dopants of the second conductivity type to form a doped region of the second conductivity type surrounding the first-type gate trench.
17. The method of manufacturing the SiC power device of claim 16, further comprising the steps of:
(f) Removing the dielectric layer;
(g) Forming a first insulating layer along inner surfaces of the first-type and second-type gate trenches, wherein the second-type gate trenches are completely filled with the first insulating layer;
(h) Back etching the first insulating layer along the upper part of the first type gate groove;
(i) Forming a second insulating layer along the side wall of the groove to serve as a gate oxide layer;
(j) Depositing a doped polysilicon layer into the first type gate trench;
(k) And etching back the first doped polysilicon layer to be used as a gate electrode.
CN202211018776.7A 2022-08-24 2022-08-24 SIC semiconductor power device with low on-resistance and low switching loss Pending CN115458591A (en)

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