CN116169171A - SOI-LDMOS device and manufacturing method thereof - Google Patents

SOI-LDMOS device and manufacturing method thereof Download PDF

Info

Publication number
CN116169171A
CN116169171A CN202111417634.3A CN202111417634A CN116169171A CN 116169171 A CN116169171 A CN 116169171A CN 202111417634 A CN202111417634 A CN 202111417634A CN 116169171 A CN116169171 A CN 116169171A
Authority
CN
China
Prior art keywords
region
layer
oxide layer
soi
gate oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111417634.3A
Other languages
Chinese (zh)
Other versions
CN116169171B (en
Inventor
莫海锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Huatai Electronics Co Ltd
Original Assignee
Suzhou Huatai Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Huatai Electronics Co Ltd filed Critical Suzhou Huatai Electronics Co Ltd
Priority to CN202111417634.3A priority Critical patent/CN116169171B/en
Priority claimed from CN202111417634.3A external-priority patent/CN116169171B/en
Publication of CN116169171A publication Critical patent/CN116169171A/en
Application granted granted Critical
Publication of CN116169171B publication Critical patent/CN116169171B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The application provides an SOI-LDMOS device and a manufacturing method thereof, wherein the device comprises an SOI substrate, an active region, at least one first conducting structure and a second conducting structure, wherein the SOI substrate comprises a substrate, a trap-rich layer, a buried layer oxide layer, a top silicon layer and a gate oxide layer which are sequentially arranged; the active region is positioned in the top silicon layer, and comprises a body region, a body contact region and a source region, wherein the body contact region is adjacent to the source region and is positioned in the body region; the first conducting structure is positioned in the SOI substrate and penetrates through the trap rich layer and the substrate; the second conducting structure is located in the SOI substrate and is in contact with the first conducting structure, penetrates through the gate oxide layer, the body region and the buried oxide layer and is in contact with the trap-rich layer, and the second conducting structure is located on one side of the body contact region, which is far away from the source region. The second conducting structure ensures better heat dissipation capacity and robustness of the device.

Description

SOI-LDMOS device and manufacturing method thereof
Technical Field
The application relates to the field of semiconductors, in particular to an SOI-LDMOS device and a manufacturing method thereof.
Background
In the traditional SOI-LDMOS (Silicon-On-Insulator Laterally-Diffused Metal-Oxide Semiconductor) device, the insulating oxide layer in the device reduces the coupling capacitance between the output end of the LDMOS device and the substrate, and greatly improves the performance of the device. However, the thermal conductivity of the insulating oxide layer is only about one percent of that of silicon, so that the heat dissipation capacity is reduced, and the SOI-LDMOS device is limited to be applied to the low-power field. Meanwhile, due to the inherent parasitic bipolar transistor, the LDMOS device is easy to start under the hole current generated by strong ionization of the drift region, and the robustness of the LDMOS device is limited.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main purpose of the application is to provide an SOI-LDMOS device and a manufacturing method thereof, so as to solve the problems that the heat dissipation capacity and the robustness of the SOI-LDMOS device in the prior art are poor, and the performance of the device is affected.
According to an aspect of an embodiment of the present invention, there is provided an SOI-LDMOS device, including an SOI substrate, an active region, at least one first conductive structure and a second conductive structure, wherein the SOI substrate includes a substrate, a trap rich layer, a buried oxide layer, a top silicon layer and a gate oxide layer, which are sequentially disposed; the active region is located in the top silicon layer, and comprises a body region, a body contact region and a source region, wherein the body contact region is adjacent to the source region and is located in the body region; at least one first conducting structure is located in the SOI substrate, and penetrates through the trap rich layer and the substrate; the second conduction structure is located in the SOI substrate and is in contact with the first conduction structure, penetrates through the gate oxide layer, the body region, the buried layer oxide layer and is in contact with the trap-rich layer, and the second conduction structure is located on one side of the body contact region, which is far away from the source region.
Optionally, the SOI-LDMOS device further comprises a dielectric layer and a third conductive structure, wherein the dielectric layer is located in the gate oxide layer and is located on at least part of the surfaces of the body contact region and the source region away from the buried oxide layer; the third conducting structure is located in the gate oxide layer, the first end of the third conducting structure is in contact with the dielectric layer, and the second end of the third conducting structure is flush with the surface, away from the top silicon layer, of the gate oxide layer.
Optionally, the SOI-LDMOS device further comprises a metal layer on a surface of the gate oxide layer remote from the top silicon layer, and the metal layer is in contact with the second and third conductive structures, respectively.
Optionally, the active region further includes a drain region and a drift region, the drift region is located at one side of the body region, the drain region is located in the drift region, the SOI-LDMOS device further includes a gate region, and the gate region is located in the gate oxide layer and is located at one side of the third conductive structure away from the second conductive structure.
Optionally, a distance between an edge of the second conductive structure and an edge of the body contact region is less than 0.3 μm.
Optionally, the dimension of the first conducting structure in the first direction is 1.5 μm-100 μm, the first direction is perpendicular to the thickness direction of the substrate, and the first direction is parallel to the distance direction between the second conducting structure and the body contact region.
Optionally, the trap rich layer material comprises polysilicon, the first via structure material comprises tungsten, and the second via structure material comprises tungsten.
According to another aspect of the embodiment of the present invention, there is also provided a method for manufacturing an SOI-LDMOS device, including: providing a preparation SOI substrate, wherein the preparation SOI substrate comprises a substrate, a trap-rich layer, a buried oxide layer and a top silicon layer which are sequentially arranged; forming an active region in the top silicon layer, wherein the active region comprises a body region, a body contact region and a source region, and the body contact region is adjacent to the source region and is located in the body region; forming a gate oxide layer on the exposed surface of the preparation SOI substrate with the active region to obtain an SOI substrate; sequentially forming a second groove and at least one first groove in an SOI substrate, wherein the second groove is communicated with the first groove, the second groove penetrates through the gate oxide layer, the body region and the buried oxide layer to a preset surface, the preset surface is a surface, far away from the substrate, of the trap-rich layer, and the first groove penetrates through the trap-rich layer and the substrate; and filling a first material in the first groove to form a first conducting structure, and filling a second material in the second groove to form a second conducting structure.
Optionally, forming a gate oxide layer on an exposed surface of the preliminary SOI substrate on which the active region is formed, including: forming a dielectric layer on at least part of the surfaces of the body contact region and the source region, which are far away from the buried oxide layer; forming a preparation gate oxide layer on the exposed surface on which the dielectric layer is formed and the exposed surface of the preparation SOI substrate; removing part of the preparation gate oxide layer to form a third groove, wherein at least part of the dielectric layer is exposed by the third groove, and the rest of the preparation gate oxide layer forms the gate oxide layer; filling a third material into the third groove to form a third conducting structure
Optionally, after filling the first groove with a first material to form a first conductive structure and filling the second groove with a second material to form a second conductive structure, the method further includes: and forming a metal layer on the surface of the gate oxide layer, which is far away from the top silicon layer, wherein the metal layer is respectively contacted with the second conducting structure and the third conducting structure.
By adopting the technical scheme, the SOI-LDMOS device comprises an SOI substrate, an active region, at least one first conducting structure and a second conducting structure, wherein the SOI substrate comprises a substrate, a trap-rich layer, a buried layer oxide layer, a top silicon layer and a gate oxide layer which are sequentially arranged; the active region is located in the top silicon layer, and comprises a body region, a body contact region and a source region, wherein the body contact region is adjacent to the source region and is located in the body region; at least one first conducting structure is located in the SOI substrate, and penetrates through the trap rich layer and the substrate; the second conduction structure is located in the SOI substrate and is in contact with the first conduction structure, penetrates through the gate oxide layer, the body region, the buried layer oxide layer and is in contact with the trap-rich layer, and the second conduction structure is located on one side of the body contact region, which is far away from the source region. Compared with the problems that the heat radiation capacity and the robustness of the SOI-LDMOS device are poor and the performance of the device is affected in the prior art, in the SOI-LDMOS device, the second conducting structure penetrates through the gate oxide layer, the body region, the buried layer oxide layer and contacts with the trap-rich layer, the buried layer oxide layer is opened, a heat radiation channel with low thermal resistance is provided, and the heat radiation capacity of the device is guaranteed. Meanwhile, the device forms a good current path between the second conduction structure and the body region, and the current of the body region can directly reach the substrate through the second conduction structure, so that the resistance of the body region is ensured to be smaller, the base region resistance of the parasitic bipolar transistor of the device is ensured to be smaller, and the robustness of the device is ensured to be better.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a schematic structure of an SOI-LDMOS device according to an embodiment of the present application;
fig. 2 shows a schematic top view of the SOI-LDMOS device of fig. 1;
fig. 3 is a flow chart illustrating a method of fabricating an SOI-LDMOS device according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. an SOI substrate; 20. an active region; 30. a first conductive structure; 40. a second conductive structure; 50. a dielectric layer; 60. a third conductive structure; 70. a metal layer; 80. a gate region; 90. a source field plate; 100. a fourth conductive structure; 101. a substrate; 102. a trap rich layer; 103. a buried oxide layer; 104. a top silicon layer; 105. a gate oxide layer; 201. a body region; 202. a body contact region; 203. a source region; 204. a drain region; 205. and a drift region.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the SOI-LDMOS device in the prior art has poor heat dissipation capability and robustness, and affects the performance of the device.
According to an embodiment of the present application, as shown in fig. 1, there is provided an SOI-LDMOS device, including an SOI substrate 10, an active region 20, at least one first conductive structure 30 and a second conductive structure 40, wherein the SOI substrate 10 includes a substrate 101, a trap rich layer 102, a buried oxide layer 103, a top silicon layer 104 and a gate oxide layer 105, which are sequentially disposed; the active region 20 is located in the top silicon layer 104, the active region 20 includes a body region 201, a body contact region 202, and a source region 203, and the body contact region 202 is adjacent to the source region 203 and is located in the body region 201; at least one of the first conductive structures 30 is located in the SOI substrate 10, the first conductive structure 30 penetrating through the trap rich layer 102 and the substrate 101; the second conductive structure 40 is located in the SOI substrate 10 and is in contact with the first conductive structure 30, the second conductive structure 40 penetrates the gate oxide layer 105, the body region 201, the buried oxide layer 103 and is in contact with the trap rich layer 102, and the second conductive structure 40 is located on a side of the body contact region 202 away from the source region 203.
The SOI-LDMOS device comprises an SOI substrate, an active region, at least one first conducting structure and a second conducting structure, wherein the SOI substrate comprises a substrate, a trap-rich layer, a buried oxide layer, a top silicon layer and a gate oxide layer which are sequentially arranged; the active region is positioned in the top silicon layer, and comprises a body region, a body contact region and a source region, wherein the body contact region is adjacent to the source region and is positioned in the body region; at least one first conducting structure is positioned in the SOI substrate, and penetrates through the trap rich layer and the substrate; the second conducting structure is located in the SOI substrate and is in contact with the first conducting structure, penetrates through the gate oxide layer, the body region, the buried oxide layer and is in contact with the trap rich layer, and the second conducting structure is located on one side of the body contact region away from the source region. Compared with the problems of poor heat radiation capability and poor robustness of the SOI-LDMOS device and influence on the performance of the device in the prior art, in the SOI-LDMOS device, the second conducting structure penetrates through the gate oxide layer, the body region and the buried layer oxide layer and is in contact with the trap-rich layer, the buried layer oxide layer is opened, a heat radiation channel with low thermal resistance is provided, and the heat radiation capability of the device is guaranteed. Meanwhile, a good current path is formed between the second conduction structure and the body region, and the current of the body region can directly reach the substrate through the second conduction structure, so that the resistance of the body region is ensured to be smaller, the base region resistance of the parasitic bipolar transistor of the device is ensured to be smaller, and the robustness of the device is ensured to be better.
In order to further ensure the robustness of the device, according to one embodiment of the present application, as shown in fig. 1, the SOI-LDMOS device further includes a dielectric layer 50 and a third conductive structure 60, where the dielectric layer 50 is located in the gate oxide layer 105 and on at least a portion of the surface of the body contact region 202 and the source region 203 away from the buried oxide layer 103; the third conductive structure 60 is located in the gate oxide layer 105, the first end of the third conductive structure 60 is in contact with the dielectric layer 50, and the second end of the third conductive structure 60 is flush with the surface of the gate oxide layer 105 away from the top silicon layer 104. The third conducting structure is respectively connected with the body contact area and the source area through the dielectric layer, so that the resistance of the body contact area is further ensured to be smaller, and the device is further ensured to form good ohmic contact. In particular, the body contact region may be further ensured to have a small resistance by ion implantation into the body contact region.
According to another embodiment of the present application, as shown in fig. 1, the SOI-LDMOS device further includes a metal layer 70, wherein the metal layer 70 is located on a surface of the gate oxide layer 105 away from the top silicon layer 104, and the metal layer 70 is in contact with the second conductive structure 40 and the third conductive structure 60, respectively.
According to yet another embodiment of the present application, as shown in fig. 1, the active region 20 further includes a drain region 204 and a drift region 205, the drift region 205 is located on one side of the body region 201, the drain region 204 is located in the drift region 205, and the SOI-LDMOS device further includes a gate region 80, the gate region 80 is located in the gate oxide layer 105 and on a side of the third conductive structure 60 away from the second conductive structure 40. The SOI-LDMOS device further comprises a source field plate 90, the source field plate 90 being located in the gate oxide layer 105, and the source field plate 90 being located on a side of the gate region 80 remote from the third conductive structure 60, the gate oxide layer 105 further comprising a fourth conductive structure 100, the dielectric layer 50 being further located on at least a part of a surface of the drain region 204 remote from the buried oxide layer 103, the fourth conductive structure 100 being located in the gate oxide layer 105, a first end of the fourth conductive structure 100 being in contact with the dielectric layer 50 located on at least a part of a surface of the drain region 204 remote from the buried oxide layer 103, a second end of the fourth conductive structure 100 being level with a surface of the gate oxide layer 105 remote from the top silicon layer 104, the metal layer 70 being further in contact with a second end of the fourth conductive structure 100.
In order to further ensure that the heat dissipation capability of the device is better, and further ensure that the robustness of the device is better, the second conductive structure needs to be as close to the body contact area and the body area as possible, and according to a specific embodiment of the present application, a distance between an edge of the second conductive structure and an edge of the body contact area is smaller than 0.3 μm. Therefore, the second conduction structure is ensured to be as close to the body contact area as possible, and the heat dissipation and the robustness of the device are further ensured to be better.
According to another specific embodiment of the present application, the dimension of the first conductive structure in the first direction is 1.5 μm to 100 μm, the first direction is perpendicular to the thickness direction of the substrate, and the first direction is parallel to the distance direction between the second conductive structure and the body contact region. Therefore, better heat dissipation and robustness of the device can be further ensured.
According to yet another specific embodiment of the present application, the trap rich layer material comprises polysilicon, the first conductive structure material comprises tungsten, and the second conductive structure material comprises tungsten.
Specifically, the trap rich layer is made of polysilicon, the first conducting structure is made of tungsten, and the second conducting structure is made of tungsten.
In still another embodiment of the present application, as shown in fig. 2, one of the second conductive structures 40 may be in contact with a plurality of the first conductive structures 30, so as to connect a plurality of the second conductive structures 40, and one metal layer 70 may also cover a plurality of the second conductive structures 40.
According to another exemplary embodiment of the present application, a method for fabricating an SOI-LDMOS device is also provided.
Fig. 3 is a flow chart of a method of fabricating an SOI-LDMOS device according to an embodiment of the present application. As shown in fig. 3, the method comprises the steps of:
step S101, providing a preparation SOI substrate, wherein the preparation SOI substrate comprises a substrate, a trap-rich layer, a buried oxide layer and a top silicon layer which are sequentially arranged;
step S102, forming an active region in the top silicon layer, wherein the active region comprises a body region, a body contact region and a source region, and the body contact region is adjacent to the source region and is located in the body region;
step S103, forming a gate oxide layer on the exposed surface of the prepared SOI substrate with the active region formed thereon, to obtain an SOI substrate;
step S104, sequentially forming a second groove and at least one first groove in the SOI substrate, wherein the second groove is communicated with the first groove, the second groove penetrates through the gate oxide layer, the body region and the buried oxide layer to a preset surface, the preset surface is the surface of the trap-rich layer far away from the substrate, and the first groove penetrates through the trap-rich layer and the substrate;
step S105, filling a first material in the first groove to form a first conductive structure, and filling a second material in the second groove to form a second conductive structure.
In the method for manufacturing the SOI-LDMOS device, a preparation SOI substrate is provided, wherein the substrate, the trap-rich layer, the buried oxide layer and the top silicon layer are sequentially arranged; forming an active region in the top silicon layer, wherein the active region comprises a body region, a body contact region and a source region, and the body contact region is adjacent to the source region and is positioned in the body region; forming a gate oxide layer on the surface of the bare drain of the preparation SOI substrate after forming the active region to obtain an SOI substrate; sequentially forming a second groove and at least one first groove in the SOI substrate, wherein the second groove is communicated with the first groove, the second groove penetrates through the gate oxide layer, the body region and the buried oxide layer to a preset surface, the preset surface is a surface, far away from the substrate, of the trap-rich layer, and the first groove penetrates through the trap-rich layer and the substrate; and filling a first material in the first groove to form a first conducting structure, and filling a second material in the second groove to form a second conducting structure. Compared with the problems of poor heat radiation capability and poor robustness of the SOI-LDMOS device and influence on the device performance in the prior art, in the manufacturing method of the SOI-LDMOS device, the second conducting structure penetrates through the gate oxide layer, the body region, the buried layer oxide layer and contacts with the trap-rich layer, the buried layer oxide layer is opened, a heat radiation channel with low thermal resistance is provided, and the heat radiation capability of the device is guaranteed. Meanwhile, a good current path is formed between the second conduction structure and the body region, and the current of the body region can directly reach the substrate through the second conduction structure, so that the resistance of the body region is ensured to be smaller, the base region resistance of the parasitic bipolar transistor of the device is ensured to be smaller, and the robustness of the device is ensured to be better.
According to a specific embodiment of the present application, forming a gate oxide layer on an exposed surface of the preliminary SOI substrate on which the active region is formed includes: forming a dielectric layer on at least part of the surface of the body contact region and the source region, which is far away from the buried oxide layer; forming a preliminary gate oxide layer on the exposed surface on which the dielectric layer is formed and on the exposed surface of the preliminary SOI substrate; removing part of the preparation gate oxide layer to form a third groove, wherein the third groove exposes at least part of the dielectric layer, and the rest of the preparation gate oxide layer forms the gate oxide layer; and filling a third material in the third groove to form a third conducting structure. The third conducting structure is respectively connected with the body contact area and the source area through the dielectric layer, so that the resistance of the body contact area is further ensured to be smaller, and the device is further ensured to form good ohmic contact. In particular, the body contact region may be further ensured to have a small resistance by ion implantation into the body contact region.
In an actual application process, a dielectric layer is formed on at least part of the surfaces of the body contact region and the source region, which are far away from the buried oxide layer, and the method further comprises: and forming a dielectric layer on at least part of the surface of the drain electrode, which is far away from the buried oxide layer.
According to another specific embodiment of the present application, after filling the first groove with a first material to form a first conductive structure and filling the second groove with a second material to form a second conductive structure, the method further includes: and forming a metal layer on the surface of the gate oxide layer, which is far away from the top silicon layer, wherein the metal layer is respectively contacted with the second conducting structure and the third conducting structure.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) The SOI-LDMOS device comprises an SOI substrate, an active region, at least one first conducting structure and a second conducting structure, wherein the SOI substrate comprises a substrate, a trap-rich layer, a buried layer oxide layer, a top silicon layer and a gate oxide layer which are sequentially arranged; the active region is positioned in the top silicon layer, and comprises a body region, a body contact region and a source region, wherein the body contact region is adjacent to the source region and is positioned in the body region; at least one first conducting structure is positioned in the SOI substrate, and penetrates through the trap rich layer and the substrate; the second conducting structure is located in the SOI substrate and is in contact with the first conducting structure, penetrates through the gate oxide layer, the body region, the buried oxide layer and is in contact with the trap rich layer, and the second conducting structure is located on one side of the body contact region away from the source region. Compared with the problems of poor heat radiation capability and poor robustness of the SOI-LDMOS device and influence on the performance of the device in the prior art, in the SOI-LDMOS device, the second conducting structure penetrates through the gate oxide layer, the body region and the buried layer oxide layer and is in contact with the trap-rich layer, the buried layer oxide layer is opened, a heat radiation channel with low thermal resistance is provided, and the heat radiation capability of the device is guaranteed. Meanwhile, a good current path is formed between the second conduction structure and the body region, and the current of the body region can directly reach the substrate through the second conduction structure, so that the resistance of the body region is ensured to be smaller, the base region resistance of the parasitic bipolar transistor of the device is ensured to be smaller, and the robustness of the device is ensured to be better.
2) In the manufacturing method of the SOI-LDMOS device, a preparation SOI substrate is provided, wherein the substrate, the trap-rich layer, the buried oxide layer and the top silicon layer are sequentially arranged; forming an active region in the top silicon layer, wherein the active region comprises a body region, a body contact region and a source region, and the body contact region is adjacent to the source region and is positioned in the body region; forming a gate oxide layer on the surface of the bare drain of the preparation SOI substrate after forming the active region to obtain an SOI substrate; sequentially forming a second groove and at least one first groove in the SOI substrate, wherein the second groove is communicated with the first groove, the second groove penetrates through the gate oxide layer, the body region and the buried oxide layer to a preset surface, the preset surface is a surface, far away from the substrate, of the trap-rich layer, and the first groove penetrates through the trap-rich layer and the substrate; and filling a first material in the first groove to form a first conducting structure, and filling a second material in the second groove to form a second conducting structure. Compared with the problems of poor heat radiation capability and poor robustness of the SOI-LDMOS device and influence on the device performance in the prior art, in the manufacturing method of the SOI-LDMOS device, the second conducting structure penetrates through the gate oxide layer, the body region, the buried layer oxide layer and contacts with the trap-rich layer, the buried layer oxide layer is opened, a heat radiation channel with low thermal resistance is provided, and the heat radiation capability of the device is guaranteed. Meanwhile, a good current path is formed between the second conduction structure and the body region, and the current of the body region can directly reach the substrate through the second conduction structure, so that the resistance of the body region is ensured to be smaller, the base region resistance of the parasitic bipolar transistor of the device is ensured to be smaller, and the robustness of the device is ensured to be better.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. An SOI-LDMOS device, comprising:
the SOI substrate comprises a substrate, a trap-rich layer, a buried oxide layer, a top silicon layer and a gate oxide layer which are sequentially arranged;
an active region in the top silicon layer, the active region comprising a body region, a body contact region and a source region, the body contact region being adjacent to the source region and both being in the body region;
at least one first conductive structure in the SOI substrate, the first conductive structure penetrating the trap rich layer and the substrate;
the second conduction structure is positioned in the SOI substrate and is in contact with the first conduction structure, penetrates through the gate oxide layer, the body region, the buried layer oxide layer and is in contact with the trap-rich layer, and the second conduction structure is positioned on one side of the body contact region, which is far away from the source region.
2. The SOI-LDMOS device of claim 1, further comprising:
the dielectric layer is positioned in the gate oxide layer and is positioned on at least part of surfaces of the body contact region and the source region, which are far away from the buried oxide layer;
and the second end of the third conduction structure is flush with the surface, far away from the top silicon layer, of the gate oxide layer.
3. The SOI-LDMOS device of claim 2, further comprising a metal layer on a surface of the gate oxide layer remote from the top silicon layer, the metal layer being in contact with the second and third conductive structures, respectively.
4. The SOI-LDMOS device of claim 2, wherein the active region further comprises a drain region and a drift region, the drift region being located on a side of the body region, the drain region being located in the drift region, the SOI-LDMOS device further comprising a gate region located in the gate oxide layer and on a side of the third conductive structure remote from the second conductive structure.
5. The SOI-LDMOS device of any of claims 1 to 4 wherein an edge of the second conductive structure is less than 0.3 μm from an edge of the body contact region.
6. The SOI-LDMOS device of any of claims 1 to 4, wherein the first conductive structure has a dimension in a first direction of 1.5 μιη to 100 μιη, the first direction being perpendicular to a thickness direction of the substrate, and the first direction being parallel to a distance direction of the second conductive structure from the body contact region.
7. The SOI-LDMOS device of any of claims 1 to 4 wherein the trap rich layer material comprises polysilicon, the first via structure material comprises tungsten, and the second via structure material comprises tungsten.
8. The manufacturing method of the SOI-LDMOS device is characterized by comprising the following steps:
providing a preparation SOI substrate, wherein the preparation SOI substrate comprises a substrate, a trap-rich layer, a buried oxide layer and a top silicon layer which are sequentially arranged;
forming an active region in the top silicon layer, wherein the active region comprises a body region, a body contact region and a source region, and the body contact region is adjacent to the source region and is located in the body region;
forming a gate oxide layer on the exposed surface of the preparation SOI substrate with the active region to obtain an SOI substrate;
sequentially forming a second groove and at least one first groove in an SOI substrate, wherein the second groove is communicated with the first groove, the second groove penetrates through the gate oxide layer, the body region and the buried oxide layer to a preset surface, the preset surface is a surface, far away from the substrate, of the trap-rich layer, and the first groove penetrates through the trap-rich layer and the substrate;
and filling a first material in the first groove to form a first conducting structure, and filling a second material in the second groove to form a second conducting structure.
9. The method of claim 8, wherein forming a gate oxide layer on the exposed surface of the preliminary SOI substrate on which the active region is formed, comprises:
forming a dielectric layer on at least part of the surfaces of the body contact region and the source region, which are far away from the buried oxide layer;
forming a preparation gate oxide layer on the exposed surface on which the dielectric layer is formed and the exposed surface of the preparation SOI substrate;
removing part of the preparation gate oxide layer to form a third groove, wherein at least part of the dielectric layer is exposed by the third groove, and the rest of the preparation gate oxide layer forms the gate oxide layer;
and filling a third material in the third groove to form a third conducting structure.
10. The method of claim 9, wherein after filling the first recess with a first material to form a first via structure and filling the second recess with a second material to form a second via structure, the method further comprises:
and forming a metal layer on the surface of the gate oxide layer, which is far away from the top silicon layer, wherein the metal layer is respectively contacted with the second conducting structure and the third conducting structure.
CN202111417634.3A 2021-11-25 SOI-LDMOS device and manufacturing method thereof Active CN116169171B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111417634.3A CN116169171B (en) 2021-11-25 SOI-LDMOS device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111417634.3A CN116169171B (en) 2021-11-25 SOI-LDMOS device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN116169171A true CN116169171A (en) 2023-05-26
CN116169171B CN116169171B (en) 2024-05-14

Family

ID=

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705855A (en) * 2023-06-14 2023-09-05 安徽大学 SOIMOSFET structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560925A (en) * 2004-02-20 2005-01-05 中国科学院上海微系统与信息技术研究 Structure of partial SOI power apparatus and implementing method
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
EP2395548A1 (en) * 2010-06-08 2011-12-14 Nxp B.V. Silicon-on-insulator structure
CN104810334A (en) * 2013-11-06 2015-07-29 恩智浦有限公司 Semiconductor device
CN105845736A (en) * 2016-05-17 2016-08-10 昆山华太电子技术有限公司 LDMOS device structure and manufacture method thereof
US9923059B1 (en) * 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
CN110637369A (en) * 2017-05-19 2019-12-31 派赛公司 Manageable substrate effects for stable SOI FETs
CN112447523A (en) * 2019-08-27 2021-03-05 台湾积体电路制造股份有限公司 Integrated circuit and method of forming the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560925A (en) * 2004-02-20 2005-01-05 中国科学院上海微系统与信息技术研究 Structure of partial SOI power apparatus and implementing method
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
EP2395548A1 (en) * 2010-06-08 2011-12-14 Nxp B.V. Silicon-on-insulator structure
CN104810334A (en) * 2013-11-06 2015-07-29 恩智浦有限公司 Semiconductor device
CN105845736A (en) * 2016-05-17 2016-08-10 昆山华太电子技术有限公司 LDMOS device structure and manufacture method thereof
US9923059B1 (en) * 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
CN110637369A (en) * 2017-05-19 2019-12-31 派赛公司 Manageable substrate effects for stable SOI FETs
CN112447523A (en) * 2019-08-27 2021-03-05 台湾积体电路制造股份有限公司 Integrated circuit and method of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705855A (en) * 2023-06-14 2023-09-05 安徽大学 SOIMOSFET structure
CN116705855B (en) * 2023-06-14 2024-02-13 安徽大学 SOI MOSFET structure

Similar Documents

Publication Publication Date Title
CN1941416B (en) Ldmos device and method for manufacturing the same
US7994006B2 (en) Manufacturing method of semiconductor device
US20150357458A1 (en) III-Nitride Device with Improved Transconductance
US20090200610A1 (en) Semiconductor device and manufacturing method thereof
CN101211983B (en) Semiconductor device and method for fabricating the same
KR19990037698A (en) Transistor and its formation method
CN103107194A (en) Trench type power transistor device and manufacturing method thereof
TWI538206B (en) Semiconductor device and manufacturing method thereof
CN108701713A (en) Source-gate region framework in vertical power semiconductor device
US20220352367A1 (en) Semiconductor device
CN102315248B (en) The method of semiconductor devices and manufacture semiconductor devices
CN116169171B (en) SOI-LDMOS device and manufacturing method thereof
JP2006527914A5 (en)
JP3354127B2 (en) High voltage element and method of manufacturing the same
US8324669B2 (en) Process for manufacturing a MOS device with intercell ion implant confined to the gate electrode region
CN116169171A (en) SOI-LDMOS device and manufacturing method thereof
KR20070073235A (en) High voltage device and method for fabricating the same
TWI453913B (en) Depletion mode semiconductor device with trench gate
JP4290378B2 (en) Horizontal power MOS transistor and manufacturing method thereof
KR0135691B1 (en) Transistor and fabrication method thereof
KR100428788B1 (en) Capacitor Structure Of Semiconductor Device And Method Of Forming The Same
JP2001015742A (en) Semiconductor device
CN116207151A (en) SiC LDMOS device and manufacturing method thereof
CN114242595A (en) Manufacturing method of SOI-LDMOS structure and structure thereof
JP2000077678A (en) Semiconductor element and its manufacture

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant