WO2017197758A1 - Ldmos device structure and manufacturing method thereof - Google Patents

Ldmos device structure and manufacturing method thereof Download PDF

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WO2017197758A1
WO2017197758A1 PCT/CN2016/091817 CN2016091817W WO2017197758A1 WO 2017197758 A1 WO2017197758 A1 WO 2017197758A1 CN 2016091817 W CN2016091817 W CN 2016091817W WO 2017197758 A1 WO2017197758 A1 WO 2017197758A1
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ldmos device
layer
channel
dielectric layer
device structure
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Chinese (zh)
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彭虎
张耀辉
莫海锋
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昆山华太电子技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer

Definitions

  • the invention relates to an LDMOS device structure and a manufacturing method thereof, and belongs to the field of semiconductor integrated circuit manufacturing.
  • RFLDMOS is an improved N-channel MOSFET designed for RF power amplifiers with a horizontal communication structure with drain, source and gate on the chip surface.
  • the source is generally connected to the bottom of the substrate by a high impurity concentration channel in the body and grounded, and has a low concentration N-type drift region between the channel and the drain.
  • LDMOS uses a double-diffusion technique to perform two diffusions of borophosphorus in succession in the same lithography window. The difference in lateral junction depth between two impurity diffusions can accurately determine the channel length.
  • the channel length L can be made small and is not limited by the lithographic precision.
  • LDMOS Since LDMOS is easy to implement sub-micron channel length in process, transconductance, drain current, maximum operating frequency and speed are greatly improved compared with general MOSFETs; the presence of high-resistance drift region increases the breakdown voltage, and The parasitic resistance between the drain and the source is reduced, which is advantageous for improving the frequency characteristics.
  • LDMOS uses a self-aligned implant and a lateral diffusion process to form a channel.
  • the effective channel length depends on the polysilicon gate length, the double-diffused borophosphide implant dose, and the thermal process. Reducing the polysilicon gate length can shorten the effective gate length, reduce Cgs and Cgd, and improve device transconductance and characteristic frequency for better RF performance.
  • the existing RFLDMOS process generally uses polysilicon gate self-alignment for boron diffusion, and the polysilicon gate length is generally greater than 0.35 um to avoid lithography biasing the implant barrier.
  • concentrated boron implantation and long-time annealing form the source surface and the substrate connection, and the high temperature for a long time causes a large warpage of the silicon wafer, and the lithography size of 0.25 um or less cannot be realized.
  • the present invention provides an LDMOS device structure and a fabrication method thereof.
  • An LDMOS device structure comprising a metal connection layer, the metal connection layer will be an LDMOS device
  • the source is connected to the substrate from the surface, and the channel of the LDMOS device is a concentration gradient channel.
  • the LDMOS device has a gate length of 90-250 nm.
  • the metal tie layer material is tungsten or copper.
  • the channel is a P-type channel, and the channel has a high concentration near the source side.
  • a method for fabricating an LDMOS device structure comprising the following steps,
  • Step 1 gate oxide and gate deposition
  • Step 2 after the gate etching and the N-type drift region are implanted, depositing a dielectric layer on the surface;
  • Step 3 self-aligning P-type implantation, annealing to form a concentration gradient channel
  • Step 4 dense N-type implantation to form a source and a drain
  • Step 5 the dielectric layer is etched, and sidewalls are formed on both sides of the gate;
  • Step 6 self-aligning concentrated P-injection to form a P-type connection layer
  • Step 7 silicide fabrication and Faraday shield fabrication
  • Step 8 the dielectric layer is deposited and planarized to form a metal layer
  • Step 9 The dielectric layer lead holes and the through silicon vias are etched and metal-filled to form lead holes and metal connection layers, respectively;
  • a metal electrode is formed by depositing and etching on the metal layer.
  • the thickness of the dielectric layer is 500-2000 angstroms, the step coverage of the dielectric layer is >90%, and the material is LPCVD SiO2 and or LPCVD SiN.
  • the invention achieves the beneficial effects that the invention adopts a dielectric layer with high step coverage to deposit as a implantation barrier layer after polysilicon etching, solves the problem of lithography alignment precision, and can realize self-alignment of gate length below 0.25 um. Quasi-injection; at the same time, the metal connection layer is used to connect the source from the surface to the substrate, and the metal connection layer process is performed after the device is formed, so that the gate length of 0.25 um or less can be realized, and the manufacturing yield and uniformity can be ensured.
  • Figure 1 is a schematic diagram of the structure of an LDMOS device.
  • Figure 2 shows the formation of a polysilicon gate.
  • Figure 3 is a deposition forming dielectric layer.
  • Figure 4 shows the N-offset region implant.
  • Figure 5 shows a P-type implant.
  • Figure 6 shows the N+ injection.
  • Figure 7 is a dielectric layer etched to form a sidewall.
  • Figure 8 shows the formation of a P-type tie layer.
  • Figure 9 shows the silicide fabrication.
  • Figure 10 shows the formation of a metal layer.
  • Figure 11 shows the formation of lead holes and metal tie layers.
  • an LDMOS device structure includes a metal connection layer 41.
  • the metal connection layer 41 connects the LDMOS device source 24 from the surface to the substrate 11.
  • the metal connection layer 41 is made of tungsten or copper, and Ti/TiN is used.
  • the channel is a gradient-graded channel, the channel is a P-type channel, and the channel has a high concentration on the side close to the source 24, and the gate length of the LDMOS device is 90-250 nm.
  • a method for fabricating an LDMOS device structure includes the following steps:
  • Step 1 gate oxide and gate deposition
  • Step 2 after gate etching and N-type drift region implantation, depositing a dielectric layer 34' on the surface, the dielectric layer 34' has a thickness of 500-2000 angstroms, and the dielectric layer 34' step deposition step coverage is >90%.
  • the material is LPCVD SiO2 and or LPCVD SiN;
  • Step 3 self-aligning P-type implantation, annealing to form a concentration gradient channel
  • Step 4 rich N-type implantation, forming source 24 and drain 23;
  • Step 5 the dielectric layer 34' is etched, forming side walls 34 on both sides of the gate;
  • Step 6 self-aligning concentrated P-injection to form a P-type connection layer
  • Step 7 silicide fabrication and Faraday shield fabrication
  • Step 8 the dielectric layer 34' is deposited and planarized to form a metal layer 51;
  • Step 9 the dielectric layer 34' lead hole and the through silicon via etched metal after filling, forming the lead post 42 and the metal connection layer 41;
  • a metal electrode 61 is formed by depositing and etching on the metal layer 51.
  • the substrate 11 is a P-type epitaxial layer 12
  • a gate oxide layer 31 is thermally oxidized on the epitaxial layer 12
  • a polysilicon is deposited on the gate oxide layer 31.
  • Polysilicon gate 32 To reduce the resistance of the polysilicon gate 32, polysilicon and silicide may also be deposited to form a gate electrode.
  • a dielectric layer 34' is deposited, which dielectric layer 34' needs to have good step coverage, and the step coverage is greater than 90%.
  • phosphorus or arsenic is implanted into the surface of the silicon wafer to form an N-type layer 21' at an implantation dose of 5E11 to 5E12.
  • the photoresist 41 blocks the drain 23 region, and the polysilicon gate 32 and the dielectric layer 34' serve as a self-aligned implant barrier layer, implanting B+, and implanting a dose of 2E13-5E14 to form a P well 22'.
  • arsenic is implanted at source 24 and drain 23 at a dose of 1E15-4E15 and then annealed.
  • the P well 22' and the N type layer 21' are annealed to form a P well 22 and an N type drift region 21, respectively.
  • dielectric layer 34' is etched to form spacers 34.
  • the photoresist 41 blocks the drain 23 region, and the polysilicon 32 and the sidewall spacer 34 serve as a self-aligned implant barrier layer, and B+ is implanted and then rapidly annealed to form a P-type connection layer 25.
  • a silicide 33 is formed on the surface of the source electrode 24 and the P-type connection layer 25.
  • the field plate 35 is formed, deposited and planarized to form a metal layer 51.
  • the lead holes and the through silicon vias are etched and filled to form the lead post 42 and the metal connection layer 41.
  • Ti/TiN is generally used as the contact layer and the barrier layer, and tungsten is used as the metal filling.
  • a metal electrode 61 is deposited and etched on the metal layer 51.
  • the invention adopts a dielectric layer with high step coverage to deposit as a implantation barrier layer after polysilicon etching, solves the problem of lithography alignment precision, can realize self-aligned implantation of gate length below 0.25 um, and adopts metal connection layer
  • the source is connected from the surface to the substrate, and the metal connection layer process is performed after the device is formed, so that the gate length of 0.25 um or less can be achieved, and the manufacturing yield and uniformity can be ensured.

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Abstract

An LDMOS device structure comprises a metal connection layer (41) connecting a source (24) of an LDMOS device from a surface to a substrate (11). A channel of the LDMOS device is a concentration gradient channel. Further disclosed is a manufacturing method of the device structure. After polysilicon etching, a dielectric layer (34') having a high step coverage is deposited and is used as an injection barrier layer, thereby resolving an issue of photoetching alignment precision and enabling self-aligned injection of a gate length below 0.25 um. In addition, the metal connection layer is used to connect the source from the surface to the substrate, and a metal connection layer process is performed after the device is formed, so that a gate length below 0.25 um can be achieved, and both manufacturing yield and uniformity can be ensured.

Description

一种LDMOS器件结构及制作方法LDMOS device structure and manufacturing method 技术领域Technical field
本发明涉及一种LDMOS器件结构及制作方法，属于半导体集成电路制造领域。The invention relates to an LDMOS device structure and a manufacturing method thereof, and belongs to the field of semiconductor integrated circuit manufacturing.
背景技术Background technique
RFLDMOS是为射频功率放大器而设计的经改进的N沟道MOSFET，具有横向沟通结构，漏极、源极和栅极都在芯片表面。源极一般由体内高杂质浓度通道与衬底底部相连接并接地，在沟道与漏极之间有一个低浓度的N型漂移区。LDMOS采用双扩散技术，在同一光刻窗口相继进行硼磷两次扩散，由两次杂质扩散横向结深之差可精确地决定沟道长度。沟道长度L可以做得很小并且不受光刻精度的限制。由于LDMOS在工艺上易于实现亚微米的沟道长度，故跨导、漏极电流、最高工作频率和速度都较一般的MOSFET有大幅的提高；高阻漂移区的存在提高了击穿电压，并使漏源两极之间的寄生电阻得以减小，这有利于提高频率特性。RFLDMOS is an improved N-channel MOSFET designed for RF power amplifiers with a horizontal communication structure with drain, source and gate on the chip surface. The source is generally connected to the bottom of the substrate by a high impurity concentration channel in the body and grounded, and has a low concentration N-type drift region between the channel and the drain. LDMOS uses a double-diffusion technique to perform two diffusions of borophosphorus in succession in the same lithography window. The difference in lateral junction depth between two impurity diffusions can accurately determine the channel length. The channel length L can be made small and is not limited by the lithographic precision. Since LDMOS is easy to implement sub-micron channel length in process, transconductance, drain current, maximum operating frequency and speed are greatly improved compared with general MOSFETs; the presence of high-resistance drift region increases the breakdown voltage, and The parasitic resistance between the drain and the source is reduced, which is advantageous for improving the frequency characteristics.
LDMOS采用自对准注入和横向扩散工艺形成沟道，有效沟道长度取决于多晶硅栅长、双扩散硼磷注入剂量和热过程。降低多晶硅栅长可以使有效栅长缩短，降低Cgs和Cgd，提高器件跨导和特征频率，从而实现更好的射频性能。LDMOS uses a self-aligned implant and a lateral diffusion process to form a channel. The effective channel length depends on the polysilicon gate length, the double-diffused borophosphide implant dose, and the thermal process. Reducing the polysilicon gate length can shorten the effective gate length, reduce Cgs and Cgd, and improve device transconductance and characteristic frequency for better RF performance.
现有RFLDMOS工艺一般采用多晶硅栅自对准进行硼扩散，多晶硅栅长一般大于0.35um，以避免光刻对偏导致注入阻挡。另外浓硼注入和长时间退火形成源极表面和衬底连接，长时间高温会导致硅片较大的翘曲，不能实现0.25um以下的光刻尺寸。The existing RFLDMOS process generally uses polysilicon gate self-alignment for boron diffusion, and the polysilicon gate length is generally greater than 0.35 um to avoid lithography biasing the implant barrier. In addition, concentrated boron implantation and long-time annealing form the source surface and the substrate connection, and the high temperature for a long time causes a large warpage of the silicon wafer, and the lithography size of 0.25 um or less cannot be realized.
发明内容Summary of the invention
为了解决上述技术问题，本发明提供了一种LDMOS器件结构及制作方法。In order to solve the above technical problems, the present invention provides an LDMOS device structure and a fabrication method thereof.
为了达到上述目的，本发明所采用的技术方案是：In order to achieve the above object, the technical solution adopted by the present invention is:
一种LDMOS器件结构，包括金属连接层，所述金属连接层将LDMOS器 源极从表面连接至衬底，所述LDMOS器件的沟道为浓度渐变沟道。An LDMOS device structure comprising a metal connection layer, the metal connection layer will be an LDMOS device The source is connected to the substrate from the surface, and the channel of the LDMOS device is a concentration gradient channel.
所述LDMOS器件的栅长为90-250nm。The LDMOS device has a gate length of 90-250 nm.
金属连接层材料为钨或铜。The metal tie layer material is tungsten or copper.
沟道为P型沟道，沟道靠近源极一侧浓度高。The channel is a P-type channel, and the channel has a high concentration near the source side.
一种LDMOS器件结构的制作方法，包括以下步骤，A method for fabricating an LDMOS device structure, comprising the following steps,
步骤1，栅氧和栅淀积；Step 1, gate oxide and gate deposition;
步骤2，栅刻蚀和N型漂移区注入后，在表面淀积一层介质层；Step 2, after the gate etching and the N-type drift region are implanted, depositing a dielectric layer on the surface;
步骤3，自对准P型注入，退火形成浓度渐变沟道；Step 3, self-aligning P-type implantation, annealing to form a concentration gradient channel;
步骤4，浓N型注入，形成源极和漏极；Step 4, dense N-type implantation to form a source and a drain;
步骤5，介质层刻蚀，在栅两侧形成侧墙；Step 5, the dielectric layer is etched, and sidewalls are formed on both sides of the gate;
步骤6，自对准浓P性注入，形成P型连接层；Step 6, self-aligning concentrated P-injection to form a P-type connection layer;
步骤7，硅化物制作和法拉第屏蔽层制作；Step 7, silicide fabrication and Faraday shield fabrication;
步骤8，介质层淀积和平坦化，形成金属层；Step 8, the dielectric layer is deposited and planarized to form a metal layer;
步骤9，介质层引线孔和硅通孔刻蚀后金属填充，分别形成引线孔和金属连接层；Step 9. The dielectric layer lead holes and the through silicon vias are etched and metal-filled to form lead holes and metal connection layers, respectively;
步骤10，在金属层上淀积和刻蚀，形成金属电极。In step 10, a metal electrode is formed by depositing and etching on the metal layer.
介质层的厚度为500-2000埃，介质层台阶淀积台阶覆盖率>90％，材料为LPCVD SiO2和或LPCVD SiN。The thickness of the dielectric layer is 500-2000 angstroms, the step coverage of the dielectric layer is >90%, and the material is LPCVD SiO2 and or LPCVD SiN.
本发明所达到的有益效果：本发明采用多晶硅刻蚀后淀积一层台阶覆盖率高的介质层作为注入阻挡层，解决了光刻对位精度问题，可以实现0.25um以下栅长的自对准注入；同时采用金属连接层将源极从表面连接至衬底，金属连接层工艺在器件形成后进行，从而可以实现0.25um以下的栅长，制造良率和均匀性都可以得到保障。The invention achieves the beneficial effects that the invention adopts a dielectric layer with high step coverage to deposit as a implantation barrier layer after polysilicon etching, solves the problem of lithography alignment precision, and can realize self-alignment of gate length below 0.25 um. Quasi-injection; at the same time, the metal connection layer is used to connect the source from the surface to the substrate, and the metal connection layer process is performed after the device is formed, so that the gate length of 0.25 um or less can be realized, and the manufacturing yield and uniformity can be ensured.
附图说明DRAWINGS
图1为LDMOS器件的结构示意图。Figure 1 is a schematic diagram of the structure of an LDMOS device.
图2为多晶硅栅形成。Figure 2 shows the formation of a polysilicon gate.
图3为淀积形成介质层。Figure 3 is a deposition forming dielectric layer.
图4为N-偏移区注入。 Figure 4 shows the N-offset region implant.
图5为P型注入。Figure 5 shows a P-type implant.
图6为N+注入。Figure 6 shows the N+ injection.
图7为介质层刻蚀形成侧墙。Figure 7 is a dielectric layer etched to form a sidewall.
图8为P型连接层形成。Figure 8 shows the formation of a P-type tie layer.
图9为硅化物制作。Figure 9 shows the silicide fabrication.
图10为金属层形成。Figure 10 shows the formation of a metal layer.
图11为引线孔和金属连接层形成。Figure 11 shows the formation of lead holes and metal tie layers.
具体实施方式detailed description
下面结合附图对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。The invention is further described below in conjunction with the drawings. The following examples are only intended to more clearly illustrate the technical solutions of the present invention, and are not intended to limit the scope of the present invention.
如图1所示，一种LDMOS器件结构，包括金属连接层41，金属连接层41将LDMOS器源极24从表面连接至衬底11，金属连接层41材料为钨或铜，采用Ti/TiN作为接触层和阻挡层，沟道为浓度渐变沟道，沟道为P型沟道，沟道靠近源极24一侧浓度高，LDMOS器件的栅长为90-250nm。As shown in FIG. 1, an LDMOS device structure includes a metal connection layer 41. The metal connection layer 41 connects the LDMOS device source 24 from the surface to the substrate 11. The metal connection layer 41 is made of tungsten or copper, and Ti/TiN is used. As the contact layer and the barrier layer, the channel is a gradient-graded channel, the channel is a P-type channel, and the channel has a high concentration on the side close to the source 24, and the gate length of the LDMOS device is 90-250 nm.
一种LDMOS器件结构的制作方法，包括以下步骤：A method for fabricating an LDMOS device structure includes the following steps:
步骤1，栅氧和栅淀积；Step 1, gate oxide and gate deposition;
步骤2，栅刻蚀和N型漂移区注入后，在表面淀积一层介质层34’，介质层34’的厚度为500-2000埃，介质层34’台阶淀积台阶覆盖率>90％，材料为LPCVD SiO2和或LPCVD SiN；Step 2, after gate etching and N-type drift region implantation, depositing a dielectric layer 34' on the surface, the dielectric layer 34' has a thickness of 500-2000 angstroms, and the dielectric layer 34' step deposition step coverage is >90%. , the material is LPCVD SiO2 and or LPCVD SiN;
步骤3，自对准P型注入，退火形成浓度渐变沟道；Step 3, self-aligning P-type implantation, annealing to form a concentration gradient channel;
步骤4，浓N型注入，形成源极24和漏极23；Step 4, rich N-type implantation, forming source 24 and drain 23;
步骤5，介质层34’刻蚀，在栅两侧形成侧墙34；Step 5, the dielectric layer 34' is etched, forming side walls 34 on both sides of the gate;
步骤6，自对准浓P性注入，形成P型连接层；Step 6, self-aligning concentrated P-injection to form a P-type connection layer;
步骤7，硅化物制作和法拉第屏蔽层制作；Step 7, silicide fabrication and Faraday shield fabrication;
步骤8，介质层34’淀积和平坦化，形成金属层51；Step 8, the dielectric layer 34' is deposited and planarized to form a metal layer 51;
步骤9，介质层34’引线孔和硅通孔刻蚀后金属填充，分别形成引线柱42和金属连接层41；Step 9, the dielectric layer 34' lead hole and the through silicon via etched metal after filling, forming the lead post 42 and the metal connection layer 41;
步骤10，在金属层51上淀积和刻蚀，形成金属电极61。 In step 10, a metal electrode 61 is formed by depositing and etching on the metal layer 51.
如图2-11所示，为制作过程的具体实施例；As shown in Figure 2-11, it is a specific embodiment of the manufacturing process;
其中，如图2所示，衬底11上为P型外延层12，在外延层12上热氧化生长一层栅氧化层31，栅氧化层31上淀积一层多晶硅，光刻刻蚀形成多晶硅栅32。为降低多晶硅栅32电阻，也可以淀积多晶硅和硅化物形成栅电极。As shown in FIG. 2, the substrate 11 is a P-type epitaxial layer 12, a gate oxide layer 31 is thermally oxidized on the epitaxial layer 12, and a polysilicon is deposited on the gate oxide layer 31. Polysilicon gate 32. To reduce the resistance of the polysilicon gate 32, polysilicon and silicide may also be deposited to form a gate electrode.
如图3所示，多晶硅栅32形成后淀积一层介质层34’，该介质层34’需要具有良好的台阶覆盖率，台阶覆盖率大于90％。As shown in Fig. 3, after the polysilicon gate 32 is formed, a dielectric layer 34' is deposited, which dielectric layer 34' needs to have good step coverage, and the step coverage is greater than 90%.
如图4所示，硅片表面注入磷或砷，形成一层N型层21’，注入剂量为5E11～5E12。As shown in Fig. 4, phosphorus or arsenic is implanted into the surface of the silicon wafer to form an N-type layer 21' at an implantation dose of 5E11 to 5E12.
如图5所示，光刻胶41将漏极23区域挡住，多晶硅栅32和介质层34’作为自对准注入阻挡层，注入B+，注入剂量为2E13-5E14，形成P阱22’。As shown in Fig. 5, the photoresist 41 blocks the drain 23 region, and the polysilicon gate 32 and the dielectric layer 34' serve as a self-aligned implant barrier layer, implanting B+, and implanting a dose of 2E13-5E14 to form a P well 22'.
如图6所示，在源极24和漏极23注入砷，剂量为1E15-4E15，然后退火。P阱22’和N型层21’退火后分别形成P阱22和N型漂移区21。As shown in FIG. 6, arsenic is implanted at source 24 and drain 23 at a dose of 1E15-4E15 and then annealed. The P well 22' and the N type layer 21' are annealed to form a P well 22 and an N type drift region 21, respectively.
如图7所示，介质层34’刻蚀形成侧墙34。As shown in Figure 7, dielectric layer 34' is etched to form spacers 34.
如图8所示，光刻胶41将漏极23区挡住，多晶硅32和侧墙34作为自对准注入阻挡层，注入B+后快速退火形成P型连接层25。As shown in FIG. 8, the photoresist 41 blocks the drain 23 region, and the polysilicon 32 and the sidewall spacer 34 serve as a self-aligned implant barrier layer, and B+ is implanted and then rapidly annealed to form a P-type connection layer 25.
如图9所示，在源极24和P型连接层25表面形成硅化物33。As shown in FIG. 9, a silicide 33 is formed on the surface of the source electrode 24 and the P-type connection layer 25.
如图10所示，场板35制作，淀积并平坦化形成金属层51As shown in FIG. 10, the field plate 35 is formed, deposited and planarized to form a metal layer 51.
如图11所示，引线孔和硅通孔刻蚀后填充，形成引线柱42和金属连接层41，一般采用Ti/TiN作为接触层和阻挡层，采用钨作为金属填充。As shown in FIG. 11, the lead holes and the through silicon vias are etched and filled to form the lead post 42 and the metal connection layer 41. Ti/TiN is generally used as the contact layer and the barrier layer, and tungsten is used as the metal filling.
最后，在金属层51上淀积和刻蚀形成金属电极61Finally, a metal electrode 61 is deposited and etched on the metal layer 51.
本发明采用多晶硅刻蚀后淀积一层台阶覆盖率高的介质层作为注入阻挡层，解决了光刻对位精度问题，可以实现0.25um以下栅长的自对准注入；同时采用金属连接层将源极从表面连接至衬底，金属连接层工艺在器件形成后进行，从而可以实现0.25um以下的栅长，制造良率和均匀性都可以得到保障。The invention adopts a dielectric layer with high step coverage to deposit as a implantation barrier layer after polysilicon etching, solves the problem of lithography alignment precision, can realize self-aligned implantation of gate length below 0.25 um, and adopts metal connection layer The source is connected from the surface to the substrate, and the metal connection layer process is performed after the device is formed, so that the gate length of 0.25 um or less can be achieved, and the manufacturing yield and uniformity can be ensured.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变形，这些改进和变形也应视为本发明的保护范围。 The above is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention. It should also be considered as the scope of protection of the present invention.

Claims (6)

  1. 一种LDMOS器件结构，其特征在于：包括金属连接层，所述金属连接层将LDMOS器源极从表面连接至衬底，所述LDMOS器件的沟道为浓度渐变沟道。An LDMOS device structure is characterized by comprising a metal connection layer connecting a LDMOS device source from a surface to a substrate, the channel of the LDMOS device being a concentration gradient channel.
  2. 根据权利要求1所述的一种LDMOS器件结构，其特征在于：所述LDMOS器件的栅长为90-250nm。The LDMOS device structure according to claim 1, wherein the LDMOS device has a gate length of 90-250 nm.
  3. 根据权利要求1所述的一种LDMOS器件结构，其特征在于：金属连接层材料为钨或铜。The LDMOS device structure according to claim 1, wherein the metal connection layer material is tungsten or copper.
  4. 根据权利要求1所述的一种LDMOS器件结构，其特征在于：沟道为P型沟道，沟道靠近源极一侧浓度高。The LDMOS device structure according to claim 1, wherein the channel is a P-type channel, and the channel has a high concentration near the source side.
  5. 基于权利要求1所述的一种LDMOS器件结构的制作方法，其特征在于：包括以下步骤，A method for fabricating an LDMOS device structure according to claim 1, comprising the steps of:
    步骤1，栅氧和栅淀积；Step 1, gate oxide and gate deposition;
    步骤2，栅刻蚀和N型漂移区注入后，在表面淀积一层介质层；Step 2, after the gate etching and the N-type drift region are implanted, depositing a dielectric layer on the surface;
    步骤3，自对准P型注入，退火形成浓度渐变沟道；Step 3, self-aligning P-type implantation, annealing to form a concentration gradient channel;
    步骤4，浓N型注入，形成源极和漏极；Step 4, dense N-type implantation to form a source and a drain;
    步骤5，介质层刻蚀，在栅两侧形成侧墙；Step 5, the dielectric layer is etched, and sidewalls are formed on both sides of the gate;
    步骤6，自对准浓P性注入，形成P型连接层；Step 6, self-aligning concentrated P-injection to form a P-type connection layer;
    步骤7，硅化物制作和法拉第屏蔽层制作；Step 7, silicide fabrication and Faraday shield fabrication;
    步骤8，介质层淀积和平坦化，形成金属层；Step 8, the dielectric layer is deposited and planarized to form a metal layer;
    步骤9，介质层引线孔和硅通孔刻蚀后金属填充，分别形成引线孔和金属连接层；Step 9. The dielectric layer lead holes and the through silicon vias are etched and metal-filled to form lead holes and metal connection layers, respectively;
    步骤10，在金属层上淀积和刻蚀，形成金属电极。In step 10, a metal electrode is formed by depositing and etching on the metal layer.
  6. 根据权利要求5所述的基于权利要求1所述的一种LDMOS器件结构的制作方法，其特征在于：介质层的厚度为500-2000埃，介质层台阶淀积台阶覆盖率>90％，材料为LPCVD SiO2和或LPCVD SiN。 The method for fabricating an LDMOS device structure according to claim 5, wherein the dielectric layer has a thickness of 500-2000 angstroms, and the dielectric layer step deposition step coverage is >90%. It is LPCVD SiO2 and or LPCVD SiN.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538441A (en) * 2014-07-03 2015-04-22 上海华虹宏力半导体制造有限公司 Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN105047716A (en) * 2015-06-10 2015-11-11 上海华虹宏力半导体制造有限公司 RF LDMOS device and manufacturing method thereof
CN105374879A (en) * 2015-11-16 2016-03-02 上海华虹宏力半导体制造有限公司 Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03175678A (en) * 1989-12-04 1991-07-30 Sharp Corp Manufacture of semiconductor device
JP2006140447A (en) * 2004-10-14 2006-06-01 Renesas Technology Corp Semiconductor device and method of manufacturing the same
CN104425588B (en) * 2013-08-20 2017-06-06 上海华虹宏力半导体制造有限公司 RFLDMOS devices and its manufacture method
CN205723553U (en) * 2016-06-14 2016-11-23 张路非 A kind of metallurgical bonding glass sealed diode structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538441A (en) * 2014-07-03 2015-04-22 上海华虹宏力半导体制造有限公司 Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN105047716A (en) * 2015-06-10 2015-11-11 上海华虹宏力半导体制造有限公司 RF LDMOS device and manufacturing method thereof
CN105374879A (en) * 2015-11-16 2016-03-02 上海华虹宏力半导体制造有限公司 Radio frequency laterally diffused metal oxide semiconductor (LDMOS) device

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