CN104979404A - Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen - Google Patents
Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen Download PDFInfo
- Publication number
- CN104979404A CN104979404A CN201510267184.2A CN201510267184A CN104979404A CN 104979404 A CN104979404 A CN 104979404A CN 201510267184 A CN201510267184 A CN 201510267184A CN 104979404 A CN104979404 A CN 104979404A
- Authority
- CN
- China
- Prior art keywords
- field oxide
- region
- drift region
- raceway groove
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 13
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 title abstract description 5
- 239000001301 oxygen Substances 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000009826 distribution Methods 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 25
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
The present invention provides a novel super junction lateral double-diffused metal oxide semiconductorfield-effect transistor (SJ-LDMOS) with ladder field oxygen. The novel super-junction lateral double-diffused metal oxide semiconductorfield-effect transistor comprises an SJ layer formed on the surface of an LDMOS drifting region; and a novel semiconductor device of a ladder field oxidization layer is formed above Super Junction by using a two-step shallow slot isolation technology. On one hand, the distribution of an electric field on the surface is more uniform by using electric field regulating effect, so that the breakdown voltage of the device is increased; and on the other hand, the thickness of a thinner oxidized layer, close to a device channel, of the ladder field oxidization layer is smaller so that more majority carriers are accumulated on the surface of the drifting region under a field plate at an open status, and a vertical current channel of the device under the thin ladder oxidization layer becomes wide, and furthermore, the conducting resistance of the device is greatly reduced.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of lateral double diffusion metal oxide semiconductor field effect transistor.
Background technology
Superjunction SJ (Super Junction) technology is applied to LDMOS (Lateral Double-diffusedMOSFET) and forms the focus that SJ-LDMOS structure is LDMOS device research.Because SJ-LDMOS has low-down conducting resistance R under certain puncture voltage BV (Breakdown Voltage) condition
oN, broken the limit relation of conventional power MOS device, be widely used in super low-power consumption PIC (Power Integrated Circuit) design.But many problems are encountered in the process of SJ-LDMOS realization, comprise substrate-assisted depletion effect SAD (Substrate Assisted Depletion), namely the SJ-LDMOS realized in P-type silicon substrate, because N post drift region is simultaneously by adjacent P post and P type substrate assisted depletion, cause the electric charge of Super Junction can not full remuneration, cause BV significantly to reduce.
There is the impact that resilient coating (Buffer) SJ-LDMOS structure can reduce substrate-assisted depletion effectively, and this structure and traditional B CD (Bipolar-CMOS-DMOS) process compatible.In traditional BCD technique, when manufacturing isolating oxide layer between Buffer SJ-LDMOS drift region field oxygen and device, adopt local oxidation of silicon LOCOS (Local Oxidation of Silicon) technology.Because the high-temperature technology of LOCOS can make the N post of superjunction seriously increase with the counterdiffusion of P post phase on the one hand, the effect of inhaling boron row phosphorus in the process on the other hand due to field oxide growth makes the N post of superjunction not identical with P post concentration, cause electric charge can not full remuneration, thus make the electrology characteristic of device poor.
Shallow-trench isolation STI (Shallow Trench Isolation) technology working temperature compared with LOCOS technology is lower, can overcome the above problems well.But in employing STI BCD manufacture technics SJ-LDMOS process, in order to reduce process costs, on drift region the thickness of field oxide be by device between the isolation degree of depth determine, the performance of SJ-LDMOS receives the restriction of device BCD technique.Although the thick field oxide layer between device meets the condition of isolation, the performance of device is not well optimized, and while raising device withstand voltage, conduction resistance also increases considerably.
Summary of the invention
The present invention proposes a kind of lateral double diffusion metal oxide semiconductor field effect transistor, be intended to the contradiction effectively optimizing SJ-LDMOS puncture voltage and conduction resistance.
Technical scheme of the present invention is as follows:
Cross bimoment, comprising:
The substrate of semi-conducting material;
The epitaxial loayer grown over the substrate, as resilient coating;
Form adjacent base and drift region on said epitaxial layer there, N post is injected in drift region and P post forms superjunction drift region alternately;
Be positioned at field oxide adjacent on superjunction drift region and drain region, wherein field oxide and raceway groove keep spacing;
The raceway groove that described base utilizes double diffusion technique to be formed, described base is formed channeled substrate contact and forms source region with near raceway groove side short circuit;
Be positioned at the gate insulation layer above raceway groove and grid;
The source electrode formed on source region and drain region respectively and drain electrode;
On architecture basics same as the prior art above, structural change of the present invention mainly:
Described field oxide is notch cuttype, is namely wherein the more shallow thin field oxide of the degree of depth near the region of raceway groove, near and the region in adjacent drain region be the darker thick field oxide layer of the degree of depth; Described gate insulation layer and grid extend and are covered to the part of thin field oxide above raceway groove.
Based on above-mentioned basic scheme, the present invention also does following optimization further and limits and improve:
When the thickness of thin field oxide is about 1/2 of the thickness of thick field oxide layer, the characteristic of device is optimum.
The thick field oxide layer of ladder field oxide designs specific thickness according to the concrete requirement of withstand voltage of device, and such as: when device withstand voltage is 100 ~ 300V, the thickness of thick field oxide layer is about 1 μm; When device withstand voltage is 300 ~ 700V, the thickness of thick field oxide layer is about 1.5 μm.
When the ladder corner location of ladder field oxide is near the centre position of device drift region, the best performance of device.
Accordingly, the special feature making the method for field effect transistor device of the present invention is just: when being formed with source region, first utilize near the region of raceway groove the thin field oxide that STI technology Formation Depth is more shallow on surface, superjunction drift region, ensure that gate insulation layer and grid extend above raceway groove and be covered to the part of thin field oxide; Then at the thick field oxide layer that surface, superjunction drift region utilizes STI technology Formation Depth darker near the mutually isolated place between the region of drain terminal and multiple described lateral double diffusion metal oxide semiconductor field effect transistor (note: usually making such devices is all that multiple device makes jointly), namely stair-stepping field oxide is formed on the surface of superjunction drift region.
The beneficial effect of technical solution of the present invention is as follows:
The present invention forms Super Junction on surface, the drift region of LDMOS, reduces the conducting resistance of drift region on the one hand; Eliminate substrate-assisted depletion effect on the other hand, make device have very high puncture voltage.Above device drift region, forming ladder field oxide, is the improvement and bring new ideas to conventional Drift district having single monolayer thick oxide layer SJ-LDMOS.
Ladder field oxide is formed by two step STI technology on the surface of SJ-LDMOS drift region.On the one hand, the surface field of ladder field oxide to device drift region is modulated, and makes the surface electric field distribution of drift region more even, thus effectively raises device electric breakdown strength.On the other hand, because the field oxide near raceway groove place is thinning, there is the majority-carrier accumulation of higher concentration in the surface, drift region in the on state below field plate, and the current channel on the oxide layer underlying device longitudinal direction of thinner rank broadens, thus reduce the conducting resistance of device significantly, the overall performance of device is optimized.
Accompanying drawing explanation
Fig. 1 is the structural representation (front view) of the embodiment of the present invention;
Fig. 2 is the three-dimensional sectional schematic diagram (for the ease of mark, having made part isometric section to superjunction, drift region insulating layer and ladder field oxide etc.) of the embodiment of the present invention;
Drawing reference numeral illustrates:
1-source electrode; 2-grid, comprises the field plate extending to field oxide upper section and formed; 3-gate insulation layer; 4-ladder field oxide; 5-drain electrode; 6-drain region; The superjunction drift region of 7-N post formation alternate with P post; 8-resilient coating; 9-substrate; 10-base; 11-source region; 12-raceway groove;
Embodiment
As shown in Figure 1, the lateral double diffusion metal oxide semiconductor field-effect tube structure that the present invention has ladder field oxygen comprises:
The substrate 9 of semi-conducting material;
Be positioned at the resilient coating 8 of the epitaxial loayer on substrate as device;
Laying respectively at base 10 and the drain region 6 at two ends on resilient coating 8, is drain electrode 5 above drain region;
Be positioned at source region 11 and the raceway groove 12 of base region surface;
Area surface forms source electrode 1, and raceway groove 12 is positioned at below grid 2 for gate insulation layer 3 above;
Between raceway groove and drain region, surface, drift region forms N post and P post superjunction drift region 7 alternately;
It is ladder field oxide 4 above superjunction drift region 7;
The thickness of thin field oxide is 41, and the thickness of thick field oxide layer is 42.
Form Super Junction layer on the surface of LDMOS drift region, effectively can reduce the conducting resistance of drift region.Again owing to being resilient coating below Super Junction, effectively can solve substrate-assisted depletion effect, make device have very high puncture voltage.In order to the characteristic of further optimised devices, solve the problem that field oxide thickness is subject to isolating oxide layer thickness limits between device, utilize two step STI technology to form ladder field oxide on superjunction drift region.According to Electric Field Modulated principle, the electric field of ladder field oxide to surface, drift region is modulated, and makes its Electric Field Distribution more even, further increases the puncture voltage of device.Again because the thin field oxide thickness near raceway groove is less, increase in the concentration of the most current-carrying accumulation of surface, drift region field plate lower zone, and broaden at the guiding path of thin field oxide low-side current, thus reduce the conducting resistance of device significantly.
For N raceway groove LDMOS, specifically can be prepared by following steps:
1) extension N-type resilient coating on the substrate of semi insulating material (comprising Si, SiC and GaAs etc.);
2) left end forms P type base on the buffer layer;
3) inject N post and the P post of some high concentrations alternately from base to drain region, form superjunction drift region;
4) utilize two step STI technology, be formed with source region and on superjunction drift region, form ladder field oxide simultaneously; The ladder corner location of field oxide is the point midway of superjunction drift region; Wherein, the thickness of thin field oxide is 1/2 of the thickness of thick field oxide layer; When requirement of withstand voltage is 100 ~ 300V, the thickness of thick field oxide layer is 1 μm; When requirement of withstand voltage is 300 ~ 700V, the thickness of thick field oxide layer is 1.5 μm;
5) on raceway groove, form gate oxide and depositing polysilicon, etch polysilicon and gate oxide, form grid;
6) utilize in base double diffusion technique to inject and form raceway groove, inject at right-hand member simultaneously and form drain region;
7) channeled substrate contact is formed at base left end;
8) at device surface deposit passivation layer, and contact hole is etched;
9) depositing metal also etching formation drain electrode and source electrode.
Through experiment, the performance of this device compares to traditional devices and significantly promotes, and when two kinds of device drift region length are identical, the puncture voltage of this device improves about 25%; When two kinds of device electric breakdown strengths are identical, conduction resistance declines about 30%.
Certainly, the LDMOS in the present invention also can be P type raceway groove, and its structure is equal to N raceway groove LDMOS, also should belong to the protection range of the application's claim, not repeat them here.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these schemes of improving and replacing also fall into protection scope of the present invention.
Claims (5)
1. a cross bimoment, comprising:
The substrate of semi-conducting material;
The epitaxial loayer grown over the substrate, as resilient coating;
Form adjacent base and drift region on said epitaxial layer there, N post is injected in drift region and P post forms superjunction drift region alternately;
Be positioned at field oxide adjacent on superjunction drift region and drain region, wherein field oxide and raceway groove keep spacing;
The raceway groove that described base utilizes double diffusion technique to be formed, described base is formed channeled substrate contact and forms source region with near raceway groove side short circuit;
Be positioned at the gate insulation layer above raceway groove and grid;
The source electrode formed on source region and drain region respectively and drain electrode;
It is characterized in that:
Described field oxide is notch cuttype, is namely wherein the more shallow thin field oxide of the degree of depth near the region of raceway groove, near and the region in adjacent drain region be the darker thick field oxide layer of the degree of depth; Described gate insulation layer and grid extend and are covered to the part of thin field oxide above raceway groove.
2. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, is characterized in that: the thickness of thin field oxide is 1/2 of the thickness of thick field oxide layer.
3. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, is characterized in that: when requirement of withstand voltage is 100 ~ 300V, and the thickness of thick field oxide layer is 1 μm; When requirement of withstand voltage is 300 ~ 700V, the thickness of thick field oxide layer is 1.5 μm.
4. lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, is characterized in that: the ladder corner location of described field oxide is the point midway of superjunction drift region.
5. make a method for lateral double diffusion metal oxide semiconductor field effect transistor according to claim 1, comprise the following steps:
1) epitaxial buffer layer on the substrate of semi-conducting material;
2) left end forms base on the buffer layer;
3) from base to right-hand member, superjunction drift region is generated, i.e. the N post of alter least-squares high concentration and P post;
4) be formed with source region and on superjunction drift region, form field oxide simultaneously;
5) on raceway groove, form gate oxide and depositing polysilicon, etch polysilicon and gate oxide, form grid;
6) utilize in base double diffusion technique to inject and form raceway groove, the right-hand member simultaneously in superjunction drift region injects and forms drain region;
7) channeled substrate contact is formed at base left end;
8) at whole surface deposition passivation layer, and contact hole is etched;
9) depositing metal also etching formation drain electrode and source electrode;
It is characterized in that:
When being formed with source region, first utilizing near the region of raceway groove the thin field oxide that STI technology Formation Depth is more shallow on surface, superjunction drift region, ensureing that gate insulation layer and grid extend above raceway groove and being covered to the part of thin field oxide; Then at the thick field oxide layer that surface, superjunction drift region utilizes STI technology Formation Depth darker near the mutually isolated place between the region and multiple described lateral double diffusion metal oxide semiconductor field effect transistor of drain terminal, namely stair-stepping field oxide is formed on the surface of superjunction drift region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510267184.2A CN104979404A (en) | 2015-05-22 | 2015-05-22 | Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510267184.2A CN104979404A (en) | 2015-05-22 | 2015-05-22 | Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104979404A true CN104979404A (en) | 2015-10-14 |
Family
ID=54275730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510267184.2A Pending CN104979404A (en) | 2015-05-22 | 2015-05-22 | Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979404A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108063158A (en) * | 2017-12-06 | 2018-05-22 | 重庆邮电大学 | A kind of LDMOS device with groove profile oxide layer and horizontal superjunction |
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
| CN109860276A (en) * | 2019-02-14 | 2019-06-07 | 长江存储科技有限责任公司 | Semiconductor devices and forming method thereof |
| CN111933713A (en) * | 2020-09-24 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN113228297A (en) * | 2021-02-25 | 2021-08-06 | 英诺赛科(苏州)科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN113990864A (en) * | 2021-12-28 | 2022-01-28 | 广州粤芯半导体技术有限公司 | Terminal structure layout of semiconductor device |
| CN114220849A (en) * | 2022-02-23 | 2022-03-22 | 江苏游隼微电子有限公司 | LDMOS device compatible with CMOS process |
| CN115084235A (en) * | 2022-07-25 | 2022-09-20 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method and chip |
| US20230207692A1 (en) * | 2020-10-29 | 2023-06-29 | United Microelectronics Corp. | High voltage semiconductor device including buried oxide layer |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100163992A1 (en) * | 2008-12-31 | 2010-07-01 | Kim Mi-Young | Semiconductor device and method for fabricating the same |
| US20100270616A1 (en) * | 2009-04-24 | 2010-10-28 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
| CN102244092A (en) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | Junction termination structure of transverse high-pressure power semiconductor device |
| CN102254946A (en) * | 2011-01-11 | 2011-11-23 | 苏州英诺迅科技有限公司 | Radio frequency transverse diffusion N-type Metal Oxide Semiconductor (MOS) tube and manufacturing method thereof |
| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
-
2015
- 2015-05-22 CN CN201510267184.2A patent/CN104979404A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100163992A1 (en) * | 2008-12-31 | 2010-07-01 | Kim Mi-Young | Semiconductor device and method for fabricating the same |
| US20100270616A1 (en) * | 2009-04-24 | 2010-10-28 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| CN101916779A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect |
| CN102254946A (en) * | 2011-01-11 | 2011-11-23 | 苏州英诺迅科技有限公司 | Radio frequency transverse diffusion N-type Metal Oxide Semiconductor (MOS) tube and manufacturing method thereof |
| CN102244092A (en) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | Junction termination structure of transverse high-pressure power semiconductor device |
| CN102361031A (en) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108063158A (en) * | 2017-12-06 | 2018-05-22 | 重庆邮电大学 | A kind of LDMOS device with groove profile oxide layer and horizontal superjunction |
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
| CN109860276B (en) * | 2019-02-14 | 2022-08-09 | 长江存储科技有限责任公司 | Semiconductor device and method of forming the same |
| CN109860276A (en) * | 2019-02-14 | 2019-06-07 | 长江存储科技有限责任公司 | Semiconductor devices and forming method thereof |
| CN111933713A (en) * | 2020-09-24 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN111933713B (en) * | 2020-09-24 | 2021-02-05 | 晶芯成(北京)科技有限公司 | Semiconductor device and method for manufacturing the same |
| US20230207692A1 (en) * | 2020-10-29 | 2023-06-29 | United Microelectronics Corp. | High voltage semiconductor device including buried oxide layer |
| CN113228297A (en) * | 2021-02-25 | 2021-08-06 | 英诺赛科(苏州)科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN113990864A (en) * | 2021-12-28 | 2022-01-28 | 广州粤芯半导体技术有限公司 | Terminal structure layout of semiconductor device |
| CN113990864B (en) * | 2021-12-28 | 2022-03-18 | 广州粤芯半导体技术有限公司 | Terminal structure layout of semiconductor device |
| CN114220849A (en) * | 2022-02-23 | 2022-03-22 | 江苏游隼微电子有限公司 | LDMOS device compatible with CMOS process |
| CN115084235A (en) * | 2022-07-25 | 2022-09-20 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method and chip |
| CN115084235B (en) * | 2022-07-25 | 2023-01-17 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104979404A (en) | Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen | |
| JP6640904B2 (en) | SiC semiconductor device having offset below trench | |
| TWI453919B (en) | Diode structures with controlled injection efficiency for fast switching | |
| US8659076B2 (en) | Semiconductor device structures and related processes | |
| CN110148629B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN109920854B (en) | MOSFET device | |
| CN107204372A (en) | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure | |
| CN103178093B (en) | The structure of high-voltage junction field-effect transistor and preparation method | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| TW202006956A (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
| CN107093622B (en) | Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with semi-insulating polycrystalline silicon layer | |
| CN104835836B (en) | A kind of lateral super-junction bilateral diffusion metal oxide semiconductor field-effect tube with dual field modulation | |
| CN108511528A (en) | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof | |
| CN104241348A (en) | Low-on-resistance SiC IGBT and manufacturing method thereof | |
| KR20210100547A (en) | Charge compensation mosfet with graded epi profile and methods of manufacturing thereof | |
| CN109087952A (en) | With low separate gate VDMOS device and manufacturing method than conducting resistance | |
| CN108538909A (en) | Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block | |
| KR20140044075A (en) | Semiconductor device and method manufacturing the same | |
| CN113594255A (en) | Groove type MOSFET device and preparation method thereof | |
| CN108565286B (en) | high-K dielectric groove transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN110047930A (en) | VDMOS device | |
| CN105870189A (en) | Lateral super-junction double-diffusion metal oxide semiconductor field effect transistor having bulk electric field modulation effect | |
| CN108258050A (en) | High K dielectric channel lateral super-junction bilateral diffusion metal oxide elemental semiconductor field-effect tube and preparation method thereof | |
| CN114664934B (en) | DMOS transistor with field plate and manufacturing method thereof | |
| CN103094124B (en) | The structure of fetron and manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151014 |
|
| RJ01 | Rejection of invention patent application after publication |