CN103236439B - VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in novel structure and manufacture method of VDMOS device - Google Patents
VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in novel structure and manufacture method of VDMOS device Download PDFInfo
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Abstract
The invention discloses a VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in a novel structure and a manufacture method of the VDMOS device. A first groove is formed in an active region, in addition, a thick insulation oxidation layer is grown on the inner wall of the first groove, the first groove is deeper than a cell groove, the depth of the first groove exceeds a half of the thickness of a first conducting type epitaxial layer of a semiconductor base plate, and the voltage withstanding requirement of the device is met. Meanwhile, a first metal is arranged above a first conducting polycrystalline silicon arranged in the first groove, the first metal is in equipotential electric connection with the first conducting polycrystalline silicon, and the voltage withstanding capability of the device is further improved. The VDMOS device and the manufacture method have the advantages that the first groove is introduced, and the voltage withstanding capability of the device is enhanced, so the epitaxial layer with lower electrical resistivity can be selected, and the device meets the higher voltage withstanding requirement and also has the lower feature on resistance at the same time.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially a kind of VDMOS device of new structure and manufacture method thereof.
Background technology
Tradition VDMOS(Vertical Double Diffusion MOS) drain-source withstand voltage (Vds) upper limit of device is generally no more than 1500V.At this wherein, the device within 200V is withstand voltage adopts the cellular of groove (Trench) structure usually, and object increases the cellular integrated level in unit are, thus effectively reduce the specific on-resistance (Rsp) of device; And the withstand voltage above device of 500V adopts the cellular of plane (Planar) structure usually, because the withstand voltage demand of cellular can be guaranteed like this.
In order to obtain lower specific on-resistance and higher drain-source is withstand voltage simultaneously, the power MOSFET device with superjunction (Super Junction) structure arises at the historic moment, it utilizes the P-N post in implant devices extension Withstand voltage layer to the two-dimentional pressure-resistance structure realizing electric field level-vertical, so both can meet device withstand voltage demand, the resistivity of device epitaxial layers can be reduced again simultaneously, therefore, the specific on-resistance of device is effectively reduced.
But superjunction power MOSFET device also has its inferior position, specifically comprise following two aspects:
1. the manufacturing process more complicated of superjunction power MOSFET device, technology stability, consistency are relatively poor.Being widely used in the superjunction MOS device manufacture method commercially produced has two kinds at present: 1). multilayer epitaxial growth method (Multi-epitaxial growth); 2). deep trench completion method (Deep trench filling).
The former forms the P-N post pair in epitaxial loayer by repeatedly epitaxial growth, photoetching and ion implantation, and device performance is very easy to the impact of the alignment precision being subject to epitaxial growth quality and photoetching and injection, and technological process is longer, and cost is very high; The latter fills the P-N post pair formed in epitaxial loayer by the extension in deep plough groove etched and deep trench, gash depth needs to reach 40um-50um usually, this is a very large challenge concerning etching groove equipment, simultaneously, deep trench is filled and is easily produced multiple physical imperfection, and the withstand voltage properties of device is affected.
2. superjunction power MOSFET device is widely used in the product in the withstand voltage scope of 500V-900V, and for the product in the withstand voltage scope of 200V-500V, it declines to a great extent to the contribution of device feature conducting resistance, even lose advantage, this is mainly because withstand voltage lower device, the proportion that epilayer resistance accounts for the overall conducting resistance of device (Rdson) is lower, and super-junction structure and non-best choice.
But, for the product in the withstand voltage scope of 200V-500V, traditional groove structure cell is difficult to again realize requirement of withstand voltage, in gash depth, groove, the thickness of insulated gate oxide layer all becomes the key factor affecting voltage endurance capability, therefore, the rarely seen groove VDMOS device reaching this kind of withstand voltage demand on market.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of VDMOS device and manufacture method thereof of new structure are provided, it both can meet the withstand voltage demand of the very inaccessible 200V-500V of conventional trench structures VDMOS device, the low specific on-resistance that conventional planar structure VDMOS device and hyperconjugation VDMOS device are difficult to realize in the withstand voltage scope of 200V-500V can be obtained again, and there is the manufacturing process of simple and stable.
Technical scheme of the present invention is as follows:
According to technical scheme provided by the present invention, a kind of VDMOS device of new structure, in the top plan view of described VDMOS device, comprise and be positioned at active area on semiconductor substrate and terminal protection district, described terminal protection district is around being surrounded by source region; The cellular that regular array is arranged is comprised in described active area; On the cross section of described VDMOS device, described semiconductor substrate comprises the first conductive type epitaxial layer being positioned at surface and the first conductivity type substrate layer be positioned at below substrate, described first conductive type epitaxial layer is connected with the first conductivity type substrate layer, the upper surface of described first conductive type epitaxial layer is the first interarea of semiconductor substrate, the lower surface of described first conductivity type substrate layer is the second interarea of semiconductor substrate, and the top of described first conductive type epitaxial layer is provided with the second conductive type layer; Second interarea of described semiconductor substrate is provided with drain metal;
On the cross section of described VDMOS device active area, the first groove is provided with in described first conductive type epitaxial layer, described first groove is extended vertically downward by the first interarea of semiconductor substrate, the degree of depth stretches in the first conductive type epitaxial layer below the second conductive type layer, described first trench wall superficial growth has insulating oxide, has in the first groove of insulating oxide be filled with the first conductive polycrystalline silicon in inwall growth;
On the cross section of described VDMOS device active area, the first insulating medium layer is coated with at described first groove notch, described first insulating medium layer is provided with the first contact hole, described first contact hole is positioned at above the first conductive polycrystalline silicon, in described first contact hole, be filled with the first metal, described first metal and the first conductive polycrystalline silicon equipotential are electrically connected;
On the cross section of described VDMOS device active area, cellular groove is provided with between every two adjacent the first grooves, described cellular groove is extended vertically downward by the first interarea of semiconductor substrate, the degree of depth stretches in the first conductive type epitaxial layer below the second conductive type layer, the superficial growth of described cellular trench wall has insulated gate oxide layer, have in the cellular groove of insulated gate oxide layer in inwall growth and be filled with the second conductive polycrystalline silicon, the second insulating medium layer is coated with at described cellular groove notch, the both sides of described cellular groove are provided with source contact openings, source metal is filled with in described source contact openings, the first conductivity type implanted region is provided with above the both sides outer wall that described cellular groove is corresponding, described source metal and the second conductive type layer and the first conductivity type implanted region ohmic contact.
Its further technical scheme is:
On the cross section of described VDMOS device active area, described first metal is not connected mutually with source metal.
On the cross section of described VDMOS device active area, the degree of depth of described first groove is greater than the degree of depth of cellular groove.
In addition, the present invention also provides a kind of manufacture method of VDMOS device of new structure, comprises the steps:
A () provides the semiconductor substrate with two opposing main faces, described semiconductor substrate comprises the first conductivity type substrate layer and is positioned at the first conductive type epitaxial layer above described first conductivity type substrate layer; Described two opposing main faces comprise the first interarea and the second interarea;
(b) on the first interarea of above-mentioned semiconductor substrate, deposit first groove hard mask layer;
C the first groove hard mask layer is optionally sheltered and etched to (), form the hard mask window of the first etching groove;
D () utilizes above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, forms the first groove, and described first gash depth is less than the first conductive type epitaxial layer thickness;
E () removes the first groove hard mask layer on the first interarea, on the first interarea and the first trench wall growth insulating oxide;
F () be deposit first conductive polycrystalline silicon on above-mentioned insulating oxide, described first conductive polycrystalline silicon fills the first groove that inwall growth has insulating oxide simultaneously;
G the first conductive polycrystalline silicon above () etching removal first interarea, obtains the first conductive polycrystalline silicon in the first groove;
Insulating oxide on (h) erosion removal first interarea;
(i) deposit cellular groove hard mask layer on the first interarea of semiconductor substrate;
J cellular groove hard mask layer is optionally sheltered and etched to (), form the hard mask window of cellular etching groove;
K () utilizes above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, and form cellular groove, described cellular groove is between the first groove, and the degree of depth is shallower than the first groove;
L () removes the cellular groove hard mask layer on the first interarea, on the first interarea and cellular trench wall growth insulated gate oxide layer;
M () be deposit second conductive polycrystalline silicon on above-mentioned insulated gate oxide layer, described second conductive polycrystalline silicon fills the cellular groove that inwall growth has insulated gate oxide layer simultaneously;
N the second conductive polycrystalline silicon above () etching removal first interarea, obtains the second conductive polycrystalline silicon in cellular groove;
O () is on the first interarea, autoregistration ion implantation second conductive type impurity ion, and the second conductive type layer being positioned at semiconductor substrate first conductive type epitaxial layer top is formed by high temperature knot, the degree of depth of described second conductive type layer is less than the second conductive polycrystalline silicon distance to downward-extension in cellular groove;
P (), on described first interarea, carries out source region photoetching, and inject the first conductive type impurity ion of high concentration, and is formed the first conductivity type implanted region be positioned at above the corresponding both sides outer wall of cellular groove by high temperature knot;
(q) on above-mentioned first interarea, deposit insulating medium layer;
R () carries out contact hole photoetching and etching on described insulating medium layer, thus the first contact hole is formed above the first groove notch, source contact openings is formed in cellular groove both sides, meanwhile, above the first groove notch He above cellular groove notch, the first insulating medium layer and the second insulating medium layer is formed respectively;
S () be deposited metal on described first insulating medium layer and on the second insulating medium layer, and described metal level fills the first contact hole and source contact openings;
T () carries out photoetching and etching on described metal level, form the first metal and source metal, the first conductive polycrystalline silicon equipotential in described first metal and the first groove is electrically connected, described source metal and the second conductive type layer and the first conductivity type implanted region ohmic contact;
U () be deposit drain metal on the second interarea of described semiconductor substrate.
Its further technical scheme is:
The material of described semiconductor substrate comprises silicon.
Described hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
Described insulating medium layer is silex glass USG, boron-phosphorosilicate glass BPSG or phosphorosilicate glass PSG.
The degree of depth of described first groove is greater than the degree of depth of cellular groove, and is the 50%-90% of semiconductor substrate first conductive type epitaxial layer thickness.
Insulating oxide layer thickness on described first trench wall is 2000A-10000A.
Note: in both above-mentioned " the first conduction type " and " the second conduction type ", for N-type VDMOS device, the first conduction type is N-type, and the second conduction type is P type; For P type VDMOS device, the first conduction type is just in time contrary with N type semiconductor device with the type of the second conduction type indication.
Advantageous Effects of the present invention is:
One, the present invention is provided with the first groove in active area, and the first trench wall growth has thick insulating oxide, simultaneously, the degree of depth of the first groove is far deeper than cellular groove, its degree of depth has exceeded the half of semiconductor substrate first conductive type epitaxial layer thickness, therefore, when VDMOS device turns off withstand voltage work, device drain applies a high potential relative to source electrode, first this high potential can make to be positioned near the first groove outer wall below the second conductive type layer and induce the second a large amount of conduction type electric charges, electric charge can make the first conductive type epitaxial layer between adjacent first trenches exhaust, form Withstand voltage layer, simultaneously, heavy insulation oxide layer on first trench wall is also withstand voltage together, so, as the cellular beneath trenches that coexists adds a horizontal Withstand voltage layer, thus meet the withstand voltage demand of device.
Two, the first metal is provided with above first conductive polycrystalline silicon of the present invention in the first groove, first metal and the first conductive polycrystalline silicon equipotential are electrically connected, when VDMOS device turns off withstand voltage work, first metal applies one with the bias voltage of drain potential identical polar, bias voltage size is lower than drain voltage, electric field strength in first conductive type epitaxial layer of the bias voltage meeting partial offset that first metal applies between adjacent first trenches below the second conductive type layer, and the peak electric field in this region is shifted to cellular channel bottom, like this, also can the voltage endurance capability of boost device further.
Three, VDMOS device of the present invention adds the voltage endurance capability of device by introducing the first groove, thus, break away from traditional VDMOS device and realize high withstand voltage mode by increase epilayer resistance rate and epitaxy layer thickness merely, thus the epitaxial loayer of more low-resistivity can be selected, therefore, device also has lower specific on-resistance while meeting higher withstand voltage demand.
Four, in structure of the present invention, the manufacturing process forming structure cell all realizes by means of widely used semiconductor fabrications, does not increase process implementing difficulty and cost, therefore, is beneficial to and promotes and batch production.
Accompanying drawing explanation
Fig. 1 is the vertical view of VDMOS device of the present invention.
Fig. 2 is the active area cross section view of VDMOS device of the present invention.
Fig. 3 ~ Figure 17 is the cutaway view in the concrete implementing process of VDMOS device of the present invention each stage, wherein:
Fig. 3 is the cutaway view of semiconductor substrate.
Fig. 4 is the cutaway view after the hard mask open of formation first groove.
Fig. 5 is the cutaway view after formation first groove.
Fig. 6 is the cutaway view after growth insulating oxide.
Fig. 7 is the cutaway view after etching first conductive polycrystalline silicon.
Fig. 8 is the cutaway view on removal first interarea after insulating oxide.
Fig. 9 is the cutaway view after forming the hard mask open of cellular groove.
Figure 10 is the cutaway view after forming cellular groove.
Figure 11 is the cutaway view after growth insulated gate oxide layer.
Figure 12 is the cutaway view after etching second conductive polycrystalline silicon.
Figure 13 is the cutaway view after formation second conductive type layer.
Figure 14 is the cutaway view behind formation first conductivity type implanted region.
Figure 15 is the cutaway view after forming source contact openings and the first contact hole.
Figure 16 is the cutaway view after formation first metal and source metal.
Figure 17 is the cutaway view after forming drain metal.
Figure 18 does not apply positive bias and applies the correspondence position that certain specifies peak electric field under positive bias two kinds of different situations on the first metal.
Figure 19 is drain-source withstand voltage (BVdss) change curve corresponding apply different positive bias on the first metal after.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.
As shown in Figure 1, in the top plan view of VDMOS device, comprise the active area being positioned at semiconductor substrate center and the terminal protection district being positioned at outer ring, described active area, in described active area, comprise some regular array and cellular arranged in parallel.
As shown in Figure 2, on the cross section of VDMOS device, described semiconductor substrate comprises N-type epitaxy layer and is positioned at the N+ substrate layer below described N-type epitaxy layer, and described N+ substrate layer adjoins N-type epitaxy layer, and the concentration of N+ substrate layer is greater than the concentration of N-type epitaxy layer.The top of described N-type epitaxy layer is provided with P well layer.
On the cross section of described VDMOS device active area, described N-type epitaxy layer top is provided with the first groove, described first groove is positioned at P well layer, the degree of depth stretches in the N-type epitaxy layer below P well layer, first gash depth is about in 50%-90%(the present embodiment of N-type epitaxy layer thickness gets 70%), described first trench wall superficial growth has insulating oxide, described insulating oxide layer thickness is get 8000A in 2000A-10000A(the present embodiment), have in the first groove of insulating oxide in inwall growth and be filled with the first conductive polycrystalline silicon.
On the cross section of described VDMOS device active area, the first insulating medium layer is coated with at described first groove notch, described first insulating medium layer is provided with the first contact hole, described first contact hole is positioned at above the first conductive polycrystalline silicon, in described first contact hole, be filled with the first metal, described first metal and the first conductive polycrystalline silicon equipotential are electrically connected.
On the cross section of described VDMOS device active area, cellular groove is provided with between every two adjacent the first grooves, described cellular groove is positioned at P well layer, the degree of depth stretches in the N-type epitaxy layer below P well layer, the degree of depth of cellular groove is less than the degree of depth of the first groove, the superficial growth of described cellular trench wall has insulated gate oxide layer, have in the cellular groove of insulated gate oxide layer in inwall growth and be filled with the second conductive polycrystalline silicon, the second insulating medium layer is coated with at described cellular groove notch, the both sides of described cellular groove are provided with source contact openings, source metal is filled with in described source contact openings, N+ type injection region is provided with above the both sides outer wall that described cellular groove is corresponding, the doping content of described N+ type injection region is higher than the concentration of N-type epitaxy layer, described source metal and P well layer and N+ type injection region ohmic contact.
On the cross section of described VDMOS device active area, described first metal is not connected mutually with source metal.
On the cross section of described VDMOS device active area, the N+ substrate layer surface of described semiconductor substrate is provided with drain metal.
The VDMOS device of said structure, is formed by following processing step manufacture:
Step a, provide the semiconductor substrate with two opposing main faces, described semiconductor substrate comprises the first conductivity type substrate layer and is positioned at the first conductive type epitaxial layer above described first conductivity type substrate layer; Described two opposing main faces comprise the first interarea and the second interarea; As shown in Figure 3.
Surface corresponding to described N-type epitaxy layer forms the first interarea, and the surface that N+ substrate layer is corresponding forms the second interarea; Described N+ substrate layer adjoins N-type epitaxy layer; The material of semiconductor substrate comprises silicon; As shown in Figure 3.
Step b, on the first interarea of above-mentioned semiconductor substrate, deposit first groove hard mask layer; As shown in Figure 4.
Step c, optionally shelter and etch the first groove hard mask layer, form the hard mask window of the first etching groove; As shown in Figure 4.
Steps d, utilize above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, forms the first groove, and described first gash depth is less than the first conductive type epitaxial layer thickness; As shown in Figure 5.
Step e, the first groove hard mask layer removed on the first interarea, on the first interarea and the first trench wall growth insulating oxide, described insulating oxide layer thickness is 8000A; As shown in Figure 6.
Step f, on above-mentioned insulating oxide deposit first conductive polycrystalline silicon, described first conductive polycrystalline silicon fills inwall growth simultaneously the first groove of insulating oxide; As shown in Figure 7.
The first conductive polycrystalline silicon above step g, etching removal first interarea, obtains the first conductive polycrystalline silicon in the first groove; As shown in Figure 7.
Insulating oxide on step h, erosion removal first interarea; As shown in Figure 8.
Step I, on the first interarea of semiconductor substrate deposit cellular groove hard mask layer; As shown in Figure 9.
Step j, optionally shelter and etch cellular groove hard mask layer, form the hard mask window of cellular etching groove; As shown in Figure 9.
Step k, utilize above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, form cellular groove, described cellular groove is between the first groove, and the degree of depth is shallower than the first groove; As shown in Figure 10.
Step l, the cellular groove hard mask layer removed on the first interarea, on the first interarea and cellular trench wall growth insulated gate oxide layer; As shown in figure 11.
Step m, on above-mentioned insulated gate oxide layer deposit second conductive polycrystalline silicon, described second conductive polycrystalline silicon fills inwall growth simultaneously the cellular groove of insulated gate oxide layer; As shown in figure 12.
The second conductive polycrystalline silicon above step n, etching removal first interarea, obtains the second conductive polycrystalline silicon in cellular groove; As shown in figure 12.
Step o, on the first interarea, autoregistration ion implantation p type impurity ion, and the P well layer being positioned at semiconductor substrate N-type epitaxy layer top is formed by high temperature knot, the degree of depth of described P well layer is less than the second conductive polycrystalline silicon distance to downward-extension in cellular groove; As shown in figure 13.
Step p, on described first interarea, carry out source region photoetching, and inject the N-type impurity ion of high concentration, and formed the N+ type injection region be positioned at above the corresponding both sides outer wall of cellular groove by high temperature knot; As shown in figure 14.
Step q, on above-mentioned first interarea, deposit insulating medium layer; As shown in figure 15.
Step r, on described insulating medium layer, carry out contact hole photoetching and etching, thus the first contact hole is formed above the first groove notch, source contact openings is formed in cellular groove both sides, meanwhile, above the first groove notch He above cellular groove notch, the first insulating medium layer and the second insulating medium layer is formed respectively; As shown in figure 15.
Step s, deposited metal on described first insulating medium layer and on the second insulating medium layer, and described metal level fills the first contact hole and source contact openings; As shown in figure 16.
Step t, on described metal level, carry out photoetching and etching, form the first metal and source metal, the first conductive polycrystalline silicon equipotential in described first metal and the first groove is electrically connected, described source metal and P well layer and N+ type injection region ohmic contact; As shown in figure 16.
Step u, on the second interarea of described semiconductor substrate deposit drain metal; As shown in figure 17.
The working mechanism of VDMOS device of the present invention is: in the active area of described device, be provided with the first groove, and the first trench wall growth has thick insulating oxide, simultaneously, the degree of depth of the first groove is far deeper than cellular groove, and its degree of depth has exceeded the half of semiconductor substrate N-type epitaxy layer thickness.When described VDMOS device needs to turn off withstand voltage work, device drain applies a positive voltage, device source electrode connecting to neutral current potential, first this positive voltage can make to be positioned near the first groove outer wall below P well layer and induce a large amount of positive charges, electronics in N-type epitaxy layer between described positive charge and adjacent first trenches constitutes the structure that a group is similar to P-N junction, this P-N junction is oppositely bigoted under drain electrode positive voltage, and exhaust rapidly, form Withstand voltage layer, simultaneously, heavy insulation oxide layer on first trench wall is also withstand voltage together, so, as the cellular beneath trenches that coexists adds a horizontal Withstand voltage layer, thus add the voltage endurance capability of device.
In addition, the first metal is provided with above the first conductive polycrystalline silicon in described first groove, described first metal and the first conductive polycrystalline silicon equipotential are electrically connected, when described VDMOS device needs to turn off withstand voltage work, described first metal applies a positive bias, this positive bias is less than drain voltage, electric field strength in the N-type epitaxy layer of the positive bias meeting partial offset that described first metal applies between adjacent first trenches below P well layer, and the peak electric field in this region is shifted to cellular channel bottom, as shown in figure 18, when not adding positive bias, peak electric field is positioned at position A, when after increase positive bias, peak electric field moves up gradually, and positive bias is larger, peak electric field is about near position B, regulate best peak electric field position can the voltage endurance capability of boost device further by the size of conservative control positive bias like this.As shown in following table and Figure 19, for the N channel enhancement VDMOS device of a 200V, increase the size of positive bias on the first metal gradually, drain-source breakdown voltage (BVdss) the also corresponding increase of device.
Described VDMOS device adds the voltage endurance capability of device by introducing the first groove, thus, break away from traditional VDMOS device and realize high withstand voltage mode by increase epilayer resistance rate and epitaxy layer thickness merely, thus the epitaxial loayer of more low-resistivity can be selected, therefore, device also has lower specific on-resistance while meeting higher withstand voltage demand, for the N channel enhancement VDMOS device of 200V, the specific on-resistance of the specific on-resistance contrast conventional groove type VDMOS device of device of the present invention, 3.9m Ω-cm2 is reduced to by 5.8m Ω-cm2, reduce about 33%.
Note, above-described embodiment is described for N-type VDMOS device.The present invention also may be used for P type VDMOS device, only needs that the conduction type in above-described embodiment changes N-type into by P type, N-type changes P type into.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive without departing from the basic idea of the present invention or associate, all should think and be included within protection scope of the present invention.
Claims (8)
1. a VDMOS device for new structure, in the top plan view of described VDMOS device, comprise and be positioned at active area on semiconductor substrate and terminal protection district, described terminal protection district is around being surrounded by source region; The cellular that regular array is arranged is comprised in described active area; On the cross section of described VDMOS device, described semiconductor substrate comprises the first conductive type epitaxial layer being positioned at surface and the first conductivity type substrate layer be positioned at below substrate, described first conductive type epitaxial layer is connected with the first conductivity type substrate layer, the upper surface of described first conductive type epitaxial layer is the first interarea of semiconductor substrate, the lower surface of described first conductivity type substrate layer is the second interarea of semiconductor substrate, and the top of described first conductive type epitaxial layer is provided with the second conductive type layer; Second interarea of described semiconductor substrate is provided with drain metal;
It is characterized in that:
On the cross section of described VDMOS device active area, the first groove is provided with in described first conductive type epitaxial layer, described first groove is extended vertically downward by the first interarea of semiconductor substrate, the degree of depth stretches in the first conductive type epitaxial layer below the second conductive type layer, described first trench wall superficial growth has insulating oxide, has in the first groove of insulating oxide be filled with the first conductive polycrystalline silicon in inwall growth;
On the cross section of described VDMOS device active area, the first insulating medium layer is coated with at described first groove notch, described first insulating medium layer is provided with the first contact hole, described first contact hole is positioned at above the first conductive polycrystalline silicon, in described first contact hole, be filled with the first metal, described first metal and the first conductive polycrystalline silicon equipotential are electrically connected;
On the cross section of described VDMOS device active area, cellular groove is provided with between every two adjacent the first grooves, described cellular groove is extended vertically downward by the first interarea of semiconductor substrate, the degree of depth stretches in the first conductive type epitaxial layer below the second conductive type layer, the superficial growth of described cellular trench wall has insulated gate oxide layer, have in the cellular groove of insulated gate oxide layer in inwall growth and be filled with the second conductive polycrystalline silicon, the second insulating medium layer is coated with at described cellular groove notch, the both sides of described cellular groove are provided with source contact openings, source metal is filled with in described source contact openings, the first conductivity type implanted region is provided with above the both sides outer wall that described cellular groove is corresponding, described source metal and the second conductive type layer and the first conductivity type implanted region ohmic contact,
For N-type VDMOS device, described first conduction type is N-type, and described second conduction type is P type; For P type VDMOS device, described first conduction type is P type, and described second conduction type is N-type.
2. the VDMOS device of new structure according to claim 1, it is characterized in that: on the cross section of described VDMOS device active area, described first metal is not connected mutually with source metal.
3. the VDMOS device of new structure according to claim 1, it is characterized in that: on the cross section of described VDMOS device active area, the degree of depth of described first groove is greater than the degree of depth of cellular groove.
4. a manufacture method for the VDMOS device of new structure, is characterized in that comprising the steps:
A () provides the semiconductor substrate with two opposing main faces, described semiconductor substrate comprises the first conductivity type substrate layer and is positioned at the first conductive type epitaxial layer above described first conductivity type substrate layer; Described two opposing main faces comprise the first interarea and the second interarea;
(b) on the first interarea of above-mentioned semiconductor substrate, deposit first groove hard mask layer;
C the first groove hard mask layer is optionally sheltered and etched to (), form the hard mask window of the first etching groove;
D () utilizes above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, forms the first groove, and described first gash depth is less than the first conductive type epitaxial layer thickness;
E () removes the first groove hard mask layer on the first interarea, on the first interarea and the first trench wall growth insulating oxide;
F () be deposit first conductive polycrystalline silicon on above-mentioned insulating oxide, described first conductive polycrystalline silicon fills the first groove that inwall growth has insulating oxide simultaneously;
G the first conductive polycrystalline silicon above () etching removal first interarea, obtains the first conductive polycrystalline silicon in the first groove;
Insulating oxide on (h) erosion removal first interarea;
I () be deposit cellular groove hard mask layer on the first interarea of semiconductor substrate;
J cellular groove hard mask layer is optionally sheltered and etched to (), form the hard mask window of cellular etching groove;
K () utilizes above-mentioned hard mask window, anisotropic dry etch semiconductor substrate on the first interarea, and form cellular groove, described cellular groove is between the first groove, and the degree of depth is shallower than the first groove;
L () removes the cellular groove hard mask layer on the first interarea, on the first interarea and cellular trench wall growth insulated gate oxide layer;
M () be deposit second conductive polycrystalline silicon on above-mentioned insulated gate oxide layer, described second conductive polycrystalline silicon fills the cellular groove that inwall growth has insulated gate oxide layer simultaneously;
N the second conductive polycrystalline silicon above () etching removal first interarea, obtains the second conductive polycrystalline silicon in cellular groove;
O () is on the first interarea, autoregistration ion implantation second conductive type impurity ion, and the second conductive type layer being positioned at semiconductor substrate first conductive type epitaxial layer top is formed by high temperature knot, the degree of depth of described second conductive type layer is less than the second conductive polycrystalline silicon distance to downward-extension in cellular groove;
P (), on described first interarea, carries out source region photoetching, and inject the first conductive type impurity ion of high concentration, and is formed the first conductivity type implanted region be positioned at above the corresponding both sides outer wall of cellular groove by high temperature knot;
(q) on above-mentioned first interarea, deposit insulating medium layer;
R () carries out contact hole photoetching and etching on described insulating medium layer, thus the first contact hole is formed above the first groove notch, source contact openings is formed in cellular groove both sides, meanwhile, above the first groove notch He above cellular groove notch, the first insulating medium layer and the second insulating medium layer is formed respectively;
S () be deposited metal on described first insulating medium layer and on the second insulating medium layer, and described metal level fills the first contact hole and source contact openings;
T () carries out photoetching and etching on described metal level, form the first metal and source metal, the first conductive polycrystalline silicon equipotential in described first metal and the first groove is electrically connected, described source metal and the second conductive type layer and the first conductivity type implanted region ohmic contact;
U () be deposit drain metal on the second interarea of described semiconductor substrate;
For the manufacture method of N-type VDMOS device, described first conduction type is N-type, and described second conduction type is P type; For the manufacture method of P type VDMOS device, described first conduction type is P type, and described second conduction type is N-type.
5. the manufacture method of the VDMOS device of new structure according to claim 4, is characterized in that: the material of described semiconductor substrate comprises silicon.
6. the manufacture method of the VDMOS device of new structure according to claim 4, is characterized in that: described hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
7. the manufacture method of the VDMOS device of new structure according to claim 4, is characterized in that: described insulating medium layer is silex glass USG, boron-phosphorosilicate glass BPSG or phosphorosilicate glass PSG.
8. the manufacture method of the VDMOS device of new structure according to claim 4, is characterized in that: the degree of depth of described first groove is 50% ~ 90% of semiconductor substrate first conductive type epitaxial layer thickness.
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| CN105529369B (en) | 2016-03-08 | 2019-05-14 | 中国电子科技集团公司第二十四研究所 | A kind of semiconductor structure cell and power semiconductor |
| CN107785426B (en) | 2016-08-31 | 2020-01-31 | 无锡华润上华科技有限公司 | kinds of semiconductor devices and their manufacture |
| CN107785273B (en) | 2016-08-31 | 2020-03-13 | 无锡华润上华科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN107978641A (en) * | 2017-11-23 | 2018-05-01 | 中航（重庆）微电子有限公司 | A kind of power MOS (Metal Oxide Semiconductor) device manufacture method of new gate structure |
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| CN102104068A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
| CN203288599U (en) * | 2013-04-22 | 2013-11-13 | 无锡新洁能股份有限公司 | VDMOS device of novel structure |
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| CN102104068A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
| CN203288599U (en) * | 2013-04-22 | 2013-11-13 | 无锡新洁能股份有限公司 | VDMOS device of novel structure |
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