CN106847919A - A kind of high pressure hyperconjugation VDMOS - Google Patents
A kind of high pressure hyperconjugation VDMOS Download PDFInfo
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- CN106847919A CN106847919A CN201611218670.6A CN201611218670A CN106847919A CN 106847919 A CN106847919 A CN 106847919A CN 201611218670 A CN201611218670 A CN 201611218670A CN 106847919 A CN106847919 A CN 106847919A
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- superjunction
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- hyperconjugation vdmos
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- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000002019 doping agent Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of high pressure hyperconjugation VDMOS, including：N+ substrates；First superjunction, above N+ substrates；Second superjunction, above the first superjunction.The first superjunction is formd in first epitaxial region of the present invention half hyperconjugation VDMOS in the prior art, to realize that transverse electric field regulates and controls, the dopant concentration of the first epitaxial region is increased considerably, the conducting resistance of device is finally considerably reduced.So solving half hyperconjugation VDMOS of the prior art has the larger technical problem of conducting resistance.
Description
Technical field
The present invention relates to microelectronics technology, more particularly to a kind of high pressure hyperconjugation VDMOS.
Background technology
Full hyperconjugation VDMOS (Vertical Double Diffused Metal Oxide Semiconductor, vertical couple
Diffused MOS field-effect should be managed) structure, as shown in figure 1, Withstand voltage layer is alternately made up of N posts and P posts, based on electricity
Lotus compensation principle, electric field is approximately distributed rectangular, BV (Breakdown Voltage, breakdown voltage) is only depended on drift region
Thickness, and it is unrelated with its doping concentration.Doping concentration an order of magnitude higher than traditional VDMOS of full superjunction Withstand voltage layer, equal BV
Ron (On Resistance, conducting resistance) it is smaller than traditional VDMOS 5-10 times, therefore, full hyperconjugation VDMOS is described as power half
Landmark structure in conductor device development history.The difficult point for preparing full hyperconjugation VDMOS is to prepare superjunction, due to breakdown voltage
(BV) depth-to-width ratio to P posts is directly proportional, if it is desired to obtain larger breakdown voltage, then need to etch deep larger P posts wide, but
It is to be limited to existing process conditions, the breakdown voltage of full hyperconjugation VDMOS is extremely difficult to more than 900V.
The structure of half hyperconjugation VDMOS, as shown in Fig. 2 from structure cell, it be on the basis of full hyperconjugation VDMOS,
The first epitaxial region is introduced between super-junction structure and substrate N+ areas, the first epitaxial region is the N- cushions of a low concentration, also referred to as
It is bottom auxiliary layer.First epitaxial region forms the first drift region of half hyperconjugation VDMOS, and superjunction N posts form second drift of VDMOS
Area is (i.e.：Second epitaxial region).Superjunction N posts still with p-well (i.e.：P-body) it is connected.Compared with full hyperconjugation VDMOS, half superjunction
The P post depth of VDMOS shortens, and depth-to-width ratio reduces, and greatly reduces manufacturing process difficulty, and the breakdown voltage of half hyperconjugation VDMOS can
To reach more than 900V.But, because the dopant concentration of the first epitaxial region is relatively low, so the resistivity of the first epitaxial region is larger,
So as to considerably increase the conducting resistance of device.
The content of the invention
The embodiment of the present invention solves half hyperconjugation VDMOS of the prior art and deposits by providing a kind of high pressure hyperconjugation VDMOS
In the technical problem that conducting resistance is larger.
The present invention provides following technical scheme by one embodiment of the invention：
A kind of high pressure hyperconjugation VDMOS, including：
N+ substrates；
First superjunction, above the N+ substrates；
Second superjunction, above first superjunction.
Preferably, first superjunction, including：
First epitaxial region；
First P posts, positioned at first epitaxial region outside.
Preferably, second superjunction, including：
Second epitaxial region；
2nd P posts, positioned at second epitaxial region outside.
Preferably, the high pressure hyperconjugation VDMOS, also includes：
P-well, above second superjunction, and is connected with second epitaxial region and the 2nd P posts.
Preferably, the high pressure hyperconjugation VDMOS, also includes：
N+ source regions, are arranged on above the p-well.
Preferably, the high pressure hyperconjugation VDMOS, also includes：
Source electrode, is connected with the p-well and the N+ source regions；
Drain electrode, is connected with the N+ substrates.
Preferably, the high pressure hyperconjugation VDMOS, also includes：
Gate oxide, above the p-well and second epitaxial region, and with the p-well and described second
Epitaxial region is connected；
Grid, is connected with the gate oxide.
One or more technical schemes provided in the embodiment of the present invention, at least have the following technical effect that or advantage：
In embodiments of the present invention, a kind of high pressure hyperconjugation VDMOS is disclosed, including：N+ substrates；First superjunction, positioned at N+
Above substrate；Second superjunction, above the first superjunction.First extension of the present invention half hyperconjugation VDMOS in the prior art
The first superjunction is formd in area, to realize that transverse electric field regulates and controls, the dopant concentration of the first epitaxial region is increased considerably, it is final big
The amplitude reduction conducting resistance of device.So solving half hyperconjugation VDMOS of the prior art, to there is conducting resistance larger
Technical problem.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to that will make needed for embodiment description
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the present invention, for this
For the those of ordinary skill of field, on the premise of not paying creative work, can also obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the structure chart of full hyperconjugation VDMOS of the prior art；
Fig. 2 is the structure chart of half hyperconjugation VDMOS of the prior art；
Fig. 3 is the structure chart of the high pressure hyperconjugation VDMOS in the embodiment of the present invention.
Specific embodiment
The embodiment of the present invention solves half hyperconjugation VDMOS of the prior art and deposits by providing a kind of high pressure hyperconjugation VDMOS
In the technical problem that conducting resistance is larger.
The technical scheme of the embodiment of the present invention is in order to solve the above technical problems, general thought is as follows：
A kind of high pressure hyperconjugation VDMOS, including：N+ substrates；First superjunction, above the N+ substrates；Second superjunction, position
Above first superjunction.
In order to be better understood from above-mentioned technical proposal, below in conjunction with Figure of description and specific embodiment to upper
Technical scheme is stated to be described in detail.
Embodiment one
As shown in figure 3, a kind of high pressure hyperconjugation VDMOS is present embodiments provided, including：
N+ substrates；
First superjunction, above N+ substrates；
Second superjunction, above the first superjunction.
In specific implementation process, the first superjunction includes the first epitaxial region and a P posts, and a P posts are located at the first extension
Area outside.Second superjunction includes the second epitaxial region and the 2nd P posts, and the 2nd P is located at the second epitaxial region outside.
In specific implementation process, the first epitaxial region is the first drift region for foring the high pressure hyperconjugation VDMOS, second
Epitaxial region forms the second drift region of the high pressure hyperconjugation VDMOS.
In specific implementation process, the first epitaxial region is the N- cushions of low concentration, and the first epitaxial region is to constitute
One N posts, in the first epitaxial region introducing p-type mixes area, and the p-type is mixed area and constitutes a P posts, so, just outside first
Yan Qu forms the first superjunction, it is achieved that transverse electric field regulates and controls, has increased considerably the dopant concentration of the first epitaxial region, most
The conducting resistance of device is considerably reduced eventually.
Simultaneously as the first epitaxial region typically will not be too thick, so filling to form the difficulty of a P posts not by cutting
Greatly, i.e., the structure can't increase the technology difficulty of device, it is ensured that the breakdown voltage of the high pressure hyperconjugation VDMOS can reach
To more than 900V.
Further, as shown in figure 3, the high pressure hyperconjugation VDMOS, also includes：
P-well, above the second superjunction, and is connected with the second epitaxial region and the 2nd P posts；
N+ source regions, are arranged on above p-well；
Source electrode, is connected with p-well and N+ source regions；
Drain electrode, is connected with N+ substrates；
Gate oxide, above p-well and the second epitaxial region, and is connected with p-well and the second epitaxial region；
Grid, is connected with gate oxide.
In specific implementation process, p-well can simultaneously be connected with the second epitaxial region and the 2nd P posts, it is also possible to only with the 2nd P
Post is connected.
In specific implementation process, source electrode, drain electrode can be adopted and be formed from aluminium, and grid can be made of polysilicon.
Technical scheme in the embodiments of the present invention, at least has the following technical effect that or advantage：
In embodiments of the present invention, a kind of high pressure hyperconjugation VDMOS is disclosed, including：N+ substrates；First superjunction, positioned at N+
Above substrate；Second superjunction, above the first superjunction.First extension of the present invention half hyperconjugation VDMOS in the prior art
The first superjunction is formd in area, to realize that transverse electric field regulates and controls, the dopant concentration of the first epitaxial region is increased considerably, it is final big
The amplitude reduction conducting resistance of device.So solving half hyperconjugation VDMOS of the prior art, to there is conducting resistance larger
Technical problem.
, but those skilled in the art once know basic creation although preferred embodiments of the present invention have been described
Property concept, then can make other change and modification to these embodiments.So, appended claims are intended to be construed to include excellent
Select embodiment and fall into having altered and changing for the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification without deviating from essence of the invention to the present invention
God and scope.So, if these modifications of the invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (7)
1. a kind of high pressure hyperconjugation VDMOS, it is characterised in that including：
N+ substrates；
First superjunction, above the N+ substrates；
Second superjunction, above first superjunction.
2. high pressure hyperconjugation VDMOS as claimed in claim 1, it is characterised in that first superjunction, including：
First epitaxial region；
First P posts, positioned at first epitaxial region outside.
3. high pressure hyperconjugation VDMOS as claimed in claim 2, it is characterised in that second superjunction, including：
Second epitaxial region；
2nd P posts, positioned at second epitaxial region outside.
4. high pressure hyperconjugation VDMOS as claimed in claim 3, it is characterised in that the high pressure hyperconjugation VDMOS, also includes：
P-well, above second superjunction, and is connected with second epitaxial region and the 2nd P posts.
5. high pressure hyperconjugation VDMOS as claimed in claim 4, it is characterised in that the high pressure hyperconjugation VDMOS, also includes：
N+ source regions, are arranged on above the p-well.
6. high pressure hyperconjugation VDMOS as claimed in claim 5, it is characterised in that the high pressure hyperconjugation VDMOS, also includes：
Source electrode, is connected with the p-well and the N+ source regions；
Drain electrode, is connected with the N+ substrates.
7. high pressure hyperconjugation VDMOS as claimed in claim 6, it is characterised in that the high pressure hyperconjugation VDMOS, also includes：
Gate oxide, above the p-well and second extension, and with the p-well and second epitaxial region
It is connected；
Grid, is connected with the gate oxide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611218670.6A CN106847919A (en) | 2016-12-26 | 2016-12-26 | A kind of high pressure hyperconjugation VDMOS |
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| CN201611218670.6A CN106847919A (en) | 2016-12-26 | 2016-12-26 | A kind of high pressure hyperconjugation VDMOS |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170236930A1 (en) * | 2014-09-29 | 2017-08-17 | Wuxi China Resources Huajing Microelectronics Co | Vertical double-diffused metal-oxide semiconductor field-effect transistor and manufacturing method therefor |
| CN108231903A (en) * | 2018-01-24 | 2018-06-29 | 重庆大学 | A kind of soft superjunction power MOSFET for restoring body diode of band |
| CN108336131A (en) * | 2018-02-26 | 2018-07-27 | 丛艳欣 | Vertical double diffused metal-oxide semi conductor transistor and preparation method thereof |
| CN109698228A (en) * | 2017-10-20 | 2019-04-30 | 深圳尚阳通科技有限公司 | A kind of super-junction device and manufacturing method |
| CN113851542A (en) * | 2021-09-24 | 2021-12-28 | 电子科技大学重庆微电子产业技术研究院 | Super-junction MOSFET with soft reverse recovery characteristic |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010032998A1 (en) * | 2000-03-17 | 2001-10-25 | Susumu Iwamoto | Super-junction semiconductor device and method of manufacturing the same |
-
2016
- 2016-12-26 CN CN201611218670.6A patent/CN106847919A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010032998A1 (en) * | 2000-03-17 | 2001-10-25 | Susumu Iwamoto | Super-junction semiconductor device and method of manufacturing the same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170236930A1 (en) * | 2014-09-29 | 2017-08-17 | Wuxi China Resources Huajing Microelectronics Co | Vertical double-diffused metal-oxide semiconductor field-effect transistor and manufacturing method therefor |
| CN109698228A (en) * | 2017-10-20 | 2019-04-30 | 深圳尚阳通科技有限公司 | A kind of super-junction device and manufacturing method |
| CN108231903A (en) * | 2018-01-24 | 2018-06-29 | 重庆大学 | A kind of soft superjunction power MOSFET for restoring body diode of band |
| CN108231903B (en) * | 2018-01-24 | 2020-06-02 | 重庆大学 | Super junction power MOSFET with soft recovery body diode |
| CN108336131A (en) * | 2018-02-26 | 2018-07-27 | 丛艳欣 | Vertical double diffused metal-oxide semi conductor transistor and preparation method thereof |
| CN113851542A (en) * | 2021-09-24 | 2021-12-28 | 电子科技大学重庆微电子产业技术研究院 | Super-junction MOSFET with soft reverse recovery characteristic |
| CN113851542B (en) * | 2021-09-24 | 2024-04-12 | 电子科技大学重庆微电子产业技术研究院 | Super junction MOSFET with soft reverse recovery characteristic |
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