CN108336131B - Vertical double diffused metal-oxide semi conductor transistor and preparation method thereof - Google Patents
Vertical double diffused metal-oxide semi conductor transistor and preparation method thereof Download PDFInfo
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- CN108336131B CN108336131B CN201810159636.9A CN201810159636A CN108336131B CN 108336131 B CN108336131 B CN 108336131B CN 201810159636 A CN201810159636 A CN 201810159636A CN 108336131 B CN108336131 B CN 108336131B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 61
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 239000002019 doping agent Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 208000032750 Device leakage Diseases 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 16
- 239000000243 solution Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012776 electronic material Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The present invention provides a kind of vertical double diffused metal-oxide semi conductor transistors and preparation method thereof, it is related to technology of semiconductor chips field, comprising: N-type substrate, the area N+, P- body area, PN alternating superjunction area, N+ source region, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and device drain metal；Grid oxic horizon be covered in N+ source region, the area N+, P- body area junction upper surface, polysilicon gate is equipped with above grid oxic horizon, grid oxic horizon and polysilicon gate extremely " convex " type layer, wherein, the upper surface of the central area in the area N+ is higher than the upper surface in P- body area, and the upper surface of the side zones in the area N+ is higher than the upper surface in PN alternating superjunction area；PN alternating superjunction area is alternately arranged by P+ floor and N+ floor lateral separation, the technical solution alleviates the pressure resistance technical problem that performance is poor, capacitance resistance is high of the existing technology, the voltage endurance capability for improving device, improves saturation current, significantly reduces device grids oxidation layer capacitance.
Description
Technical field
The present invention relates to technology of semiconductor chips fields, partly lead more particularly, to a kind of vertical double diffused metal-oxide
Body transistor and preparation method thereof.
Background technique
The advantages of vertical double diffused metal-oxide semi conductor transistor has bipolar transistor and common MOS device concurrently, nothing
By switch application or linear applications, VDMOS is ideal power device.VDMOS be mainly used for electric machine speed regulation, inverter,
Uninterruptible power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc..VDMOS point for enhanced VDMOS and
Depletion type VDMOS.With the development of semiconductor design arts and field of semiconductor technology, current VDMOS device to
Low cost, the development of high-performance field, higher performance and lower cost mean that more extensive market is applied.It is realizing
In process of the present invention, at least there are the following problems in the prior art: the electronic material being widely present at present for inventor's discovery, especially
Semiconductor material, in order to guarantee that device has stable pressure-resistant performance, the grid oxic horizon in structure is often with higher
Capacitor has seriously affected the conduction property of device, hinders its development in field, and therefore, there are resistance to pressures for the prior art
The technical problem that energy is poor, capacitance resistance is high.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of vertical double diffused metal-oxide semi conductor transistor and
Its production method, to alleviate the pressure resistance technical problem that performance is poor, capacitance resistance is high of the existing technology.
In a first aspect, the embodiment of the invention provides a kind of vertical double diffused metal-oxide semi conductor transistor, packet
Include: N-type substrate, the area N+, P- body area, PN alternating superjunction area, N+ source region, grid oxic horizon, polysilicon gate, dielectric layer isolation,
Device source metal and device drain metal；
The area N+ is the electronics drift region being made of central area, bottom edge area and side zones；
The top of N-type substrate is connect with the bottom edge area in the area N+, and the inner surface in the area N+ extends to P- body area to central area, and PN is handed over
It is located between the two sides, the area N+ and P- body area of the central area in the area N+ for superjunction area, the upper surface in P- body area replaces superjunction area with PN
Connection be equipped with N+ source region, grid oxic horizon be covered in N+ source region, the area N+, P- body area junction upper surface, gate oxidation
Layer top is equipped with polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer, and PN replaces superjunction area and N+ source region connects
The upper surface at the place of connecing is provided with device source metal, and the upper surface of the side zones in the area N+ is equipped with device drain metal, polysilicon gate
The upper surface of pole and its dielectric layer is provided between device source metal, between device source metal and device drain metal
Isolation；
Wherein, the upper surface of the central area in the area N+ is higher than the upper surface in P- body area, and the upper surface of the side zones in the area N+ is higher than
The upper surface in PN alternating superjunction area；
PN alternating superjunction area is alternately arranged by P+ floor and N+ floor longitudinal gap, and the upper and lower surface in PN alternating superjunction area is
P+ layers.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
Superjunction area is alternately arranged by three floor P+ floor and two layers of N+ floor longitudinal gap, and upper and lower surface is P+ layers；
P+ layers be from top to bottom respectively the first P+ layer, the 2nd P+ layer and the 3rd P+ layers, N+ layers respectively the first N+ layers with the
Two N+ layers, the first N+ layers be located at the first P+ layer and the 2nd between P+ layers, the 2nd N+ layers positioned at the 2nd P+ layers and the 3rd between P+ layers.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the first P+
Layer, the 2nd P+ layer and the 3rd P+ layers of doping concentration are successively successively decreased, and the first P+ layers of dopant dose are 4E15~5E15, and the 2nd P+ layers
Dopant dose be 3E15~4E15, the 3rd P+ layer dopant dose be 2E15~3E15.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the first N+
Layer and the 2nd N+ layers of dopant dose are 2E15.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, with the area N+
The thickness degree at the middle part of grid oxic horizon that is in contact of central area be greater than grid oxic horizon both wings thickness degree.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the area N+ is
N-type heavily doped region, dopant dose are 1E15~2E15, and cross-sectional width is 2~5 μm.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
The cross-sectional width in superjunction area is 5~10 μm.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
Every layer of P+ floor or N+ floor with a thickness of 2~3 μm in superjunction area.
Second aspect, the embodiment of the invention provides a kind of systems of vertical double diffused metal-oxide semi conductor transistor
Make method, comprising:
N-type substrate is provided, N+ epitaxial layer is formed in the upper surface of N-type substrate, is formed in the upper surface of N+ epitaxial layer by P+
Layer and the N+ layers of alternately arranged epitaxial layer in lateral separation, and the upper and lower surface of epitaxial layer is P+ layers；
Groove is formed in the center of epitaxial layer, the bottom of groove extends to the upper surface of N+ epitaxial layer, and the two of groove
Side forms PN and replaces superjunction area；
P- epitaxial layer is formed in the trench, carries out surface planarisation after extension；
A floor exposure mask is deposited in the upper surface in P- epitaxial layer and PN alternating superjunction area, and the width of exposure mask is less than P- epitaxial layer
With the overall width in PN alternating superjunction area, the center of exposure mask opens up fluted, and the bottom of groove extends to the upper surface of P- epitaxial layer；
Etching is continued to groove and forms deep trench, the bottom of deep trench extends to the upper surface of N+ epitaxial layer, and edge
The both ends of exposure mask perform etching to form side slot to PN alternating superjunction area, bottom to the upper surface of N+ epitaxial layer of side slot；
Deep trench and side slot are driven by heat and inject N-type ion, exposure mask, N+ epitaxial layer, depth are removed by wet processing
Groove and side slot form the area N+；
Grid oxic horizon is formed in the junction upper surface in the area N+ and P- body area, deposits to be formed on the surface of grid oxic horizon
Polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer；
Photoetching is carried out in the two sides P- body area of polysilicon gate to inject to form N+ source region；
Device source metal is formed in the upper surface in the alternating superjunction area PN and N+ source region junction, in the side zones in the area N+
Upper surface forms device drain metal, forms dielectric layer between device source metal, device drain metal and polysilicon gate
Isolation.
The embodiment of the present invention brings following the utility model has the advantages that vertical double diffused metal-oxygen provided by the embodiment of the present invention
Compound semiconductor transistor and preparation method thereof, comprising: N-type substrate, the area N+, P- body area, PN replace superjunction area, N+ source region, grid
Pole oxide layer, polysilicon gate, dielectric layer isolation, device source metal and device drain metal；The area N+ is by central area, bottom edge
The electronics drift region in area and side zones composition；The top of N-type substrate is connect with the bottom edge area in the area N+, and the inner surface in the area N+ is to center
Area extends to P- body area, and PN alternating superjunction area is located between the two sides, the area N+ and P- body area of the central area in the area N+, P- body area it is upper
Surface replaces superjunction area connection with PN equipped with N+ source region, and grid oxic horizon is covered in N+ source region, the area N+, P- body area junction
Upper surface, polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer, PN alternating are equipped with above grid oxic horizon
The upper surface of superjunction area and N+ source region junction is provided with device source metal, and the upper surface of the side zones in the area N+ is leaked equipped with device
Pole metal, the upper surface of polysilicon gate and its between device source metal, device source metal and device drain metal it
Between be provided with dielectric layer isolation；Wherein, the upper surface of the central area in the area N+ is higher than the upper surface in P- body area, the side zones in the area N+
Upper surface be higher than PN alternating superjunction area upper surface；PN alternating superjunction area is alternately arranged by P+ floor and N+ floor longitudinal gap, and
The upper and lower surface that PN replaces superjunction area is P+ floor.The technical solution is by using the alternating superjunction area PN of multilayered structure and the area N+
Organic cooperation, when gate oxidation is utilized, the oxidation rate on the area the N+ surface rule fast compared with polysilicon improves the resistance to of device
Pressure energy power, improves saturation current, significantly reduces device grids oxidation layer capacitance, reduces device while improving device performance
The structural volume of part, reduces the production cost of device, and then alleviates that pressure-resistant performance of the existing technology is poor, capacitance resistance
High technical problem.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the cross-sectional view of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention；
Fig. 2 is the top view of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention；
Fig. 3 is the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
Flow chart；
Fig. 4 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S1；
Fig. 5 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S2；
Fig. 6 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S3；
Fig. 7 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S4；
Fig. 8 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S5；
Fig. 9 be vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention production method in,
The product schematic diagram of step S6；
Figure 10 is the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
In, the product schematic diagram of step S7；
Figure 11 is the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
In, the product schematic diagram of step S8.
Icon:
The area 1-N+；P+ layers of 2a- the first；P+ layers of 2b- the 2nd；P+ layers of 2c- the 3rd；N+ layers of 3a- the first；N+ layers of 3b- the 2nd；4-
N+ source region；5-P- body area；6- polysilicon gate；7- grid oxic horizon；The isolation of 8- dielectric layer；9- device source metal；10- device
Drain metal.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Currently, the electronic material being widely present, especially semiconductor material, in order to guarantee that device has stable resistance to pressure
Can, grid oxic horizon in structure often capacitor with higher has seriously affected the conduction property of device, hinder its
Development in field is based on this, vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention and its system
Make method, the voltage endurance capability of device can be improved, improve saturation current, reduces device grids and aoxidize layer capacitance.
Embodiment one:
Referring to Fig. 1 and Fig. 2, vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention cuts open
View and top view.A kind of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, comprising: N-type
Substrate, the area N+ 1, P- body area 5, PN alternating superjunction area, N+ source region 4, grid oxic horizon 7, polysilicon gate 6, dielectric layer isolation 8,
Device source metal 9 and device drain metal 10.Wherein, the area N+ is the electric float being made of central area, bottom edge area and side zones
Move area.The cross section of side zones is " mouth " font, and the cross section of central area is line-styled, positioned at the center of side zones, bottom edge
Area is square, and is located at bottom device.The bottom edge area in the area N+ is highly doped epitaxial layer, and side zones are longitudinal by injecting and expanding
The area N+ formed is dissipated, further, the epitaxial layer concentration in bottom edge area can be higher than the side zones that longitudinal injection diffuses to form.It should
Technical solution will introduce the highly doped area N+ inside the epitaxial layer being spaced between drain electrode and source electrode, reduce the resistance of epitaxial layer
Rate, and then reduce VDMOS device conducting resistance.
The top of N-type substrate is connect with the bottom edge area in the area N+, and the inner surface in the area N+ extends to P- body area to central area, and PN is handed over
It is located between the two sides, the area N+ and P- body area of the central area in the area N+ for superjunction area, the upper surface in P- body area replaces superjunction area with PN
Connection be equipped with N+ source region, grid oxic horizon be covered in N+ source region, the area N+, P- body area junction upper surface, gate oxidation
Layer top is equipped with polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer, and grid oxic horizon and polysilicon gate
The outer edge of pole is aligned, compared with the N+ plot structure of traditional horizontal type, when which is utilized gate oxidation, the area N+ surface
The oxidation rate rule fast compared with polysilicon, improves the voltage endurance capability of device, improves saturation current, significantly reduce device gate
Pole aoxidizes layer capacitance.The upper surface of the alternating superjunction area PN and N+ source region junction is provided with device source metal, the side in the area N+
The upper surface in area is equipped with device drain metal, the upper surface of polysilicon gate and its between device source metal, device source electrode
Dielectric layer is provided between metal and device drain metal to be isolated.
When semiconductor devices works, apply positive voltage on polysilicon gate 6, generates conducting channel in lower section, electronics is from N
+ source region 4 is set out, and conducting channel is flowed through, and is collected by the area N+ 1, is finally flowed out from the device drain metal 10 of the side zones in the area N+.Its
In, the upper surface of the central area in the area N+ is higher than the upper surface in P- body area, and the upper surface of the side zones in the area N+ is higher than PN and replaces superjunction
The upper surface in area.
Further, PN replaces superjunction area and is alternately arranged by P+ floor and N+ floor longitudinal gap, and PN alternating superjunction area is upper
Lower surface is P+ layers.Wherein, P+ layers are p-type heavily doped region, and N+ layers are N-type heavily doped region, reversed when applying between source and drain
Bias, PN alternating superjunction area all exhaust, and undertake the strong electrical field between source and drain.Opposite traditional devices, the structure are not required to increase terminal
Pressure-resistance structure significantly reduces device area, thereby reduces the production cost of device.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
Superjunction area is alternately arranged by three floor P+ floor and two layers of N+ floor longitudinal gap, and upper and lower surface is P+ layers.
P+ layers are respectively the first P+ layers of 2a, the 2nd P+ layers of 2b from top to bottom and the 3rd P+ layers of 2c, N+ layers are respectively the first N+
Layer 3a and the 2nd N+ layers of 3b, for the first N+ layers of 3a between the first P+ layers of 2a and the 2nd P+ layers of 2b, the 2nd N+ layers of 3b are located at the 2nd P
Between+layer 2b and the 3rd P+ layers of 2c.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the first P+
Layer, the 2nd P+ layer and the 3rd P+ layers of doping concentration are successively successively decreased, and the first P+ layers of dopant dose are 4E15~5E15, and the 2nd P+ layers
Dopant dose be 3E15~4E15, the 3rd P+ layer dopant dose be 2E15~3E15.Wherein, the unit of dopant dose be from
Sub- number/square centimeter.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the first N+
Layer and the 2nd N+ layers of dopant dose are 2E15.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the area N+ is adopted
With the PTBI2T electronics drift layer being polymerize by TBI material.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, with the area N+
The thickness degree at the middle part of grid oxic horizon that is in contact of central area be greater than grid oxic horizon both wings thickness degree.Due to the area N+
Surface is heavy doping, and therefore, on the area N+ surface, the oxide layer of growth is thicker, so that the gate oxidation layer capacitance of device is reduced,
Improve saturation current.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the area N+ is
N-type heavily doped region, dopant dose are 1E15~2E15, and cross-sectional width is 2~5 μm.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
The cross-sectional width in superjunction area is 5~10 μm.
Further, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, PN alternating
Every layer of P+ floor or N+ floor with a thickness of 2~3 μm in superjunction area.
Vertical double diffused metal-oxide semi conductor transistor provided by the embodiment of the present invention, comprising: N-type substrate, N+
Area, P- body area, PN alternating superjunction area, N+ source region, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and
Device drain metal；The area N+ is the electronics drift region being made of central area, bottom edge area and side zones；The top of N-type substrate and N+
The bottom edge area in area connects, and the inner surface in the area N+ extends to P- body area to central area, and PN alternating superjunction area is located at the central area in the area N+
Two sides, between the area N+ and P- body area, the upper surface in P- body area replaces superjunction area connection with PN equipped with N+ source region, grid oxygen
Change floor be covered in N+ source region, the area N+, P- body area junction upper surface, polysilicon gate, grid are equipped with above grid oxic horizon
The upper surface of oxide layer and polysilicon gate extremely " convex " type layer, the alternating superjunction area PN and N+ source region junction is provided with device source electrode
Metal, the upper surface of the side zones in the area N+ are golden equipped with device drain metal, the upper surface of polysilicon gate and its with device source electrode
Between category, dielectric layer is provided between device source metal and device drain metal is isolated；Wherein, the central area in the area N+ is upper
Surface is higher than the upper surface in P- body area, and the upper surface of the side zones in the area N+ is higher than the upper surface in PN alternating superjunction area；PN is alternately super
Interface is alternately arranged by P+ layers with N+ layers of longitudinal gap, and the upper and lower surface in PN alternating superjunction area is P+ floor.The technical solution
By using organic cooperation in PN alternating the superjunction area and the area N+ of multilayered structure, when gate oxidation is utilized, the oxygen on the area N+ surface
Change the rate rule fast compared with polysilicon, improves the voltage endurance capability of device, improve saturation current, significantly reduce device grids
Layer capacitance is aoxidized, the structural volume of device is reduced while improving device performance, reduces the production cost of device, Jin Erhuan
The pressure resistance technical problem that performance is poor, capacitance resistance is high of the existing technology is solved.
Embodiment two:
Referring to Fig. 3, the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
Flow chart.A kind of production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, packet
It includes:
Step S1: providing N-type substrate (not shown), N+ epitaxial layer is formed in the upper surface of N-type substrate, in N+ extension
The upper surface of layer is formed by P+ layers and the N+ layers of alternately arranged epitaxial layer of longitudinal gap, and the upper and lower surface of epitaxial layer
It is P+ layers.Referring to fig. 4, the production side of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
In method, the product schematic diagram of step S1.
Step S2: groove is formed in the center of epitaxial layer, the bottom of groove extends to the upper surface of N+ epitaxial layer, ditch
The two sides of slot form PN and replace superjunction area.Referring to Fig. 5, vertical double diffused metal-oxide provided in an embodiment of the present invention is partly led
In the production method of body transistor, the product schematic diagram of step S2.It is longitudinal by three floor P+ floor and two layers of N+ floor that PN replaces superjunction area
Arrangement is alternated, and upper and lower surface is P+ layers.P+ layers are respectively the first P+ layers, the 2nd P+ layers and the 3rd P+ from top to bottom
Layer, N+ layer be respectively the first N+ layer with the 2nd N+ layers, the first N+ layers positioned at the first P+ layers and the 2nd between P+ layers, the 2nd N+ layers of position
In the 2nd P+ layers and the 3rd between P+ layers.First P+ layers, the 2nd P+ layers and the 3rd P+ layers of doping concentration successively successively decrease, the first P+
Layer dopant dose is 4E15~5E15, and the 2nd P+ layer of dopant dose is 3E15~4E15, and the 3rd P+ layers of dopant dose is
2E15~3E15.First N+ layers and the 2nd N+ layers of dopant dose is 2E15.The cross-sectional width that PN replaces superjunction area is 5~10
μm.PN replace every layer of P+ floor or N+ floor in superjunction area with a thickness of 2~3 μm.Wherein, the unit of dopant dose be ion number/
Square centimeter.Wherein, P+ layers are p-type heavily doped region, and N+ layer are N-type heavily doped region, when applying reverse biased, PN between source and drain
Alternately superjunction area all exhausts, and undertakes the strong electrical field between source and drain.Opposite traditional devices, the structure are not required to increase terminal pressure resistance knot
Structure significantly reduces device area, thereby reduces the production cost of device.
Step S3: P- epitaxial layer is formed in the trench, carries out surface planarisation after extension.Referring to Fig. 6, the embodiment of the present invention
In the production method of the vertical double diffused metal-oxide semi conductor transistor provided, the product schematic diagram of step S3.
Step S4: a floor exposure mask is deposited in the upper surface in P- epitaxial layer and PN alternating superjunction area, and the width of exposure mask is less than
The overall width of P- epitaxial layer and PN alternating superjunction area, the center of exposure mask opens up fluted, and the bottom of groove extends to P- epitaxial layer
Upper surface.Referring to Fig. 7, the production side of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
In method, the product schematic diagram of step S4.
Step S5: etching is continued to groove and forms deep trench, the bottom of deep trench extends to the upper table of N+ epitaxial layer
Face, and perform etching to form side slot to PN alternating superjunction area along the both ends of exposure mask, the bottom of side slot to N+ epitaxial layer it is upper
Surface.Referring to Fig. 8, in the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention,
The product schematic diagram of step S5.
Step S6: being driven deep trench and side slot by heat and inject N-type ion, exposure mask is removed by wet processing, outside N+
Prolong floor, deep trench and side slot and forms the area N+.Wherein, the area N+ is that the electronics being made of central area, bottom edge area and side zones drifts about
Area, it is P- body area between superjunction area that the central area two sides in the area N+ replace with PN, and the upper surface of the central area in the area N+ is higher than P- body
The upper surface in area, the upper surface of the side zones in the area N+ are higher than the upper surface in PN alternating superjunction area.Referring to Fig. 9, the embodiment of the present invention
In the production method of the vertical double diffused metal-oxide semi conductor transistor provided, the product schematic diagram of step S6.Further
, in vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, the area N+ is N-type heavily doped region, is mixed
Miscellaneous dosage is 1E15~2E15, and cross-sectional width is 2~5 μm.Vertical double diffused metal-oxide provided in an embodiment of the present invention half
In conductor transistor, the area N+ uses the PTBI2T electronics drift layer being polymerize by TBI material.The bottom edge area in the area N+ is highly doped outer
Prolong layer, side zones are longitudinal area N+ by injecting and diffuseing to form, and further, the epitaxial layer concentration in bottom edge area can be higher than
The side zones that longitudinal injection diffuses to form.The technical solution will introduce highly doped inside the epitaxial layer being spaced between drain electrode and source electrode
The area Za N+, reduces the resistivity of epitaxial layer, and then reduces VDMOS device conducting resistance.
Step S7: grid oxic horizon is formed in the junction upper surface in the area N+ and P- body area, on the surface of grid oxic horizon
Deposition forms polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer, and grid oxic horizon and polysilicon gate
Outer edge alignment.Further, the thickness degree at the middle part for the grid oxic horizon being in contact with the central area in the area N+ is greater than grid
The thickness degree of the both wings of oxide layer.Since the area N+ surface is heavy doping, on the area N+ surface, the oxide layer of growth is thicker, with
The N+ plot structure of traditional horizontal type is compared, and when which is utilized gate oxidation, the oxidation rate on the area N+ surface is compared with polysilicon
Fast rule improves the voltage endurance capability of device, improves saturation current, significantly reduces device grids oxidation layer capacitance.Ginseng
See Figure 10, in the production method of vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention, step S7
Product schematic diagram.
Step S8: photoetching is carried out in the two sides P- body area of polysilicon gate and injects to form N+ source region.Referring to Figure 11, the present invention
In the production method for vertical double diffused metal-oxide semi conductor transistor that embodiment provides, the product schematic diagram of step S8.
Step S9: device source metal is formed in the upper surface in the alternating superjunction area PN and N+ source region junction, in the area N+
The upper surface of side zones forms device drain metal, the shape between device source metal, device drain metal and polysilicon gate
It is isolated at dielectric layer, the section view of as Fig. 1 vertical double diffused metal-oxide semi conductor transistor provided in an embodiment of the present invention
Product in figure.When semiconductor devices works, apply positive voltage on polysilicon gate, generates conducting channel, electronics in lower section
From N+ source region, conducting channel is flowed through, is collected by the area N+, is finally flowed out from the device drain metal of the side zones in the area N+.
The production method of vertical double diffused metal-oxide semi conductor transistor provided by the embodiment of the present invention, comprising:
N-type substrate is provided, N+ epitaxial layer is formed in the upper surface of N-type substrate, is formed in the upper surface of N+ epitaxial layer by P+ layers and N+ layers
The alternately arranged epitaxial layer of longitudinal gap forms groove in the center of epitaxial layer, and the bottom of groove extends to outside N+
Prolong the upper surface of layer, the two sides of groove form PN and replace superjunction area；P- epitaxial layer is formed in the trench, is handed in P- epitaxial layer and PN
A floor exposure mask is deposited for the upper surface in superjunction area, the center of exposure mask opens up fluted, and the bottom of groove extends to P- epitaxial layer
Upper surface；Etching is continued to groove and forms deep trench, and performs etching to be formed to PN alternating superjunction area along the both ends of exposure mask
Side slot, deep trench and side slot are driven by heat and injects N-type ion, remove exposure mask, N+ epitaxial layer, zanjon by wet processing
Slot and side slot form the area N+；Grid oxic horizon is formed in the junction upper surface in the area N+ and P- body area, in grid oxic horizon
Surface deposits to form polysilicon gate, grid oxic horizon and polysilicon gate extremely " convex " type layer；In the two sides P- of polysilicon gate
Body area carries out photoetching and injects to form N+ source region；Device source electrode gold is formed in the upper surface in the alternating superjunction area PN and N+ source region junction
Belong to, device drain metal is formed in the upper surface of the side zones in the area N+, in device source metal, device drain metal and polysilicon
Dielectric layer isolation is formed between grid.The technical solution is matched by using the PN alternating superjunction area of multilayered structure with the organic of the area N+
It closes, when gate oxidation is utilized, the oxidation rate on the area the N+ surface rule fast compared with polysilicon improves the voltage endurance capability of device,
Saturation current is improved, device grids oxidation layer capacitance is significantly reduced, the knot of device is reduced while improving device performance
Structure volume, reduces the production cost of device, and then alleviates the pressure resistance skill that performance is poor, capacitance resistance is high of the existing technology
Art problem.
In the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " connects " connected "
Connect " it shall be understood in a broad sense, for example, it may be being fixedly connected, it may be a detachable connection, or be integrally connected；It can be machine
Tool connection, is also possible to be electrically connected；It can be directly connected, two members can also be can be indirectly connected through an intermediary
Connection inside part.For the ordinary skill in the art, above-mentioned term can be understood in the present invention with concrete condition
Concrete meaning.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (9)
1. a kind of vertical double diffused metal-oxide semi conductor transistor characterized by comprising N-type substrate, the area N+, P- body
Area, PN alternating superjunction area, N+ source region, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and device leakage
Pole metal；
The area N+ is the electronics drift region being made of central area, bottom edge area and side zones；
The top of the N-type substrate is connect with the bottom edge area in the area N+, and the inner surface in the area N+ extends to institute to central area
The area ShuP-Ti, PN alternating superjunction area are located at the two sides of central area, the side zones in the area N+ and P- body area in the area N+
Between, the upper surface in P- body area replaces superjunction area connection with the PN equipped with the N+ source region, the gate oxidation
Floor be covered in the N+ source region, the area N+, P- body area junction upper surface, be equipped with the polysilicon above the grid oxic horizon
Grid, the grid oxic horizon and polysilicon gate extremely " convex " type layer, the alternating superjunction area PN and N+ source region junction
Upper surface be provided with device source metal, the upper surface of the side zones in the area N+ is equipped with device drain metal, the polycrystalline
The upper surface of silicon gate and its between the device source metal, between the device source metal and device drain metal
It is provided with the dielectric layer isolation；
Wherein, the upper surface of the central area in the area N+ be higher than P- body area upper surface, the side zones in the area N+ it is upper
Surface is higher than the upper surface in PN alternating superjunction area；
PN alternating superjunction area is alternately arranged by P+ floor and N+ floor longitudinal gap, and the upper and lower surface in PN alternating superjunction area
It is P+ layers.
2. vertical double diffused metal-oxide semi conductor transistor according to claim 1, which is characterized in that the PN
Alternately superjunction area is alternately arranged by three floor P+ floor and two layers of N+ floor longitudinal gap, and upper and lower surface is P+ layers；
Described P+ layers be from top to bottom respectively the first P+ layer, the 2nd P+ layers and the 3rd P+ layers, described N+ layers respectively the first N+ layers
With the 2nd N+ layers, the described first N+ layers be located at the first P+ layer and the 2nd between P+ layer, the described 2nd N+ layers positioned at the 2nd P+ layers and
3rd between P+ layers.
3. vertical double diffused metal-oxide semi conductor transistor according to claim 2, which is characterized in that described
One P+ layers, the 2nd P+ layers and the 3rd P+ layers of doping concentration successively successively decrease, the described first P+ layers of dopant dose are 4E15~5E15,
Described 2nd P+ layers dopant dose be 3E15~4E15, the described 3rd P+ layer dopant dose be 2E15~3E15, wherein mix
The unit of miscellaneous dosage is ion number/square centimeter.
4. vertical double diffused metal-oxide semi conductor transistor according to claim 2 or 3, which is characterized in that described
First N+ layers and the 2nd N+ layer of dopant dose is 2E15, and the unit of dopant dose is ion number/square centimeter.
5. vertical double diffused metal-oxide semi conductor transistor according to claim 1, which is characterized in that with the N
The thickness degree at the middle part for the grid oxic horizon that the central area in+area is in contact is greater than the thickness degree of the both wings of grid oxic horizon.
6. vertical double diffused metal-oxide semi conductor transistor according to claim 1, which is characterized in that the N+
Area be N-type heavily doped region, dopant dose be 1E15~2E15, cross-sectional width be 2~5 μm, wherein the unit of dopant dose be from
Sub- number/square centimeter.
7. vertical double diffused metal-oxide semi conductor transistor according to claim 1, which is characterized in that the PN
Alternately the cross-sectional width in superjunction area is 5~10 μm.
8. vertical double diffused metal-oxide semi conductor transistor according to claim 1, which is characterized in that the PN
Alternately in superjunction area every layer of P+ floor or N+ floor with a thickness of 2~3 μm.
9. a kind of production method of vertical double diffused metal-oxide semi conductor transistor characterized by comprising
N-type substrate is provided, N+ epitaxial layer is formed in the upper surface of the N-type substrate, is formed in the upper surface of the N+ epitaxial layer
By P+ layers and the N+ layers of alternately arranged epitaxial layer of longitudinal gap, and the upper and lower surface of the epitaxial layer is P+ layers；
Groove is formed in the center of the epitaxial layer, the bottom of groove extends to the upper surface of N+ epitaxial layer, and the two of groove
Side forms PN and replaces superjunction area；
P- epitaxial layer is formed in the trench, carries out surface planarisation after extension；
A floor exposure mask is deposited in the upper surface in the P- epitaxial layer and PN alternating superjunction area, and the width of the exposure mask is less than described
The overall width of P- epitaxial layer and PN alternating superjunction area, the center of the exposure mask open up fluted, and the bottom of groove extends to described
The upper surface of P- epitaxial layer；
Etching is continued to the groove and forms deep trench, the bottom of deep trench extends to the upper surface of N+ epitaxial layer, and edge
The both ends of the exposure mask perform etching to form side slot to PN alternating superjunction area, the upper table of the bottom of side slot to N+ epitaxial layer
Face；
The deep trench and side slot are driven by heat and inject N-type ion, the exposure mask is removed by wet processing, outside the N+
Prolong floor, deep trench and side slot and forms the area N+；
Grid oxic horizon is formed in the junction upper surface in the area N+ and P- body area, is deposited on the surface of grid oxic horizon
Form polysilicon gate, the grid oxic horizon and polysilicon gate extremely " convex " type layer；
The P- body area described in the two sides of polysilicon gate carries out photoetching and injects to form N+ source region；
Device source metal is formed in the upper surface in the alternating superjunction area the PN and N+ source region junction, in the area N+
The upper surfaces of side zones forms device drain metal, the device source metal, device drain metal and polysilicon gate it
Between formed dielectric layer isolation.
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