CN114695557B - VDMOS device for lithium battery charging management and preparation method thereof - Google Patents
VDMOS device for lithium battery charging management and preparation method thereof Download PDFInfo
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- CN114695557B CN114695557B CN202210331241.9A CN202210331241A CN114695557B CN 114695557 B CN114695557 B CN 114695557B CN 202210331241 A CN202210331241 A CN 202210331241A CN 114695557 B CN114695557 B CN 114695557B
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- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910052744 lithium Inorganic materials 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000007726 management method Methods 0.000 title description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000002347 injection Methods 0.000 claims abstract description 60
- 239000007924 injection Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 210000000746 body region Anatomy 0.000 claims abstract description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 239000007943 implant Substances 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000227 grinding Methods 0.000 claims 1
- 238000002513 implantation Methods 0.000 description 15
- 238000001514 detection method Methods 0.000 description 13
- 238000000407 epitaxy Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The invention discloses a VDMOS device for lithium battery charge management, which comprises a substrate, a first epitaxial layer, a first groove extending from the first epitaxial layer to the substrate, a second epitaxial layer filled in the first groove, a second groove positioned between the first grooves and extending to the substrate, a first silicon oxide layer filled in the second groove, a second silicon oxide layer formed on the second groove and the first epitaxial layer, an opening positioned between the second silicon oxide layers, and a polysilicon layer on the second silicon oxide layer, a body region between the second grooves, a first injection region positioned in the body region and connected with the second silicon oxide layer by the opening, a second injection region positioned between the first injection regions, a third injection region extending to the first groove and connected with part of the second groove on the lower surface of the substrate, and a first metal layer, a second metal layer and a third metal layer. The invention also provides a preparation method of the VDMOS device for lithium battery charging management, which improves the over-temperature feedback rate and improves the working stability of lithium battery charging management.
Description
Technical Field
The invention relates to the field of lithium battery charging management, in particular to a VDMOS device for lithium battery charging management and a preparation method thereof.
Background
With the development of technology, lithium batteries are widely used in the fields of life, military, etc., due to their special charge and discharge characteristics. However, because the lithium battery has certain limitations in use, such as when charging, if current is not limited, the battery is overheated and even explodes in the charging process, which causes great threat to personal safety, and the charging temperature of the lithium battery is too high, so that the service life of the battery is accelerated to be reduced. Therefore, it is necessary to effectively control and thermally manage the charging of the lithium battery, so as to avoid the overheat phenomenon of the lithium battery. In the charging process, the lithium battery is heated and damaged due to the excessively high charging current, so that the overcurrent protection capability is also necessary for the lithium battery charging system.
For the above reasons, a temperature sensor and an over-temperature protection circuit must be arranged in a lithium battery charging system, and the charging system is subjected to temperature detection and over-temperature protection by an over-current protection circuit. The temperature and current sensor can monitor the temperature and charging current of the system in real time, and feed information back to the protection circuit, when the temperature of the system is too high or the current is too high, the protection circuit can timely turn off the VDMOS, so that the lithium battery is prevented from being damaged due to over-temperature and over-current. Because the charging current is too large when the temperature is too high, the information of the working environment temperature and the charging current of the device is difficult to extract, and the problem that the system reliability is reduced due to slow over-temperature feedback speed is caused.
Disclosure of Invention
In view of the above, the invention provides a VDMOS integrated with a temperature sensor, which aims to accurately and timely extract the temperature information of the working environment of a device, and when the temperature is too high, the device automatically cuts off the charging current, so that the charging system for the lithium battery can effectively ensure that the lithium battery and the charging system are not affected by over-temperature damage. The novel device is used for a charging system, can reduce manufacturing cost, quickens over-temperature feedback speed, and improves system reliability, and is realized by adopting the following technical scheme.
In a first aspect, the present invention provides a VDMOS device for lithium battery charge management, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a first conductivity type formed on the substrate, wherein the first epitaxial layer extends from the upper surface of the first epitaxial layer to first trenches which are arranged in the substrate at intervals, second epitaxial layers of the first conductivity type are filled in the first trenches, the second epitaxial layers are positioned between the first trenches and extend to second trenches of the substrate, first silicon oxide layers are filled in the second trenches, and the depth of the second trenches is larger than that of the first trenches;
a second silicon oxide layer formed on the second trench and the first epitaxial layer at intervals, an opening between the second silicon oxide layers, and a polysilicon layer formed on the second silicon oxide layer;
a body region of a second conductivity type formed between the second trenches, a first implant region of a first conductivity type formed in the body region at a distance from a lower surface of the opening and connected to the second silicon oxide layer, a second implant region of the second conductivity type formed between the first implant regions, and a third implant region of the second conductivity type formed on a lower surface of the substrate and extending to the first trenches and connected to a portion of the second trenches;
the first epitaxial layer is formed on the first epitaxial layer, the first dielectric layer is formed on part of the first groove, the second dielectric layer is formed on part of the first groove and the polycrystalline silicon layer and is connected with the first injection region, the first contact hole is formed between the first dielectric layer and the second dielectric layer, and the second contact hole penetrates through the second dielectric layer and is positioned in the opening and is connected with part of the first injection region and the second injection region;
the semiconductor device comprises a first dielectric layer, a first metal layer, a second metal layer and a third metal layer, wherein the first metal layer is formed on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, the second metal layer is formed on the lower surface of the substrate and is arranged corresponding to the third injection region, and the third metal layer is formed on the lower surface of the substrate between the third injection regions.
In a second aspect, the present invention also provides a method for preparing a VDMOS device for lithium battery charging management, including the following steps:
providing a substrate of a first conductivity type, and forming a first epitaxial layer of the first conductivity type on the substrate;
forming first grooves which extend from the upper surface of the first epitaxial layer to the inside of the substrate in a photoetching manner, filling first conductive type ions into the first grooves to form second epitaxial layers, forming second grooves which extend into the inside of the substrate through the first epitaxial layers in a photoetching manner between the first grooves, filling first silicon oxide layers into the second grooves, wherein the depth of the second grooves is larger than that of the first grooves;
forming second silicon dioxide layers which are arranged at intervals on the second groove and the first epitaxial layer, forming openings between the second silicon dioxide layers, and forming a polysilicon layer on the second silicon dioxide layers;
forming a body region of a second conductivity type between the second trenches, a first injection region of a first conductivity type in the body region and located on the lower surface of the opening and connected with the second silicon dioxide layer to form a space arrangement, a second injection region of the second conductivity type located between the first injection regions, and a third injection region of the second conductivity type extending to the lower surface of the substrate to the first trenches to form a connection with part of the second trenches;
forming a first dielectric layer on the first epitaxial layer and part of the first groove, forming a second dielectric layer connected with the first injection region on part of the first groove and the polysilicon layer, forming a first contact hole between the first dielectric layer and the second dielectric layer, and forming a second contact hole penetrating the second dielectric layer and positioned in the opening and connected with part of the first injection region and the second injection region;
and forming a first metal layer on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, forming a second metal layer on the lower surface of the substrate and corresponding to the third injection region, and forming a third metal layer on the lower surface of the substrate between the third injection regions.
The invention provides a VDMOS device for lithium battery charging management and a preparation method thereof, which have the following beneficial effects compared with the prior art:
and forming first epitaxial layers with the same conductivity type as the substrate on the substrate, forming first grooves which are arranged at intervals and extend into the substrate from the upper surface of the first epitaxial layers, filling high-resistance epitaxy into the first grooves to form second epitaxial layers, forming second grooves between the first grooves, and filling the first silicon oxide layers into the second grooves to form a plurality of current paths as isolation grooves. The second silicon dioxide layer is formed on the second groove and the first epitaxial layer, the polysilicon layer is formed on the second silicon dioxide layer, the body region, the first injection region and the second injection region are formed in the first epitaxial layer in an ion injection mode, the third injection region connected with the bottoms of the first groove and the second groove is formed in the substrate by ion injection, the second metal layer corresponding to the third injection region is used for outputting over-temperature and over-current detection signals in a circuit, namely, the over-temperature and over-current detection modules are integrated into the device, the working environment temperature of the device can be accurately and timely extracted, the manufacturing cost is reduced, the risk that the lithium battery is prevented from being damaged by the over-temperature is also reduced, and when the temperature is too high, the device automatically cuts off charging current, the over-temperature feedback rate is improved, so that the working stability of the charging management of the lithium battery is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for preparing a VDMOS device for lithium battery charging management according to an embodiment of the present invention;
fig. 2 to fig. 7 are process diagrams of a method for preparing a VDMOS device for lithium battery charging management according to an embodiment of the present invention;
fig. 8 is a circuit diagram of a lithium battery power management system according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a VDMOS device for lithium battery charging management according to an embodiment of the present invention.
The main reference numerals are as follows:
10-a substrate; 11-a first epitaxial layer; 12-a first trench; 13-a second epitaxial layer; 14-a second trench; 15-a first silicon oxide layer; 16-a second silicon dioxide layer; 17-opening; 18-a polysilicon layer; 19-body region; 20-a first implanted region; 21-a second implant region; 22-a third implant region; 23-a first dielectric layer; 24-a second dielectric layer; 25-a first contact hole; 26-a second contact hole; 27-a first metal layer; 28-a second metal layer; 29-third metal layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Referring to fig. 1, fig. 2 to fig. 7, the invention also provides a preparation method of a VDMOS device for lithium battery charging management, which comprises the following steps:
s1: providing a substrate 10 of a first conductivity type, forming a first epitaxial layer 11 of the first conductivity type on the substrate 10;
referring to fig. 2, in this embodiment, substrate 10 is a clean single crystal wafer having a specific crystal plane and suitable electrical, optical and mechanical properties for growing epitaxial layers, and substrate 10 is typically a nitride substrate material. The first conductive type is N type, the second conductive type is P type, N type ions are phosphorus, P type ions are boron, the conductive type of the substrate is the same as that of the first epitaxial layer 11, the substrate is prepared by adopting an epitaxial layer growth technology, the resistivity of the substrate 10 is 0.02-0.005ohm.cm, and the resistivity of the first epitaxial layer 11 is 20-40ohm.cm, so that the subsequent preparation process is facilitated.
S2: forming first trenches 12 which extend from the upper surface of the first epitaxial layer 11 to the inside of the substrate 10 in a photoetching manner, forming second epitaxial layers 13 by filling first conductive type ions into the first trenches 12, forming second trenches 14 which extend into the substrate 10 through the first epitaxial layer 11 between the first trenches 12 in a photoetching manner, and filling first silicon oxide layers 15 into the second trenches 14, wherein the depth of the second trenches 14 is larger than that of the first trenches 12;
referring to fig. 3 and 4, in this embodiment, photoresist (not shown) is coated on the first epitaxial layer 11 at intervals, the first epitaxial layer 11 not covered by the photoresist is removed by dry etching to form two deep trenches, i.e., first trenches 12, which are arranged at intervals, the bottoms of the first trenches 12 are located in the substrate 10, the first trenches 12 are filled with the second epitaxial layer 13 of the first conductivity type, the second epitaxial layer 13 is a high-resistance N-type epitaxy, the epitaxy on the first epitaxial layer 11 is removed by a mechanical polishing method on the epitaxy on the surface of the silicon wafer, and the epitaxy in the first trenches 12 is reserved. Similarly, a second trench 14 is formed on the first epitaxial layer 11 between the first trenches 12 by adopting a dry etching technology, the width of the second trench 14 is smaller than that of the first trench 12, the depth of the second trench 14 is larger than that of the first trench 12, the second trench 14 is connected with the first trench 12, the bottoms of the second trench 14 and the first trench 12 are all positioned in the substrate 10, the first silicon oxide layer 15 is filled in the second trench 14 and can serve as an isolation trench to play a role in shunt isolation, and the second epitaxial layer 13 is a high-resistance N-type epitaxy so that the voltage resistance inside the device can be improved, and the PN junction area is also increased.
S3: forming second silicon dioxide layers 16 arranged at intervals on the second trenches 14 and the first epitaxial layer 11, forming openings 17 between the second silicon dioxide layers 16, and forming polysilicon layers 18 on the second silicon dioxide layers 16;
referring to fig. 5 and 6, in this embodiment, photoresist is coated on the first trench 12 and the first epitaxial layer 11 to expose the first epitaxial layer 11 between the second trench 14 and the second trench 14, silicon oxide is deposited, then a layer of polysilicon is deposited on the silicon oxide, the photoresist is coated on the polysilicon at intervals, and part of polysilicon and silicon oxide are removed from the polysilicon by dry etching in the middle to form a second silicon oxide layer 16, a polysilicon layer 18 and an opening 17 which are arranged at intervals, the thickness of the second silicon oxide layer 16 is smaller than that of the polysilicon layer 18, the second silicon oxide layer 16 is a gate oxide layer, and the polysilicon layer 18 is a gate polysilicon layer.
S4: forming a body region 19 of a second conductivity type between the second trenches 14, a first implant region 20 of a first conductivity type within the body region 19 and on the lower surface of the opening 17 and connected to the second silicon dioxide layer 16 to form a spaced arrangement, a second implant region 21 of the second conductivity type between the first implant regions 20, and a third implant region 22 of the second conductivity type extending from the lower surface of the substrate 10 to the first trenches 12 to form connections to a portion of the second trenches 14;
referring to fig. 7, in the present embodiment, second conductivity type ions are implanted into the first epitaxial layer 11 along the opening 17 and diffused to form a body region 19, the upper surface of the body region 19 is connected with the two second silicon dioxide layers 16, the first conductivity type ions, the second conductivity type ions are sequentially implanted into the body region 19 along the opening 17 to form a first implantation region 20 and a second implantation region 21 located between the first implantation regions 20, the second conductivity type ions are implanted into the bottom of the first trench 12 and the bottom of the second trench 14 from the lower surface of the substrate 10 to form a third implantation region 22, the doping concentration of the first implantation region 20 and the second implantation region 21 is greater than that of the body region 19, the first implantation region 20 is symmetrically arranged about the second implantation region 21, the width of the opening 17 is smaller than the sum of the lateral widths of the two first implantation region 20 and the second implantation region 21, so as to increase the switching frequency of the device and reduce the conduction loss.
S5: forming a first dielectric layer 23 on the first epitaxial layer 11 and a part of the first trench 12, forming a second dielectric layer 24 connected with the first injection region 20 on a part of the first trench 12 and the polysilicon layer 18, forming a first contact hole 25 between the first dielectric layer 23 and the second dielectric layer 24, and forming a second contact hole 26 penetrating the second dielectric layer 24 and located in the opening 17 and connected with a part of the first injection region 20 and the second injection region 21;
referring to fig. 7 again, in this embodiment, dielectric growth is performed on the first epitaxial layer 11, the first trench 12, the polysilicon layer 18 and in the opening 17, a dry etching is used to remove a part of the dielectric located on the first trench 12 to form a first dielectric layer 23 located on the first epitaxial layer 11 and a part of the first trench 12, a second dielectric layer 24 located on a part of the first trench 12, the polysilicon layer 18 and connected to the second injection region 21, a first contact hole 25 is formed between the first dielectric layer 23 and the second dielectric layer 24, the second dielectric layer 24 is symmetrically arranged with respect to the second injection region 21, a second contact hole 26 connected to a part of the first injection region 20 and the second injection region 21 is formed between the second dielectric layers 24, and the width of the second contact hole 26 is larger than the width of the first contact hole 25.
S6: a first metal layer 27 is formed on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26, a second metal layer 28 is formed on the lower surface of the substrate 10 and is disposed corresponding to the third implantation region 22, and a third metal layer 29 is formed on the lower surface of the substrate 10 between the third implantation regions 22.
Referring to fig. 7 again, in this embodiment, a first metal layer 27 is formed by depositing metal on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26 by using a magnetron sputtering technology, and likewise, a layer of metal is deposited on the lower surface of the substrate 10, and a part of metal correspondingly disposed in the second trench 14 and part of the third injection region 22 is etched to form a second metal layer 28 arranged at intervals, and a third metal layer 29 between the third injection regions 22, the second metal layer 28 is symmetrically disposed with respect to the third metal layer 29, the projection area of the third injection region 22 in the direction perpendicular to the substrate 10 is larger than the projection area of the second metal layer 28 in the direction perpendicular to the substrate 10, the third metal layer 29 and the body region 19 are just disposed correspondingly, the first metal layer 27 can be used as the source metal of the device, the second metal layer 28 can be used for outputting an over-temperature and over-current detection signal, the third metal layer 29 can be used as the drain metal of the device, the device integrates a temperature sensor structure, can accurately extract the working environment temperature information of the device in time, the automatic battery cutting-off system can be prevented from being used for the automatic battery charging system, the lithium battery can be effectively cut off, the lithium battery can be accelerated when the system is charged, the system can be effectively charged, and the cost can be reduced, and the system can be effectively and the lithium system can be easily damaged.
Referring again to fig. 7, the present invention provides a VDMOS device for lithium battery charge management, including:
a substrate 10 of a first conductivity type;
a first epitaxial layer 11 of a first conductivity type formed on the substrate 10, extending from the upper surface of the first epitaxial layer 11 to first trenches 12 arranged in the substrate 10 at intervals, wherein the first trenches 12 are filled with a second epitaxial layer 13 of the first conductivity type, and second trenches 14 which are positioned between the first trenches 12 and extend to the substrate 10, the second trenches 14 are filled with a first silicon oxide layer 15, and the depth of the second trenches 14 is greater than that of the first trenches 12;
a second silicon oxide layer 16 formed on the second trench 14 and the first epitaxial layer 11 at intervals, an opening 17 between the second silicon oxide layer 16, and a polysilicon layer 18 formed on the second silicon oxide layer 16;
a body region 19 of the second conductivity type formed between the second trenches 14, a first implant region 20 of the first conductivity type formed in the body region 19 at intervals and located at a lower surface of the opening 17 to be connected to the second silicon oxide layer 16, a second implant region 21 of the second conductivity type located between the first implant regions 20, and a third implant region 22 of the second conductivity type formed at a lower surface of the substrate 10 to extend to the first trenches 12 and to be connected to a part of the second trenches 14;
a first dielectric layer 23 formed on the first epitaxial layer 11 and a part of the first trench 12, a second dielectric layer 24 formed on a part of the first trench 12, the polysilicon layer 18 and connected to the first injection region 20, a first contact hole 25 between the first dielectric layer 23 and the second dielectric layer 24, and a second contact hole 26 penetrating the second dielectric layer 24 and connected to a part of the first injection region 20 and the second injection region 21 within the opening 17;
a first metal layer 27 formed on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26, a second metal layer 28 formed on the lower surface of the substrate 10 and disposed in correspondence with the third implantation region 22, and a third metal layer 29 formed on the lower surface of the substrate 10 between the third implantation regions 22.
In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the width of the first trench 12 is greater than the width of the second trench 14, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the first epitaxial layer 11, the doping concentration of the body region 19 is less than the doping concentration of the second implantation region 21, the thickness of the polysilicon layer 18 is greater than the thickness of the second silicon oxide layer 16, and the width of the first contact hole 25 is less than the width of the second contact hole 26. The first trench 12 and the second trench 14 are both prepared by dry etching, the second trench 14 is used as an isolation trench to form a plurality of current paths in the device, the bottoms of the first trench 12 and the second trench 14 are connected with a third injection region 22, the third injection region 22 and the substrate 10 are different in conductivity type and can form a PN junction, the third injection region 22 and the second epitaxial layer 13 are different in conductivity type, the substrate 10 and the first epitaxial layer 11 are the same in conductivity type, and the first epitaxial layer 11 and the body region 19 are different in conductivity type and can form a PN junction. The first silicon oxide layer 15 is formed in an L-shape perpendicular to the second silicon oxide layer 16.
Referring to fig. 8, it should be noted that, in the charge management circuit, the VDMOS device of the present invention integrates an over-temperature and over-current detection system, and after the temperature is too high, the integrated detection system can output a turn-off signal to turn off the VDMOS2, and cut off the charging current, so as to protect the safety of the lithium battery and the system. The functions of the VDMOS and the over-temperature and over-current detection system in the existing system can be completed by only using one novel VDMOS device, the temperature and current detection structure can be integrated in the VDMOS device, the corresponding speed and the temperature measurement accuracy are improved, and meanwhile the manufacturing cost of the charging system is reduced.
Referring to fig. 9, it should be understood that, when the temperature detection and over-temperature and over-current protection structure of the novel VDMOS in the present invention is in a normal working state, the current passes through the channel a, the device is turned on, the system temperature is too high or the current of the channel a is too large, i.e. the charging current is too large, the current channel of the detection system is opened, i.e. the breakdown voltage of the high-temperature junction is reduced, the channel is opened, the voltage drop of the current on the high-resistance epitaxy, i.e. the second epitaxial layer 13 is increased, the NP junction is opened to form a channel, the current passes through the channel B, the over-temperature and over-current detection output signal is turned off, the VDMOS2 is turned off, the charging system stops working, the charging system is turned off after the temperature is reduced, or the current is reduced and returns to normal, and the charging is restored, thereby improving the working reliability of the charging management of the lithium battery to a certain extent.
The invention provides a VDMOS device for lithium battery charge management and a preparation method thereof, wherein a first epitaxial layer 11 with the same conductivity type as the substrate 10 is formed on the substrate 10, first grooves 12 which are arranged at intervals are formed in the substrate 10 by extending from the upper surface of the first epitaxial layer 11, the first grooves 12 are filled with high-resistance epitaxy to form second epitaxial layers 13, second grooves 14 are formed between the first grooves 12, and the second grooves 14 are filled with a first silicon oxide layer 15 as an isolation groove to form a plurality of current paths. The second silicon dioxide layer 16 is formed on the second groove 14 and the first epitaxial layer 11, the polysilicon layer 18 is formed on the second silicon dioxide layer 16, the body region 19, the first injection region 20 and the second injection region 21 are formed in the first epitaxial layer 11 in an ion injection mode, the third injection region 22 connected with the bottoms of the first groove 12 and the second groove 14 is formed in the substrate 10 by ion injection, the second metal layer 28 corresponding to the third injection region 22 is used for outputting over-temperature and over-current detection signals in a circuit, namely, the over-temperature and over-current detection modules are integrated into the device, so that the working environment temperature of the device can be accurately and timely extracted, the manufacturing cost is reduced, the risk of over-temperature damage of a lithium battery can be reduced, and when the temperature is too high, the device automatically cuts off charging current, the over-temperature feedback rate is improved, and the working stability of charging management of the lithium battery is improved.
Any particular values in all examples shown and described herein are to be construed as merely illustrative and not a limitation, and thus other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The above examples merely represent a few embodiments of the present invention, which are described in more detail and are not to be construed as limiting the scope of the present invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.
Claims (9)
1. A VDMOS device for lithium battery charge management, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a first conductivity type formed on the substrate, wherein the first epitaxial layer extends from the upper surface of the first epitaxial layer to first trenches which are arranged in the substrate at intervals, second epitaxial layers of the first conductivity type are filled in the first trenches, the second epitaxial layers are positioned between the first trenches and extend to second trenches of the substrate, first silicon oxide layers are filled in the second trenches, and the depth of the second trenches is larger than that of the first trenches;
a second silicon oxide layer formed on the second trench and the first epitaxial layer at intervals, an opening between the second silicon oxide layers, and a polysilicon layer formed on the second silicon oxide layer;
a body region of a second conductivity type formed between the second trenches, a first implant region of a first conductivity type formed in the body region at a distance from a lower surface of the opening and connected to the second silicon oxide layer, a second implant region of the second conductivity type formed between the first implant regions, and a third implant region of the second conductivity type formed on a lower surface of the substrate and extending to the first trenches and connected to a portion of the second trenches;
the first epitaxial layer is formed on the first epitaxial layer, the first dielectric layer is formed on part of the first groove, the second dielectric layer is formed on part of the first groove and the polycrystalline silicon layer and is connected with the first injection region, the first contact hole is formed between the first dielectric layer and the second dielectric layer, and the second contact hole penetrates through the second dielectric layer and is positioned in the opening and is connected with part of the first injection region and the second injection region;
the semiconductor device comprises a first dielectric layer, a first metal layer, a second metal layer and a third metal layer, wherein the first metal layer is formed on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, the second metal layer is formed on the lower surface of the substrate and is arranged corresponding to the third injection region, and the third metal layer is formed on the lower surface of the substrate between the third injection regions.
2. The VDMOS device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type, and wherein the width of the first trench is greater than the width of the second trench.
3. The lithium battery charge managed VDMOS device of claim 1, wherein the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the body region is less than the doping concentration of the second implant region.
4. The VDMOS device of claim 1, wherein the thickness of the polysilicon layer is greater than the thickness of the second silicon dioxide layer, and the width of the first contact hole is less than the width of the second contact hole.
5. The preparation method of the VDMOS device for lithium battery charging management is characterized by comprising the following steps:
providing a substrate of a first conductivity type, and forming a first epitaxial layer of the first conductivity type on the substrate;
forming first grooves which extend from the upper surface of the first epitaxial layer to the inside of the substrate in a photoetching manner, filling first conductive type ions into the first grooves to form second epitaxial layers, forming second grooves which extend into the inside of the substrate through the first epitaxial layers in a photoetching manner between the first grooves, filling first silicon oxide layers into the second grooves, wherein the depth of the second grooves is larger than that of the first grooves;
forming second silicon dioxide layers which are arranged at intervals on the second groove and the first epitaxial layer, forming openings between the second silicon dioxide layers, and forming a polysilicon layer on the second silicon dioxide layers;
forming a body region of a second conductivity type between the second trenches, a first injection region of a first conductivity type in the body region and located on the lower surface of the opening and connected with the second silicon dioxide layer to form a space arrangement, a second injection region of the second conductivity type located between the first injection regions, and a third injection region of the second conductivity type extending to the lower surface of the substrate to the first trenches to form a connection with part of the second trenches;
forming a first dielectric layer on the first epitaxial layer and part of the first groove, forming a second dielectric layer connected with the first injection region on part of the first groove and the polysilicon layer, forming a first contact hole between the first dielectric layer and the second dielectric layer, and forming a second contact hole penetrating the second dielectric layer and positioned in the opening and connected with part of the first injection region and the second injection region;
and forming a first metal layer on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, forming a second metal layer on the lower surface of the substrate and corresponding to the third injection region, and forming a third metal layer on the lower surface of the substrate between the third injection regions.
6. The method for manufacturing a VDMOS device for lithium battery charge management according to claim 5, wherein the first conductivity type is N-type, the second conductivity type is P-type, the resistivity of the substrate is 0.02-0.005ohm.
7. The method for manufacturing a VDMOS device for lithium battery charge management according to claim 5, wherein the first trench and the second trench are manufactured by dry etching, and a width of the first trench is larger than a width of the second trench.
8. The method for manufacturing a VDMOS device for lithium battery charge management of claim 5, wherein forming a second silicon dioxide layer on the second trench and the first epitaxial layer in a spaced apart arrangement comprises:
firstly, depositing silicon oxide on the first epitaxial layer, the second epitaxial layer and the first silicon oxide layer;
coating photoresist on the silicon oxide corresponding to the first epitaxial layer positioned on the first silicon oxide layer and between the second trenches;
removing the silicon oxide not covered by the photoresist to form a second silicon oxide layer and an opening between the second silicon oxide layers.
9. The method for manufacturing a VDMOS device for lithium battery charge management according to claim 5, wherein the first metal layer, the second metal layer and the third metal layer are manufactured by magnetron sputtering, the first epitaxial layer is removed by mechanical grinding, and the second epitaxial layer in the first trench is reserved to manufacture the second epitaxial layer.
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