KR102583271B1 - Monolithic metal-insulator transition device and method for manufacturing the same - Google Patents

Abstract

A monolithic metal-insulator transition device is provided. A monolithic metal-insulator transition device includes a substrate containing a driving region and a switching region; first and second source/drain regions on the driving region; a gate electrode between the first and second source/drain regions; an inlet well region formed on the switching region and adjacent to a top surface of the substrate; a control well region between the inlet well region and the lower surface of the substrate and having a conductivity type different from that of the inlet well region; a first wiring electrically connecting the first source/drain region and the control well region; and a second wiring electrically connecting the second source/drain region and the inlet well region.

Description

Monolithic metal-insulator transition device and method for manufacturing the same}

The present invention relates to a monolithic metal-insulator transition device including a critical current supply region (drive region) for inducing a metal-insulator transition.

Specifically, the present invention relates to the development of a monolithic metal-insulator-transition device consisting of a combination of two types of transistors integrated on a single substrate, and belongs to the field of semiconductor device design and manufacturing.

A metal-insulator transition device is a switching device that uses state transitions of materials and can be used as a power semiconductor device. A power semiconductor device is a device that performs power control processing within an electronic device. Power semiconductor devices are essentially used in power modules and systems. The power module may include, for example, a DC-DC Converter, a Power Inverter, a Power Supply, etc. The power semiconductor device must have a high breakdown voltage when switched off. , the allowable current must be large when switching on. In addition, power semiconductor devices require low heat generation when turned on. The on-resistance of monolithic metal-insulator transition devices uses negative differential resistance (NDR) characteristics. This can be reduced.

(Patent Document 1) US 9281812 B2 (MIT transistor system including critical current supply device)

(Non-patent document 1) Hyun-tak Kim, 'Negative-differential-resistance-switching Si-transistor operated by power pulse and identity of Zener breakdown', Applied Physics Letters 103, 173501 (2013)

The technical problem to be solved by the present invention is to provide a monolithic metal-insulator transition device that has excellent electrical characteristics and is easy to manufacture.

A monolithic metal-insulator transition device according to embodiments of the present invention for solving the above problems includes a switching region where a metal-insulator-transition switching phenomenon occurs; and a driving region that supplies a critical current to the switching region so that a metal-insulator-transition switching phenomenon occurs, wherein the switching region and the driving region may have a structure that exists on one silicon substrate.

According to embodiments, first and second source/drain regions on the driving region; a gate electrode between the first and second source/drain regions; an inlet well region formed adjacent to the upper surface of the substrate in the switching region and doped with an impurity of a first conductivity type; a control well region doped with impurities of a second conductivity type different from the first conductivity type between the inlet well region and the lower surface of the substrate; a first wiring electrically connecting the first source/drain region and the control well region; and a second wiring electrically connecting the second source/drain region and the inlet well region, and the silicon substrate may be doped with an impurity of the first conductivity type.

A monolithic metal-insulator transition device according to embodiments of the present invention for solving the above problems includes a substrate including a driving region and a switching region; first and second source/drain regions on the driving region; a gate electrode between the first and second source/drain regions; an inlet well region formed on the switching region and adjacent to a top surface of the substrate; a control well region between the inlet well region and the lower surface of the substrate and having a conductivity type different from that of the inlet well region; a first wiring electrically connecting the first source/drain region and the control well region; and a second wiring electrically connecting the second source/drain region and the inlet well region.

According to embodiments, the extended region surrounds the second source/drain region and extends below the gate electrode, and the expanded region may have a lower impurity concentration than the second source/drain region.

According to embodiments, the first source/drain region may include a first impurity region of a first conductivity type and a second impurity region of a second conductivity type different from the first conductivity type.

According to embodiments, it may further include a first contact connecting the first wiring and the first source/drain region and an inlet contact connecting the second wiring and the inlet well region, wherein the bottom of the inlet contact is It may have a larger width than the bottom of the first contact.

According to embodiments, it may further include an inlet contact connecting the second wiring and the inlet well region, and the bottom of the inlet contact may have a width greater than that of the gate electrode.

According to embodiments, the driving region may include a channel well region surrounding the first and second source/drain regions, and the channel well region may have a conductivity type different from that of the substrate.

According to embodiments, the second source/drain region may have the same conductivity type as the inlet well region.

According to embodiments, it includes a metal-insulator transition transistor on the switching region, and the metal-insulator transition transistor may operate in a negative differential resistance (NDR) mode.

According to embodiments, a lower electrode electrically connected to the substrate may be further included on the lower surface of the substrate.

According to embodiments, the control well region may include a plurality of control contact regions having a higher impurity concentration than the control well region.

According to embodiments, the substrate includes a lower layer and an upper layer on the lower layer having a lower impurity concentration than the lower layer, and the control well region may be disposed in the upper layer and connected to the lower layer.

A metal-insulator transition device according to embodiments of the present invention includes a lower electrode; a substrate having a first conductivity type on the lower electrode, the substrate including a driving region and a switching region; a control well region having a second conductivity type different from the first conductivity type on the switching region; an inlet well region having the first conductivity type within the control well region; a first source/drain region including a first impurity region having the first conductivity type and a second impurity region having the second conductivity type on the driving region; first and second source/drain regions having the first conductivity type on the driving region; A gate electrode between the first source/drain region and the second source/drain region, wherein the first source/drain region is electrically connected to the control well region, and the second source/drain region is electrically connected to the control well region. It may be electrically connected to the inlet well area.

According to embodiments, it includes an extended area surrounding the second source/drain area and extending below the gate electrode, wherein the extended area has the first conductivity type, and the extended area includes the second source/drain area. It may have a lower impurity concentration than the drain region.

According to embodiments, a lower electrode electrically connected to the substrate may be further included on the lower surface of the substrate.

According to embodiments, the driving region may include a channel well region surrounding the first and second source/drain regions, and the channel well region may have the second conductivity type.

According to embodiments, the second source/drain region may have the first conductivity type.

According to embodiments, the control well region may include a plurality of control contact regions having a higher impurity concentration than the control well region.

According to embodiments, the substrate includes a lower layer and an upper layer on the lower layer having a lower impurity concentration than the lower layer, and the control well area is disposed in the upper layer and may be in contact with the lower layer.

According to embodiments of the present invention, a monolithic metal-insulator transition device that has excellent electrical properties and is easy to manufacture can be provided.

1 and 2 are equivalent circuit diagrams of monolithic metal-insulator transition devices according to embodiments of the present invention.
Figure 3 is a top view of a monolithic metal-insulator transition device according to embodiments of the present invention.
Figure 4 is a cross-sectional view taken along line II' of Figure 3.
FIGS. 5A and 5B are enlarged cross-sectional views of portions A and B of FIG. 4, respectively.
6A to 6H are graphs showing measured electrical characteristics of monolithic metal-insulator transition devices according to embodiments of the present invention according to Experimental Examples 1 to 6.
Figure 7 is a cross-sectional view of a monolithic metal-insulator transition device according to embodiments of the present invention.
8A to 8P are cross-sectional views for explaining a method of manufacturing a monolithic metal-insulator transition device according to embodiments of the present invention.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms and various changes can be made. However, the description of the present embodiments is provided to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the present invention of the scope of the invention. Those of ordinary skill in the art will understand that the inventive concepts can be practiced in any suitable environment.

The terms used in this specification are for describing embodiments and are not intended to limit the invention. As used herein, singular forms also include plural forms, unless specifically stated otherwise in the context. As used in the specification, 'comprises' and/or 'comprising' refers to the presence of one or more other components, steps, operations and/or elements. or does not rule out addition.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) or substrate or may have a third film (or layer) between them. or layer) may be interposed.

In various embodiments of the present specification, terms such as first and second are used to describe various regions, films (or layers), etc., but these regions and films should not be limited by these terms. These terms are merely used to distinguish one region or film (or layer) from another region or film (or layer). Accordingly, a film quality referred to as a first film quality in one embodiment may be referred to as a second film quality in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Parts indicated with the same reference numerals throughout the specification represent the same elements.

Unless otherwise defined, terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art.

1 and 2 are equivalent circuit diagrams of monolithic metal-insulator transition devices according to embodiments of the present invention.

Referring to FIGS. 1 and 2 , power devices according to embodiments of the present invention may include a metal-insulator transition transistor (MITTR) and an auxiliary transistor (STR). A metal-insulator transition transistor (MITTR) can provide switching operations using changes in the state of the materials that make it up. A change in the state of a material may include a phase transition or a change in the electrical state of the material. The metal-insulator transition transistor (MITTR) may be, for example, a t-switch with a three-terminal structure. The metal-insulator transition transistor (MITTR) may include an inlet terminal (I), an outlet terminal (O), and a control terminal (C). The metal-insulator transition transistor (MITTR) can receive an electrical signal (eg, power) through the inlet terminal (I). The outlet terminal (O) may be an output terminal that outputs an electrical signal under the control of the control terminal (C). The metal-insulator transition transistor (MITTR) can receive current through the control terminal (C) and generate a metal-insulator transition phenomenon between the control terminal (C) and the outlet terminal (O). For example, the metal-insulator transition phenomenon may include a change in state between an insulator or semiconductor material and a metal. Accordingly, the electrical signal applied to the inlet terminal (I) may be output to the outlet terminal (O) or may be limited.

Specifically, as the current (or voltage) applied to the control terminal (C) of the metal-insulator transfer transistor (MITTR) increases, the current between the inlet terminal (I) and the outlet terminal (O) will increase discontinuously. You can. The current between the inlet terminal (I) and the outlet terminal (O) may rapidly increase or decrease based on a specific current value applied to the control terminal (C). At this time, the specific current value may be referred to as the critical current. According to embodiments, when the threshold current is applied to the control terminal (C), the voltage between the inlet terminal (I) and the outlet terminal (O) may decrease. This is referred to herein as Negative Differential Resistance (NDR) mode. That is, the metal-insulator transition transistor (MITTR) according to embodiments of the present invention may operate in the negative differential resistance mode.

The auxiliary transistor (STR) may include, for example, a field effect transistor. The auxiliary transistor (STR) may include a gate terminal (G), a source terminal (S), and a drain terminal (D). The gate terminal (G) may be the manager terminal (M) of a metal-insulator transition element. The source terminal (S) and drain terminal (D) of the auxiliary transistor (STR) may be connected to any one of the control terminal (C) and the inlet terminal (I) of the metal-insulator transition transistor (MITTR) according to embodiments to be described later. You can. The auxiliary transistor (STR) may provide a critical current to the metal-insulator transition transistor (MITTR) to generate a metal-insulator transition phenomenon between the control terminal (C) and the inlet terminal (I).

Referring to FIG. 1, the metal-insulator transition transistor (MITTR) and the auxiliary transistor (STR) may be n-type MOS transistors. The drain terminal (D) of the auxiliary transistor (STR) may be connected to the inlet terminal (I) of the metal-insulator transition transistor (MITTR). The source terminal (S) of the auxiliary transistor (STR) may be connected to the control terminal (C) of the metal-insulator transition transistor (MITTR).

Referring to FIG. 2, the metal-insulator transition transistor (MITTR) and the auxiliary transistor (STR) may be p-type MOS transistors. The drain terminal (D) of the auxiliary transistor (STR) may be connected to the outlet terminal (O) of the metal-insulator transition transistor (MITTR). The source terminal (S) of the auxiliary transistor (STR) may be connected to the control terminal (C) of the metal-insulator transition transistor (MITTR).

Figure 3 is a top view of a monolithic metal-insulator transition device according to embodiments of the present invention. Figure 4 is a cross-sectional view taken along line II' of Figure 3.

Referring to FIGS. 3 and 4 , a substrate 100 including a switching region (SWR) and a driving region (CIR) may be provided. The substrate 100 is a semiconductor substrate and may include, for example, one of silicon, silicon carbide, and silicon germanium. The switching region (SWR) and the driving region (CIR) may include a metal-insulator transition transistor (MITTR) and an auxiliary transistor (STR) described with reference to FIGS. 1 and 2, respectively. The switching region SWR and the driving region CIR may be formed to be horizontally adjacent to each other on the substrate 100 . That is, the metal-insulator transition transistor (MITTR) and the auxiliary transistor (STR) according to embodiments of the present invention may be monolithically integrated on one semiconductor substrate.

The substrate 100 may have a first conductivity type. In other words, the substrate 100 may be doped with impurities of the first conductivity type and may include impurities of the first conductivity type. The first conductivity type may include either n-type or p-type. For example, when the substrate 100 is a silicon (Si) substrate, n-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and p-type impurities may include boron. (B), aluminum (Al), gallium (Ga), and indium (In).

The substrate 100 may include a lower layer 101 and an upper layer 102 on the lower layer 101 . The lower layer 101 may include, for example, a silicon wafer. The upper layer 102 may include an epitaxial layer grown from the lower layer 101. The lower layer 101 and the upper layer 102 may have different impurity concentrations. For example, the impurity concentration of the upper layer 102 may be lower than that of the lower layer 101.

Impurity regions may be provided on the switching region (SWR) and driving region (CIR) of the substrate 100. The impurity regions may be regions within the substrate 100 that are doped with a dose different from that of the substrate 100 . Each of the impurity regions may have the same or different conductivity type than the substrate 100. For example, the impurity regions on the switching region SWR may include a control well region 210, an inlet well region 220, an inlet contact region 222, and control contact regions 212. For example, the impurity regions on the driving region CIR may include a channel well region 302, a first source/drain region 310, a second source/drain region 320, and an extension region 321. Hereinafter, for concise description of embodiments of the present invention, terms meaning boundaries of impurity regions (eg, bottom of impurity regions) may be used. The impurity regions may have a peak concentration in an area adjacent to the upper surface 100u of the substrate 100, and may have a smaller concentration as they approach the lower surface 100l of the substrate 100. In this specification, the boundary of the impurity region may be defined as a portion having an impurity concentration of 1% or more, based on the portion where the peak concentration of the impurity region appears. The first source/drain region 310 may be one of a source region and a drain region. The second source/drain region 320 may be different from the first source/drain region 310 among the source and drain regions.

A control well region 210 may be provided on the substrate 100 of the switching region (SWR). The control well region 210 may be a region in the substrate 100 doped with an impurity of a conductivity type different from that of the substrate 100 . The control well region 210 may have a second conductivity type different from the first conductivity type. For example, when the substrate 100 has an n-type type, the control well region 210 may have a p-type type. The control well area 210 may be formed at the top of the substrate 100 and may have a bottom that is closer to the lower surface 100l than the upper surface 100u of the substrate 100. According to embodiments, the control well region 210 may have an impurity concentration that gradually decreases from the upper surface 100u to the lower surface 100l of the substrate 100.

Control contact areas 212 may be provided within the control well area 210. The control contact areas 212 may be located adjacent to the upper surface 100u of the substrate 100. The control contact areas 212 may be spaced apart from each other with an inlet well area 220, which will be described later, interposed therebetween. The control contact areas 212 may have a second conductivity type. Each of the control contact regions 212 may have a higher impurity concentration than the control well region 210 .

An inlet well area 220 may be provided within the control well area 210. The inlet well region 220 may have a first conductivity type. The inlet well area 220 may be located between the control contact areas 212 . The bottom of the inlet well area 220 may be located at a lower level than the bottoms of the control contact areas 212 . The bottom of the inlet well area 220 may be located at a higher area than the bottom of the control well area 210. In other words, at least a portion of the control well area 210 may be located between the inlet well area 220 and the lower surface 100l of the substrate 100.

An inlet contact area 222 may be provided within the inlet well area 220. The inlet contact area 222 may have a first conductivity type. The inlet contact region 222 may have a higher impurity concentration than the inlet well region 220 .

A channel well region 302 may be provided on the substrate 100 in the driving region CIR. The channel well area 302 may be horizontally spaced apart from the control well area 210. Channel well region 302 may be electrically insulated from control well region 210. According to embodiments, a device isolation region may be formed between the control well region 210 and the channel well region 302. As an example, the device isolation region may include impurities of a second conductivity type doped at a high concentration. As another example, the device isolation region may include a trench and an insulating film that fills the inside of the trench.

A first source/drain region 310 and a second source/drain region 320 may be provided in the channel well region 302. The first and second source/drain regions 310 and 320 may be spaced apart from each other with the gate electrode 330 therebetween. Source/drain area may mean one of a source area and a drain area. For example, the first source/drain region 310 may be one of the source region and the drain region, and the second source/drain region 320 may be different from the first source/drain region 310 among the source region and drain region. It could be one. For example, the first and second source/drain regions 310 and 320 may be the source (S) and drain (D) of the auxiliary transistor (STR) described with reference to FIG. 1, respectively.

The gate electrode 330 may be formed between the first source/drain region 310 and the second source/drain region 320. The gate electrode 330 may include, for example, polysilicon. A gate spacer 331 may be provided on the sidewall of the gate electrode 330. The gate spacer 331 may not cover the top surface of the gate electrode 330. The gate spacer 331 may include, for example, at least one of silicon oxide and silicon nitride.

The first source/drain region 310 may include a first impurity region 311, a second impurity region 312, and a third impurity region 313. The second impurity region 312 may be located between the first impurity region 311 and the third impurity region 313. The first impurity region 311 and the second impurity region 312 may have a first conductivity type. The third impurity region 313 may have a second conductivity type. At this time, the first impurity region 311 may have a lower impurity concentration than the second impurity region 312.

The second source/drain region 320 may have a first conductivity type. The second source/drain region 320 may be horizontally spaced from the sidewall of the gate electrode 330.

An extended area 321 having a bottom located at a lower level than the second source/drain area 320 may be provided on the second source/drain area 320 . The extended area 321 may surround the second source/drain area 320 . The expansion area 321 may extend below the gate electrode 330. The extended region 321 may have a lower impurity concentration than the second source/drain region 320 .

An upper insulating film 104 may be provided on the upper surface 100u of the substrate 100. The upper insulating layer 104 extends between the gate electrode 330 and the channel well region 302 and may function as a gate insulating layer. The upper insulating film 104 may be formed entirely on the upper surface 100u of the substrate 100. The upper insulating film 104 may include, for example, silicon oxide.

A field insulating layer 103 may be provided between the switching region (SWR) and the driving region (CIR). The field insulating layer 103 may be connected to the upper insulating layer 104. The field insulating film 103 may have a thicker thickness than the upper insulating film 104. The field insulating layer 103 may include, for example, silicon oxide.

An interlayer insulating film 110 may be provided on the upper surface 100u of the substrate 100. The interlayer insulating film 110 may cover the gate electrode 330, the gate spacer 331, the upper insulating film 104, and the field insulating film 103. The interlayer insulating film 110 may include, for example, one of silicon oxide, silicon nitride, and silicon oxynitride.

A first wiring 412, a second wiring 414, and a third wiring 420 may be provided on the interlayer insulating film 110. The first wiring 412 may electrically connect the first source/drain region 310 and the control well region 210. The second wiring 414 may electrically connect the second source/drain region 320 and the inlet well region 220. The first wire 412 and the second wire 414 may be electrically insulated from each other. The third wiring 420 may be electrically connected to the gate electrode 330. The first wiring 412, the second wiring 414, and the third wiring 420 may be electrically separated from each other. The second wire 414 and the third wire 420 are connected to different terminals and can be controlled independently.

The first contact 431 and the second contact 432 penetrate the interlayer insulating film 110 and the upper insulating film 104 and are connected to the first source/drain region 310 and the second source/drain region 320, respectively. It can be. The bottom of the first contact 431 may contact the second impurity region 312 and the third impurity region 313. The bottom of the second contact 432 may contact the second source/drain region 320 . The first contact 431 may electrically connect the first source/drain region 310 and the first wiring 412. The second contact 432 may electrically connect the second source/drain region 320 and the second wiring 414.

The gate contact 433 may penetrate the interlayer insulating film 110 and be connected to the gate electrode 330. The gate contact 433 may electrically connect the gate electrode 330 and the third wiring 420.

The inlet contact 441 may penetrate the interlayer insulating layer 110 and the upper insulating layer 104 and be connected to the inlet contact region 222 . The inlet contact 441 may be connected to the inlet well region 220 through the inlet contact region 222. The inlet contact 441 may electrically connect the inlet well region 220 to the second wiring 414.

The control contacts 442 may penetrate the interlayer insulating layer 110 and the upper insulating layer 104 and be respectively connected to the control contact regions 212 . Control contacts 442 may be connected to the control well area 210 through control contact areas 212 . The control contacts 442 may electrically connect the control well area 210 to the first wiring 412 .

A lower electrode 140 may be provided on the lower surface 100l of the substrate 100. The lower electrode 140 may completely cover the lower surface 100l of the substrate 100. In other words, the lower electrode 140 may vertically overlap the impurity regions of the switching region (SWR) and the driving region (CIR) of the substrate 100. The lower electrode 140 may be electrically connected to the lower layer 101 of the substrate 100.

FIGS. 5A and 5B are enlarged cross-sectional views of portions A and B of FIG. 4, respectively.

Referring to FIGS. 4, 5A, and 5B, the monolithic metal-insulator transition device may be a power semiconductor device that receives power through the inlet contact 441 and outputs power through the lower electrode 140. . A higher current may be applied to the inlet contact 441 and the lower electrode 140 than to the first and second contacts 431 and 432. For example, the inlet contact 441 may be connected in parallel with the second contact 432 and may be configured to receive a higher current than the second contact 432. The width w1 of the lower end of the inlet contact 441 may be larger than the widths w3 of the lower ends of the first and second contacts 431 and 432. The contact area between the bottom of the inlet contact 441 and the inlet contact region 222 is that of the bottoms of the first and second contacts 431 and 432 and the first and second source/drain regions 310 and 320. It may be large compared to the contact area. This can improve the electrical reliability of monolithic metal-insulator transition devices.

According to embodiments, the width w1 of the bottom of the inlet contact 441 may be larger than the widths w2 of the bottom of the control contacts 442. The width (w1) of the bottom of the inlet contact 441 may be larger than the width (w4) of the gate electrode 330. Each of the widths w2 of the lower ends of the control contacts 442 may be larger than each of the widths w3 of the lower ends of the first and second contacts 431 and 432.

6A to 6H are graphs showing the electrical characteristics of monolithic metal-insulator transition elements manufactured according to embodiments of the present invention measured according to Experimental Examples 1 to 6.

[Experimental Example 1]

A constant current was applied to the control terminal of the monolithic metal-insulator transition device according to embodiments of the present invention. The inlet current (I _I ) was measured while linearly increasing the voltage (V _IO ) applied to both ends of the inlet and outlet terminals of the metal-insulator transition transistor, and is shown in Figure 6a. The electrical characteristics of the metal-insulator transition transistor were measured using a Keysight 4156 semiconductor parameter analyzer.

Referring to Figure 6a, when the constant current (Ic) applied to the control terminal is 0A, if the voltage (V _IO ) between the inlet terminal and the outlet terminal is increased, the inlet current (I _I ) increases discontinuously (discontinuous jump). can confirm. In addition, it can be seen that the voltage (V _IO ) between the inlet terminal and the outlet terminal decreases in the section where discontinuous jumps are observed. In addition, it can be seen that as the constant current (Ic) applied to the control terminal increases, the voltage (V _IO ) between the inlet terminal and the outlet terminal decreases during a discontinuous jump. It can be seen that no discontinuous jump is observed when the voltage (V _IO ) between the inlet terminal and the outlet terminal is greater than a certain value.

[Experimental Example 2]

A constant voltage (Vco) was applied between the control terminal and the outlet terminal of the monolithic metal-insulator transition device according to embodiments of the present invention. The inlet current (I _I ) was measured while increasing the voltage (V _IO ) applied to both ends of the inlet terminal and the outlet terminal of the metal-insulator transition transistor, and is shown in FIG. 6b. The Keysight 4156 Semiconductor parameter analyzer was used to measure the electrical characteristics of the metal-insulator transition transistor.

Referring to Figure 6b, when the voltage (Vco) between the control terminal and the outlet terminal is 0V, if the voltage (V _IO ) between the inlet terminal and the outlet terminal is increased, the inlet current (I _I ) increases discontinuously (discontinuously You can check the jump section). Additionally, it can be seen that as the constant voltage (Vco) increases, the voltage (V _IO ) between the inlet terminal and the outlet terminal decreases in the discontinuous jump section. Additionally, it can be seen that a discontinuous jump section is not observed when the voltage (Vco) between the control terminal and the outlet terminal is greater than a certain value.

[Experimental Example 3]

A constant voltage (Vco) was applied between the control terminal and the outlet terminal of the monolithic metal-insulator transition device according to embodiments of the present invention. While increasing the inlet current (I _I ) of the metal-insulator transition transistor, the voltage (V _IO ) applied to both ends of the inlet terminal and the outlet terminal was measured and shown in Figure 6c. The electrical characteristics of the metal-insulator transition transistor were measured using a Keysight 4156 semiconductor parameter analyzer.

Referring to Figure 6c, if the inlet current (I _I ) is increased when the voltage (Vco) between the control terminal and the outlet terminal is 0V, the voltage (V _IO ) between the inlet terminal and the outlet terminal will rapidly and discontinuously decrease. You can. Additionally, when the voltage (Vco) increases between the control terminal and the outlet terminal, the voltage (V _IO ) between the inlet terminal and the outlet terminal may discontinuously decrease. Additionally, when the voltage Vco increases between the control terminal and the outlet terminal, the jump voltage between the inlet terminal and the outlet terminal may decrease. The voltage (Vco) between the control terminal and the outlet terminal may no longer show a phenomenon of discontinuous decrease above a certain voltage. The voltage (Vco) between the control terminal and the outlet terminal can continuously increase above a certain voltage.

Referring again to FIGS. 6A to 6C, it can be seen that the metal-insulator transition transistor according to embodiments of the present invention can operate in a negative differential resistance mode. Accordingly, the metal-insulator transition transistor on resistance may be reduced.

[Experimental Example 4]

A monolithic metal-insulator transition device was formed according to embodiments of the present invention. The device breakdown voltage of the auxiliary transistor was measured and shown in Figure 6d. A monolithic metal-insulator transition device was formed according to embodiments of the present invention, but an auxiliary transistor was formed without the extended region 321 described with reference to FIG. 4 . The device breakdown voltage of the auxiliary transistor was measured and shown in Figure 6e. The electrical characteristics of the metal-insulator transition transistor were measured using a Keysight 4156 semiconductor parameter analyzer.

Referring to FIGS. 6D and 6E, it can be seen that the device breakdown voltage of the auxiliary transistor including the extension region 321 is higher than the device breakdown voltage of the auxiliary transistor formed without the expansion region 321 (see FIG. 4). Since the auxiliary transistor can be connected in parallel with the inlet and control of the metal-insulator transition transistor, it can be seen that the reliability of the monolithic metal-insulator transition device can be improved by the expansion area 321.

[Experimental Example 5]

A monolithic metal-insulator transition device was formed according to embodiments of the present invention. While changing the voltage (V _MO ) applied to the gate of the auxiliary transistor, that is, the manager electrode (M, see FIGS. 1 and 2) of the metal-insulator transition element, the voltage between the inlet terminal and the outlet terminal of the metal-insulator transition transistor The current (I _I ) flowing through the inlet terminal according to (V _IO ) was measured and shown in Figure 6f. Apply a voltage (V _MO ) between the gate of the auxiliary transistor and the outlet terminal of the metal-insulator transition transistor, and measure the current (I _I ) flowing through the inlet terminal according to the voltage (V _IO ) between the inlet terminal and the outlet terminal. It is shown in Figure 6g. The electrical characteristics of the metal-insulator transition transistor were measured using a Keysight 4156 semiconductor parameter analyzer.

Referring to FIGS. 6F and 6G, it can be seen that a discontinuous jump section occurs depending on the supply of critical current to the auxiliary transistor. It can be seen that as the voltage (V _MO ) applied to the gate of the auxiliary transistor increases, the voltage in the discontinuous jump section decreases. It can be seen that when the voltage (V _MO ) applied to the gate of the auxiliary transistor has a range of more than a predetermined value, no discontinuous jump section is observed.

[Experimental Example 6]

A monolithic metal-insulator transition device was formed according to embodiments of the present invention. The current and voltage characteristics of the monolithic metal-insulator transition device were measured using a Tektronix 370A Curve Trace and are shown in Figure 6h. The electrical characteristics of the metal-insulator transition transistor were measured using a Keysight 4156 semiconductor parameter analyzer.

Referring to FIG. 6H, it can be seen that the on-resistance of the metal-insulator transistor decreases according to the negative differential resistance mode operation of the monolithic metal-insulator transition element.

Figure 7 is a cross-sectional view of a monolithic metal-insulator transition device according to embodiments of the present invention.

Referring to FIG. 7, the control well region 210 of the switching region (SWR) is formed deeper than the channel well region 302 of the driving region (CIR) and may be connected to the lower layer 101 of the substrate 100. . The lower end of the control well area 210 may be located at a vertical level between the lower end of the channel well area 302 and the upper surface of the lower layer 101. The bottom of the control well area 210 may be located at a level that is not higher than the top surface of the lower layer 101.

According to embodiments, the channel well region 302 of the driving region CIR may also be formed to have a bottom located at a level not higher than the top surface of the lower layer 101.

8A to 8P are cross-sectional views for explaining a method of manufacturing a monolithic metal-insulator transition device according to embodiments of the present invention.

Referring to FIG. 8A, a substrate 100 including a lower layer 101 and an upper layer 102 can be prepared. The lower layer 101 can be formed by doping a semiconductor substrate with a first conductivity type impurity at a high concentration. The upper layer 102 can be formed by performing an epitaxial growth process on the upper surface of the lower layer 101. The epitaxial growth process may include, for example, a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. When forming the upper layer 102, a lower dose of impurities may be injected than that of the lower layer 101. For example, the upper layer 102 may be doped by injecting impurities of the first conductivity type at a dose ranging from 4 x 10 ¹³ cm ^-2 to 6 x 10 ¹³ cm ^-2 . The doping process for the upper layer 102 may be performed in situ.

A buffer insulating layer BP may be formed on the upper surface 100u of the substrate 100. The buffer insulating film BP may be formed using a wet oxidation process or a dry oxidation process. The buffer insulating film BP may completely cover the upper surface 100u of the substrate 100. The thickness of the buffer insulating film BP may range from 100Å to 600Å. A first mask pattern MP1 having a first opening OP1 exposing a portion of the upper surface of the buffer insulating layer BP may be formed on the buffer insulating layer BP. The first mask pattern MP1 may include, for example, photoresist.

First impurity ions (imp1) having a second conductivity type may be implanted into the upper part of the substrate 100 by performing an ion implantation process on the first mask pattern (MP1). The first impurity ions (imp1) may be implanted at a dose of 1x10 ¹² cm ^-3 to 1x10 ¹⁴ cm ^-2 . The first mask pattern MP1 may be removed after the ion implantation process.

Referring to FIG. 8B, a heat treatment process may be performed on the substrate 100 to form a channel well region 302. The channel well region 302 may be formed by diffusion of the first impurity ions imp1 described with reference to FIG. 8A. The heat treatment process may be performed in a temperature range of 950°C to 1250°C. The heat treatment process may be performed in a nitrogen atmosphere.

Referring to FIG. 8C , a second mask pattern MP2 having a second opening OP2 may be formed on the buffer insulating film BP. The second opening OP2 may be located on the channel well area 302 . Second impurity ions (imp2) may be implanted into the upper part of the channel well region 302 by performing an ion implantation process. The second impurity ions (imp2) may be injected at a dose of 1x10 ¹² cm ^-2 to 1x10 ¹⁴ cm ^-2 . The second impurity ions (imp2) may have a first conductivity type. That is, the second impurity ions imp2 may have a different conductivity type than the impurities in the channel well region 302. After the ion implantation process, the second mask pattern MP2 can be removed.

Referring to FIG. 8D , a third mask pattern MP3 having a third opening OP3 may be formed on the buffer insulating layer BP. The third opening OP3 may have a larger width than the first opening OP1 described with reference to FIG. 8A. Third impurity ions (imp3) may be implanted into the upper part of the substrate 100 by performing an ion implantation process. The third impurity ions (imp3) may have a second conductivity type. The third impurity ions (imp3) may have a higher dose than the second impurity ions (imp2). The third impurity ions (imp3) may be injected at a dose of 5x10 ¹² cm ^-2 to 5x10 ¹⁴ cm ^-2 . After the ion implantation process, the third mask pattern MP3 can be removed.

Referring to FIGS. 8D and 8E, a heat treatment process may be performed on the substrate 100 to form an expansion area 321 and a control well area 210. The expansion area 321 and the control well area 210 may be formed simultaneously through one heat treatment process. The extended area 321 may be formed by diffusion of second impurity ions (imp2), and the control well area 210 may be formed by diffusion of third impurity ions (imp3). The heat treatment process may be performed in a temperature range of 900°C to 1200°C. The heat treatment process may be performed in a nitrogen atmosphere.

After exposing the upper surface 100u of the substrate 100, the first buffer insulating film BP1 and the second buffer insulating film BP2 may be formed on the upper surface 100u of the substrate 100. The first buffer insulating layer BP1 may include, for example, silicon oxide. The second buffer insulating layer BP2 may include, for example, silicon nitride. The first buffer insulating film BP1 may have a thickness in the range of 100ÅÅ. The second buffer insulating layer BP2 may be thicker than the first buffer insulating layer BP1. The second buffer insulating film BP2 may have a thickness ranging from 1000Å to 2000Å.

Referring to FIG. 8F , a fourth mask pattern MP4 having a fourth opening OP4 may be formed on the second buffer insulating layer BP2. The fourth opening OP4 may be located in the space between the channel well area 302 and the control well area 210. The upper surface of the first buffer insulating layer BP1 may be partially exposed by performing an etching process using the fourth mask pattern MP4. After the etching process, the fourth mask pattern MP4 can be removed.

Referring to FIG. 8G, a wet oxidation process may be performed on the first buffer insulating layer BP1 to form a field insulating layer 103 having a thicker thickness than the first buffer insulating layer BP1. Wet oxidation processes may include, for example, pyrogenic wet oxidation. The field insulating film 103 may have a thickness ranging from 3000 Å to 8000 Å, for example. After performing the wet oxidation process, the second buffer insulating layer BP2 may be removed.

Referring to FIG. 8H, a fifth mask pattern MP5 having a fifth opening OP5 may be formed on the first buffer insulating layer BP1. The fifth opening OP5 may be located on the control well area 210 . Fourth impurity ions (imp4) may be implanted into the control well region 210 by performing an ion implantation process. The fourth impurity ions imp4 may have a first conductivity type. The fourth impurity ions (imp4) may be injected at a dose of 5x10 ¹³ cm ^-3 to 7 x10 ¹⁵ cm ^-2 . After the ion implantation process, the fifth mask pattern MP5 can be removed.

Referring to FIG. 8H and FIG. 8I , the inlet well region 220 may be formed by performing a heat treatment process on the substrate 100. The heat treatment process may be performed in a temperature range of 900°C to 1100°C. The heat treatment process may be performed in a nitrogen atmosphere.

The first buffer insulating layer BP1 may be removed, and an upper insulating layer 104 covering the upper surface 100u of the substrate 100 may be formed. The upper insulating film 104 may be connected to the field insulating film 103. The upper insulating film 104 may have a thinner thickness than the field insulating film 103. The upper insulating film 104 may have a thickness ranging from 100 Å to 1000 Å, for example.

A gate electrode 330 may be formed on the channel well region 302. The gate electrode 330 may partially overlap the extended area 321. Forming the gate electrode 330 may include forming a polysilicon layer on the upper surface 100u of the substrate 100 and patterning the polysilicon layer. The polysilicon layer can be deposited using low pressure chemical vapor deposition (LPCVD). The polysilicon layer can be doped by heat treatment in a POCl ₃ atmosphere.

Referring to FIG. 8J , a sixth mask pattern MP6 having sixth openings OP6 may be formed on the upper insulating film 104. The sixth openings OP6 may be located on the channel well area 302, the expansion area 321, and the inlet well area 220, respectively. The sixth opening OP6 on the channel well region 302 may partially overlap the gate electrode 330. An ion implantation process may be performed to implant fifth impurity ions (imp5) into the channel well region 302, expansion region 321, and inlet well region 220. The fifth impurity ions imp5 may have a first conductivity type. The fifth impurity ions (imp5) may be implanted at a dose of 5x10 ¹² cm ^-3 to 1x10 ¹⁴ cm ^-2 . After the ion implantation process, the sixth mask pattern MP6 can be removed.

Referring to FIG. 8K, preliminary impurity regions 315 may be formed by performing a heat treatment process on the substrate 100. The heat treatment process may be performed in a temperature range of 800°C to 1050°C. The heat treatment process may be performed in a nitrogen atmosphere.

A gate spacer 331 may be formed on the sidewalls of the gate electrode 330. Forming the gate spacer 331 may include forming an insulating film on the front surface of the substrate 100 and isotropically etching the insulating film to leave a portion of the insulating film on the sidewalls of the gate electrode 330.

Referring to FIG. 8L , a seventh mask pattern MP7 having seventh openings OP7 may be formed on the substrate 100. The seventh openings OP7 may be located on the preliminary impurity region 315 . The sixth impurity ions (imp6) may be implanted into the preliminary impurity region 315 by performing an ion implantation process. At this time, a portion of the preliminary impurity region 315 may be obscured by the gate spacer 331. The sixth impurity ions imp6 may have a first conductivity type. The sixth impurity ions (imp6) may be implanted at a higher dose than the fifth impurity ions (imp5). For example, the sixth impurity ions (imp6) may be injected at a dose of 1x10 ¹⁵ cm ^-2 to 9x10 ¹⁵ cm ^-2 . After the ion implantation process, the seventh mask pattern MP7 can be removed.

Referring to FIGS. 8L and 8M , a heat treatment process may be performed on the substrate 100 to form a second impurity region 312, a second source/drain region 320, and an inlet contact region 222. The heat treatment process may be performed in a temperature range of 800°C to 1050°C. The heat treatment process may be performed in a nitrogen atmosphere. The second impurity region 312, the second source/drain region 320, and the inlet contact region 222 may be formed by diffusion of the sixth impurity ions (imp6) implanted into the preliminary impurity region 315. . The second impurity region 312, the second source/drain region 320, and the inlet contact region 222 may have an increased impurity concentration due to additional diffusion of the sixth impurity ions imp6. The first impurity region 311 may be formed from the preliminary impurity region 315 obscured by the gate spacer 331 .

Subsequently, an eighth mask pattern MP8 having eighth openings OP8 may be formed on the substrate 100 . The eighth openings OP8 may be located on the channel well area 302 and the control well area 210, respectively. Seventh impurity ions (imp7) may be implanted into the channel well region 302 and the control well region 210 by performing an ion implantation process. The seventh impurity ions imp7 may have a second conductivity type. The seventh impurity ions (imp7) may later be injected at a dose of 1x10 ¹⁵ cm ^-2 to 9x10 ¹⁵ cm ^-2 . After the ion implantation process, the eighth mask pattern MP8 can be removed.

Referring to FIG. 8N, a heat treatment process may be performed on the substrate 100 to form the third impurity region 313 and the control contact regions 212. The heat treatment process may be performed in a temperature range of 800°C to 1050°C. The heat treatment process may be performed in a nitrogen atmosphere. The first impurity region 311 , second impurity region 312 , and third impurity region 313 may form a first source/drain region 310 .

Referring to FIG. 8O, an interlayer insulating film 110 may be formed on the entire surface of the substrate 100. The interlayer insulating film 110 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The interlayer insulating film 110 may cover the gate electrode 330 and the gate spacer 331. The interlayer insulating film 110 may have a thickness ranging from 3,000 Å to 10,000 Å, for example.

Subsequently, holes H that penetrate the interlayer insulating film 110 may be formed. The holes H may expose the top surfaces of the first and second source/drain regions 310 and 320, control contact regions 212, inlet contact region 222, and gate electrode 330. The hole H exposing the inlet contact area 222 may be formed to have a larger width than the other holes H.

Referring to FIG. 8P, a metal film 450 filling the holes H may be formed on the interlayer insulating film 110. Forming the metal film 450 can be performed using any one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). there is. For example, the metal film 450 may be formed using a sputtering process. A planarization process may be performed on the upper surface of the metal film 450.

Referring again to FIGS. 3 and 4 , the first wiring 412, the second wiring 414, and the third wiring 420 can be formed by patterning the metal film 450 on the upper surface of the interlayer insulating film 110. there is. The first wiring 412, the second wiring 414, and the third wiring 420 may be electrically separated from each other.

The lower electrode 140 may be formed on the lower surface 100l of the substrate 100. The lower electrode 140 may be formed on the entire surface of the lower surface 100l of the substrate 100 using a physical vapor deposition (PVD) process. A physical vapor deposition (PVD) process may include, for example, a sputtering process.

A person skilled in the art to which the invention pertains will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: substrate 101: lower layer
102: upper layer 103: field insulating film
104: upper insulating film 110: interlayer insulating film
140: lower electrode 210: control well area
212: control contact area 220: inlet well area
222: inlet contact area 302: channel well area
310: first source/drain area 320: second source/drain area
321: expansion area 330: gate electrode
331 gate spacer 412: first wiring
414: second wiring 420: third wiring
431: first contact 432: second contact
433: gate contact 441: inlet contact
442: Control contact

Claims (20)

lower electrode;
a substrate provided on the lower electrode, having a first impurity, a driving region and a switching region in contact with the driving region;
a channel well region provided within the substrate in the driving region and having a second impurity;
a gate electrode on the center of the channel well region;
a first source/drain region provided on one side of the channel well region and having the first impurity;
a second source/drain region provided on the other side of the channel well region, having the first impurity and being deeper than the first source/drain region;
a control well region provided within the substrate in the switching region and having a depth different from that of the second impurity and the channel well region;
an inlet well region provided within the center of the control well region;
an inlet contact area provided within the center of the inlet well area and having a first depth;
a control contact area within the edge of the control well area outside both sides of the inlet well area;
a first contact provided on the first source/drain region;
a second contact provided on the second source/drain region;
a gate contact provided on the gate electrode;
an inlet contact provided on the inlet contact area;
a control contact provided on the control contact area;
a first wire connecting the first contact to the control contact;
a second wire connecting the second contact to the inlet contact; and
Includes a third wire connected to the gate contact,
The first source/drain region is:
a first low-concentration impurity region having the first depth and the first width and having a first edge aligned with one edge of the gate electrode; and
provided within the first low-concentration impurity region, having a first depth, a second width less than the first width, disposed at a first distance from the first edge, and having a concentration higher than the first low-concentration impurity region. a first high concentration impurity region having a concentration of the first impurity,
The second source/drain region is:
a second low-concentration impurity region having a second depth deeper than the first depth, a second width wider than the first width, and a second edge partially overlapping the other edge of the gate electrode; and
is provided within the second low-concentration impurity region, has a first depth, has a second width, is disposed at a second distance from the second edge greater than the first distance, and has a concentration less than the second low-concentration impurity region. A monolithic metal-insulator-transition device comprising a second high concentration impurity region having a high concentration of the first impurity.
delete delete delete delete According to claim 1,
A monolithic metal-insulator-transition device wherein the bottom of the inlet contact has a width greater than that of the first contact. According to claim 1,
A monolithic metal-insulator transition device wherein the bottom of the inlet contact has a width greater than that of the gate electrode. delete delete delete delete delete delete delete delete delete delete delete delete delete

Images