CN116344534B

CN116344534B - ESD-resistant groove type power semiconductor device and preparation method thereof

Info

Publication number: CN116344534B
Application number: CN202310618496.8A
Authority: CN
Inventors: 范捷
Original assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Current assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-08-18
Anticipated expiration: 2043-05-30
Also published as: CN116344534A

Abstract

The invention relates to a groove type power semiconductor device capable of resisting ESD and a preparation method thereof. The ESD protection structure comprises an ESD protection groove unit and an ESD protection polysilicon unit, wherein the ESD protection groove unit is filled in the ESD protection groove unit; the ESD protection polycrystalline silicon unit is in metal ohmic contact with a front first electrode for forming a front first electrode of the power semiconductor device and a front second electrode for forming a front second electrode of the power semiconductor device, so that the ESD protection polycrystalline silicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device. The invention can effectively realize ESD protection, is compatible with the process of the trench type power semiconductor device, reduces the complexity and cost of the process, and improves the stability and reliability of the power semiconductor device.

Description

ESD-resistant groove type power semiconductor device and preparation method thereof

Technical Field

The invention relates to a power semiconductor device and a preparation method thereof, in particular to a groove type power semiconductor device capable of resisting ESD and a preparation method thereof.

Background

For integrated circuit products, charge accumulation occurs during manufacturing, testing, packaging, storage, and shipping. When the pins of the product are grounded, the current generated by the discharged charges of the pins reaches ampere level, under the condition of no ESD (Electro-Static discharge) protection structure, the instantaneously generated high voltage can lead to breakdown failure of the device, and meanwhile, a large amount of heat is generated to lead silicon materials and aluminum near the pins to achieve melting point mutual dissolution, so that lattice mismatch and metal connecting wires are broken, and finally, the product failure of an integrated circuit can be caused.

Thus, in the design of integrated circuit products, particularly power semiconductor devices, the design of electrostatic protection is directly related to functional stability. For the existing power semiconductor device, the compatibility of the existing ESD protection and the trench type power semiconductor device is poor, so that the process cost is high, and the ESD protection requirement of the power semiconductor device is difficult to meet.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide an ESD-resistant groove type power semiconductor device and a preparation method thereof, which can effectively realize ESD protection, are compatible with the process of the groove type power semiconductor device, reduce the complexity and cost of the process and improve the stability and reliability of the power semiconductor device.

According to the technical scheme provided by the invention, the groove type power semiconductor device capable of resisting ESD comprises a semiconductor substrate, an active region prepared in the central region of the semiconductor substrate and a terminal protection region surrounding the active region; and an ESD protection structure prepared in the terminal protection region, wherein,

the ESD protection structure comprises an ESD protection groove unit and an ESD protection polysilicon unit, wherein the ESD protection groove unit is positioned in the terminal protection area, and the ESD protection polysilicon unit is used for ESD protection and is filled in the ESD protection groove unit;

the ESD protection polycrystalline silicon unit is in metal ohmic contact with a front first electrode for forming a front first electrode of the power semiconductor device and a front second electrode for forming a front second electrode of the power semiconductor device, so that the ESD protection polycrystalline silicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device.

The ESD protection polysilicon cells comprise at least one first set of polysilicon cells, wherein,

the ESD protection groove unit comprises an ESD protection first groove, and a polysilicon first unit group is filled in the ESD protection first groove;

on the section of the power semiconductor device, the first polysilicon unit group comprises three in-groove N-type first polysilicon bodies and two in-groove P-type first polysilicon bodies which are sequentially arranged, wherein the two in-groove P-type first polysilicon bodies are respectively positioned between the two adjacent in-groove N-type first polysilicon bodies, the in-groove P-type first polysilicon bodies are contacted with the in-groove N-type first polysilicon bodies adjacent to the two sides, and the in-groove N-type first polysilicon bodies and the in-groove P-type first polysilicon bodies are insulated and isolated from the inner wall of the first ESD protection groove;

The front first electrode metal is in ohmic contact with the N-type first polysilicon body in the groove at one end part in the first polysilicon unit group, and the front second electrode metal is in ohmic contact with the N-type first polysilicon body in the groove at the other end part in the first polysilicon unit group.

The ESD protection trench unit comprises an ESD protection second trench and an ESD protection third trench juxtaposed with the ESD protection second trench, wherein,

the ESD protection polysilicon unit comprises a polysilicon second unit group, and the ESD protection second groove and the ESD protection third groove are filled with the polysilicon second unit group;

on the section of the power semiconductor device, the second polysilicon unit group comprises two in-groove N-type second polysilicon bodies and in-groove P-type second polysilicon bodies positioned between the two in-groove N-type second polysilicon bodies, the in-groove P-type second polysilicon bodies are in contact with the in-groove N-type second polysilicon bodies at two sides, and the in-groove N-type second polysilicon bodies and the in-groove P-type second polysilicon bodies are insulated and isolated from the positioned ESD protection second groove and the ESD protection third groove;

the first electrode metal on the front side is in ohmic contact with the second N-type polysilicon body in one groove in the second groove or the third groove, the second N-type polysilicon body in the other groove in the second groove or the third groove is electrically connected with the second N-type polysilicon body in the third groove or the second groove through a connecting metal, and the second N-type polysilicon body in the other groove in the third groove or the second groove is in ohmic contact with the second electrode metal on the front side.

Within the termination protection region, a schottky diode cell for reducing carrier lifetime is also included, wherein,

in the cross section of the power semiconductor device, the schottky diode unit comprises a second conductive type first doping region prepared in a semiconductor substrate first conductive type epitaxial layer, a diode first groove prepared in the second conductive type first doping region and a diode second groove prepared in the second conductive type first doping region;

the second diode groove is positioned under the positive side of the first diode groove, the groove width of the second diode groove is smaller than that of the first diode groove, the second diode groove is filled with a polysilicon body in the diode groove, and the polysilicon body in the diode groove is insulated and isolated from the inner wall of the second diode groove;

the polysilicon body in the diode groove is in Schottky contact with the seed layer in the groove covering the diode first groove, and the seed layer in the groove is electrically connected with the front first electrode metal filled in the diode first groove;

the outer side wall of the diode first groove is in contact with the first conductive type doped region.

A second conductivity type second doped region is provided within the second conductivity type first doped region, wherein,

The doping concentration of the second conductive type second doping region is greater than that of the second conductive type first doping region;

the second conductive type second doping region coats the outer wall of the diode first groove, the diode second groove penetrates through the second conductive type second doping region below the groove bottom of the diode first groove, and the groove bottom of the diode second groove is below the second conductive type second doping region;

the first conductive type doped region is located in the second conductive type second doped region.

The cross section of the power semiconductor device also comprises diode groove outside polysilicon bodies distributed on two sides of the diode first groove opening, wherein,

the outside polysilicon body of the diode is supported on the first conductive type epitaxial layer through the outside polysilicon insulating isolator, and is isolated from the front first electrode metal insulation filled in the first groove of the diode through the outside polysilicon insulating isolator;

the polysilicon body outside the diode trench does not overlap the first conductivity type doped region.

The in-groove seed layer includes a Ti layer and/or a TiN layer.

In the terminal protection area, a plurality of terminal pressure-resistant grooves are also included, wherein,

on the section of the power semiconductor device, a terminal withstand voltage groove is positioned between the ESD protection structure and the active region;

The terminal voltage-resistant groove penetrates through the second conductive type third doping region distributed in the terminal protection region, and the bottom of the terminal voltage-resistant groove and the bottom of the ESD protection groove are both positioned below the second conductive type third doping region;

terminal voltage-resistant conductive polysilicon is filled in the terminal voltage-resistant groove, and is insulated and isolated from the inner wall of the terminal voltage-resistant groove through a voltage-resistant groove insulating oxide layer in the terminal voltage-resistant groove;

the terminal voltage-resistant conductive polysilicon is in ohmic contact with the front first electrode metal.

Within the active region, a plurality of cells are included in parallel, wherein,

the cells adopt a groove structure.

The cells adopt an SGT structure, wherein,

the cell comprises a cell groove which penetrates through the second conductive type base region traversing the active region, and the bottom of the cell groove is positioned below the second conductive type base region;

setting cell first electrode conductive polysilicon and cell second electrode conductive polysilicon in the cell groove, wherein the cell second electrode conductive polysilicon is positioned above the cell first electrode conductive polysilicon;

the conductive polysilicon of the second electrode of the cell is insulated and isolated from the conductive polysilicon of the first electrode of the cell, and the conductive polysilicon of the first electrode of the cell and the conductive polysilicon of the second electrode of the cell are insulated and isolated from the inner wall of the groove of the cell;

The first electrode conductive polysilicon of the cell is in ohmic contact with the first electrode metal of the front surface, the second electrode conductive polysilicon of the cell is in ohmic contact with the second electrode metal of the front surface, the first electrode metal of the front surface is also in ohmic contact with the second conductive type base region and the first conductive type source regions distributed in the second conductive type base region, and the first conductive type source regions are in contact with the outer side walls of the cell grooves.

The preparation method of the ESD-resistant groove type power semiconductor device is used for preparing the power semiconductor device, wherein the preparation method of the power semiconductor device comprises the following steps:

providing a semiconductor substrate, and preparing an ESD protection structure in a terminal protection area of the semiconductor substrate;

when an ESD protection structure is prepared, firstly preparing an ESD protection groove unit in a terminal protection area, and preparing an ESD protection polysilicon unit in the ESD protection groove unit;

and when the metal layer is prepared above the front surface of the semiconductor substrate, ohmic contact is made between front surface first electrode metal for forming a front surface first electrode and front surface second electrode metal for forming a front surface second electrode and the ESD protection polycrystalline silicon unit, so that the ESD protection polycrystalline silicon unit is connected in series between the front surface first electrode and the front surface second electrode of the power semiconductor device.

The preparation method further comprises the step of preparing an active region in the central region of the semiconductor substrate, and when the cell in the active region adopts an SGT structure, the preparation method comprises the following steps:

etching the front surface of the semiconductor substrate to obtain at least a cell trench in the first conductive type epitaxial layer;

oxidizing the front surface of the semiconductor substrate to grow in the cell groove to obtain a first insulating oxide layer, and depositing polysilicon in the cell groove where the first insulating oxide layer grows to form a polysilicon filling column filling the cell groove;

etching the polysilicon filling column in the cell groove to obtain a cell conductive polysilicon column in the cell groove after etching, and simultaneously preparing an ESD protection groove unit in the first conductive type epitaxial layer;

oxidizing the front surface of the semiconductor substrate to obtain cell first electrode conductive polysilicon in a cell groove, a lower insulating oxide layer in the groove for wrapping the cell first electrode conductive polysilicon, an upper insulating oxide layer in the groove for covering the upper side wall of the cell groove and an ESD protection groove insulating oxide layer for covering the inner wall of the ESD protection groove unit;

Polysilicon deposition is carried out on the cell groove and the ESD protection groove unit to obtain cell second electrode conductive polysilicon positioned in the cell groove, and a needed ESD protection polysilicon unit is formed in the ESD protection groove unit based on the process steps of preparing a second conductive type base region and a first conductive type source region in an active region;

depositing a dielectric layer on the front surface of the semiconductor substrate to obtain an insulating dielectric layer covering the front surface of the semiconductor substrate, wherein the insulating dielectric layer covers the ESD protection groove unit and the notch of the cellular groove;

etching the contact hole on the insulating dielectric layer, and depositing metal on the insulating dielectric layer to form at least a front first electrode metal for forming a front first electrode and a front second electrode metal for forming a front second electrode,

the front first electrode metal is in ohmic contact with the cell first electrode conductive polysilicon and the ESD protection polysilicon unit, and the front second electrode metal is in ohmic contact with the cell second electrode conductive polysilicon and the ESD protection polysilicon unit.

When the ESD protection trench unit comprises an ESD protection first trench, the method for preparing and forming the ESD protection polysilicon unit comprises the following steps:

Forming an in-ESD-trench polysilicon body in the ESD protection first trench based on polysilicon deposition;

preparing a second conductive type impurity ion implantation of a second conductive type base region into the polysilicon body in the ESD groove when preparing and forming the second conductive type base region;

and selectively injecting first conductivity type impurity ions into the polysilicon body in the ESD groove to form a first polysilicon unit group in the first polysilicon unit group, wherein in the first polysilicon unit group, an in-groove N type first polysilicon body-in-groove P type first polysilicon body-in-groove N type first polysilicon body arrangement is formed.

When the ESD protection groove unit comprises an ESD protection second groove and an ESD protection third groove, the method for preparing and forming the ESD protection polysilicon unit comprises the following steps:

on the section of the power semiconductor device, when polysilicon is deposited, conducting polysilicon of a second electrode of a cell is obtained in a cell groove, and simultaneously, N-type second polysilicon bodies in two grooves are prepared in an ESD protection second groove and an ESD protection third groove;

filling the second groove and the third groove with the P-type second polysilicon bodies in the groove, wherein the P-type second polysilicon bodies in the groove are contacted with the N-type second polysilicon bodies in the grooves at two sides so as to form a second polysilicon unit group based on the P-type second polysilicon bodies in the groove and the N-type second polysilicon bodies in the grooves distributed at two sides of the P-type second polysilicon bodies in the groove;

Performing second conductivity type impurity ion implantation on the front surface of the semiconductor substrate to form a second conductivity type base region in the active region;

implanting first conductivity type impurity ions into the front surface of the semiconductor substrate to form a first conductivity type source region in the active region, wherein the first conductivity type impurity ions are also implanted into N-type second polysilicon bodies in grooves of the ESD protection second groove and the ESD protection third groove;

and when the metal is deposited, connecting metal is further included on the insulating medium layer, and the connecting metal is in ohmic contact with the N-type second polysilicon body in one groove in the second groove of the ESD protection and the corresponding N-type second polysilicon body in the corresponding groove in the third groove of the ESD protection.

The bottoms of the ESD protection second groove and the ESD protection third groove are positioned below the second conductive type base region;

the groove width of the ESD protection second groove is consistent with the groove width of the ESD protection third groove, and the groove width of the ESD protection second groove and the groove width of the ESD protection third groove are 2-2.5 times of the groove width of the element groove.

And the method also comprises a terminal pressure-resistant groove formed in the terminal protection area during groove etching, wherein,

when a first insulating oxide layer is grown in the cell groove, a pressure-resistant groove insulating oxide layer is simultaneously generated in the terminal pressure-resistant groove;

When a polysilicon filling column is formed in a cell groove, terminal voltage-resistant conductive polysilicon is formed in a terminal voltage-resistant groove at the same time, and the terminal voltage-resistant conductive polysilicon is insulated and isolated from the inner wall of the terminal voltage-resistant groove through a voltage-resistant groove insulating oxide layer in the terminal voltage-resistant groove;

In the "first conductivity type" and "second conductivity type", for an N-type power semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power semiconductor device, the first conductivity type and the second conductivity type refer to the type that is the opposite of an N-type power semiconductor device.

The invention has the advantages that: the ESD protection structure is prepared in the terminal protection area, the ESD protection groove unit and the ESD protection polysilicon unit in the ESD protection structure can be compatible with the process of the groove type cell, the complexity and the cost of the process are reduced, and after the ESD protection polysilicon unit is connected between the front first electrode and the front second electrode in series, the ESD protection can be realized, and the stability and the reliability of the power semiconductor device are improved.

Drawings

Fig. 1-6 are cross-sectional views illustrating steps of a first embodiment of an ESD protection structure according to the present invention, where,

FIG. 1 is a cross-sectional view of a cell trench and a termination trench according to the present invention.

Fig. 2 is a cross-sectional view of the present invention after a second insulating oxide layer is formed.

Fig. 3 is a cross-sectional view of the present invention after preparing an N-type second polysilicon body in a trench.

Fig. 4 is a cross-sectional view of a second polysilicon body of the in-tank P-type for forming a second set of polysilicon cells in accordance with the present invention.

Fig. 5 is a cross-sectional view of the P-type base region and the n+ source region of the present invention.

Fig. 6 is a cross-sectional view of the present invention after metal deposition.

Fig. 7 is a schematic diagram of a second embodiment of the ESD protection structure of the invention.

Fig. 8 is a schematic diagram of the present invention for simultaneously forming schottky diode cells.

Reference numerals illustrate: the semiconductor device comprises a 1-N type epitaxial layer, a 2-cell trench, a 3-terminal voltage-withstand trench, a 4-ESD protection second trench, a 5-ESD protection third trench, a 6-cell first electrode conductive polysilicon, a 7-voltage-withstand trench insulating oxide layer, an 8-cell trench upper window, a 9-terminal voltage-withstand conductive polysilicon, a 10-cell second insulating oxide layer, a 11-cell second electrode conductive polysilicon, a 12-first in-trench N type second polysilicon body, a 13-in-trench P type second polysilicon body fill region, a 14-second in-trench N type second polysilicon body, a 15-in-trench P type second polysilicon body, a 16-P type base region, a 17-N+ source region, a 18-insulating dielectric layer, a 19-front side second electrode metal, a 20-front side first electrode metal, a 21-connection metal, a 22-ESD protection first trench, a 23-in-trench N type first polysilicon body, a 24-trench P type first polysilicon body, a 25-N+ substrate, a 26-trench outer silicon insulator, a 27-trench P type second polysilicon body fill region, a 15-trench P type second polysilicon body, a 16-P type base region, a 17-N+ source region, a 18-insulating dielectric layer, a 19-front side second electrode metal, a 20-front side first electrode metal, a 21-connection metal, a 22-ESD protection first trench, a 23-in-trench N type first polysilicon body, a 24-trench P type first polysilicon body, a 25-N+ substrate, a doped diode insulation layer, a 28-N+ substrate, a second silicon body, a 28-type P+ doped diode insulation layer, a drain region, a diode region P, a 35-type P, a diode region P, and a diode region P-type P, and a 35-type diode region P.

Detailed Description

The invention will be further described with reference to the following specific drawings and examples.

In order to effectively realize ESD protection, the method is compatible with a trench type power semiconductor device process, reduces the complexity and cost of the process, and takes a first conductivity type as an N type as an example for the trench type power semiconductor device capable of resisting ESD, in one embodiment of the invention, the method comprises a semiconductor substrate, an active region prepared in a central region of the semiconductor substrate and a terminal protection region surrounding the active region; and an ESD protection structure prepared in the terminal protection region, wherein,

the ESD protection polycrystalline silicon unit is in ohmic contact with front first electrode metal 20 used for forming a front first electrode of the power semiconductor device and front second electrode metal 19 used for forming a front second electrode of the power semiconductor device, so that the ESD protection polycrystalline silicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device.

Specifically, the semiconductor substrate may be in the form of a material commonly used in the prior art, for example, a silicon substrate, a SiC substrate, or the like, and may be specifically selected as required. Generally, the semiconductor substrate includes an n+ substrate 25 and an N-type epitaxial layer 1 on the n+ substrate 25, the N-type epitaxial layer 1 has a lower doping concentration than the n+ substrate 25, and the N-type epitaxial layer 1 has a thickness greater than that of the n+ substrate 25. The front surface of the semiconductor substrate is formed by the surface of the N-type epitaxial layer 1, and the back surface of the semiconductor substrate is formed by the surface corresponding to the front surface of the n+ substrate 25, and the front and back surfaces of the semiconductor substrate are the same as those in the conventional case.

For a power semiconductor device, the power semiconductor device generally comprises an active area and a terminal protection area, wherein the active area is positioned in a central area of the power semiconductor device, the terminal protection area surrounds the active area, and the specific function functions of the active area and the terminal protection area are consistent with the prior art.

In order to realize ESD protection of the power semiconductor device, in one embodiment of the present invention, an ESD protection structure is prepared in the termination protection region, specifically, the ESD protection structure includes an ESD protection trench and an ESD protection polysilicon unit, where the ESD protection polysilicon unit is filled in the ESD protection trench, and of course, the ESD protection polysilicon unit needs to be insulated from the ESD protection trench where it is located.

For a trench-type power semiconductor device, the front electrode generally includes a front first electrode and a front second electrode, where when the power semiconductor device is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type device, the front first electrode is generally a source and the front second electrode is a gate; when the power semiconductor device is a IGBT (Insulated Gate Bipolar Transistor) type device, the front first electrode is typically an emitter and the front second electrode is a gate.

In specific implementation, the front first electrode metal 20 for forming the front first electrode and the front second electrode metal 19 for forming the front second electrode are connected with the ESD protection polysilicon unit in an adapting manner, so that the ESD protection polysilicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device, and at this time, the ESD protection of the power semiconductor device can be realized by using the ESD protection polysilicon unit.

In specific implementation, the ESD protection structure may take different implementation forms, and specific description will be given below for the ESD protection structure corresponding to different embodiments.

In one embodiment of the invention, the ESD protection polysilicon cells comprise at least one first group of polysilicon cells, wherein,

The ESD protection groove unit comprises an ESD protection first groove 22, and a polysilicon first unit group is filled in the ESD protection first groove 22;

on the cross section of the power semiconductor device, the first polysilicon unit group includes three N-type first polysilicon bodies 23 in the groove and two P-type first polysilicon bodies 24 in the groove, the two P-type first polysilicon bodies 24 in the groove are respectively located between the two adjacent N-type first polysilicon bodies 23 in the groove, the P-type first polysilicon bodies 24 in the groove are contacted with the N-type first polysilicon bodies 23 in the groove adjacent to the two sides, and the N-type first polysilicon bodies 23 in the groove and the P-type first polysilicon bodies 24 in the groove are insulated and isolated from the inner wall of the first ESD protection groove 22;

the front first electrode metal 20 is in ohmic contact with the N-type first polysilicon body 23 in the groove at one end portion in the polysilicon first cell group, and the front second electrode metal 19 is in ohmic contact with the N-type first polysilicon body 23 in the groove at the other end portion in the polysilicon first cell group.

An embodiment in which the ESD protection polysilicon unit comprises at least one first set of polysilicon is shown in fig. 7, and the case in which the ESD protection trench unit comprises only one first ESD protection trench 22 is also shown, where the first set of polysilicon is filled in the first ESD protection trench 22, and the first ESD protection trench 22 is located in the N-type epitaxial layer 1, and extends vertically downward from the front surface of the semiconductor substrate into the N-type epitaxial layer 1.

Fig. 7 shows a schematic view of the ESD protection first trench 22 and the polysilicon first cell group on the power semiconductor device section, at this time, for the polysilicon first cell group, an in-groove N-type first polysilicon body 23-in-groove P-type first polysilicon body 24-in-groove N-type first polysilicon body 23 are formed, so as to achieve the purpose of ESD protection by using the arrangement form. In particular, an insulating oxide layer is required to be disposed on the inner wall of the ESD protection first trench 22, and insulation and isolation between the polysilicon first cell group and the inner wall of the ESD protection first trench 22 can be achieved by using the insulating oxide layer.

In fig. 7, the front side second electrode metal 19 is in ohmic contact with the leftmost in-groove N-type first polysilicon body 23, and the front side first electrode metal 20 is in ohmic contact with the rightmost in-groove N-type first polysilicon body 23. Of course, the positions of the N-type first polysilicon bodies 23 in the grooves in which the front first electrode metal 20 and the front second electrode metal 19 are in ohmic contact can also be selected according to the exchange, and the specific ohmic contact state can be selected according to the needs, so as to meet the requirement that the polysilicon first unit group is connected in series between the front first electrode and the front second electrode.

In one embodiment of the present invention, the ESD protection trench unit includes an ESD protection second trench 4 and an ESD protection third trench 5 juxtaposed with the ESD protection second trench 4, wherein,

the ESD protection polysilicon unit comprises a polysilicon second unit group, and the ESD protection second groove 4 and the ESD protection third groove 5 are filled with the polysilicon second unit group;

on the section of the power semiconductor device, the second polysilicon unit group comprises two in-groove N-type second polysilicon bodies and an in-groove P-type second polysilicon body 15 positioned between the two in-groove N-type second polysilicon bodies, the in-groove P-type second polysilicon body 15 is in contact with the in-groove N-type second polysilicon bodies at two sides, and the in-groove N-type second polysilicon body and the in-groove P-type second polysilicon body 15 are insulated and isolated from the positioned ESD protection second groove 4 and the ESD protection third groove 5;

the front first electrode metal 20 is in ohmic contact with the N-type second polysilicon body in one of the ESD protection second trench 4 or the ESD protection third trench 5, the N-type second polysilicon body in the other of the ESD protection second trench 4 or the ESD protection third trench 5 is electrically connected with the N-type second polysilicon body in one of the ESD protection third trench 5 or the ESD protection second trench 4 through a connection metal 21, and the N-type second polysilicon body in the other of the ESD protection third trench 5 or the ESD protection second trench 4 is in ohmic contact with the front second electrode metal 19.

Fig. 6 shows an embodiment in which the ESD protection trench unit includes both the ESD protection second trench 4 and the ESD protection third trench 5, and in this case, the ESD protection polysilicon unit includes two polysilicon second cell groups, and in general, the ESD protection second trench 4 and the ESD protection third trench 5 are generally formed based on the same process step, the respective widths of the ESD protection second trench 4 and the ESD protection third trench 5 are smaller than the respective widths of the ESD protection first trench 22, and the ESD protection second trench 4, the ESD protection third trench 5, and the ESD protection first trench 22 generally have the same trench depth.

In the cross section of the power semiconductor device shown in fig. 6, a second polysilicon unit group includes two in-groove N-type second polysilicon bodies and one in-groove P-type second polysilicon body 15, where the two in-groove N-type second polysilicon bodies may specifically be a first in-groove N-type second polysilicon body 12 and a second in-groove N-type second polysilicon body 14, and the first in-groove N-type second polysilicon body 12 and the second in-groove N-type second polysilicon body 14 may be independent forms, or the first in-groove N-type second polysilicon body 12 and the second in-groove N-type second polysilicon body 14 may be connected to each other to form an integral form, which may be specifically selected according to practical needs. The two polysilicon second cell groups are generally in the same distribution form in the ESD protection second trench 4 and the ESD protection third trench 5, but the polysilicon second cell groups are insulated and isolated from the inner walls of the ESD protection second trench 4 and the ESD protection third trench where they are located, and the insulation and isolation forms can be as described above, and insulation oxide layers are prepared in the ESD protection second trench 4 and the ESD protection third trench 5.

In order to meet the requirement that when the ESD protection polysilicon unit is connected in series between the front first electrode and the front second electrode, the front first electrode metal 20 is in ohmic contact with the N-type second polysilicon body in one of the ESD protection second trench 4 and the ESD protection third trench 5, the front second electrode metal 19 is in ohmic contact with the N-type second polysilicon body in the corresponding one of the ESD protection third trench 5 and the ESD protection second trench 4, and the remaining N-type second polysilicon body in the trench between the ESD protection second trench 4 and the ESD protection third trench 5 is connected by using the connecting metal 21.

In fig. 6, the front second electrode metal 19 is in ohmic contact with the N-type second polysilicon body 12 in the first trench in the ESD protection second trench 4, the front first electrode metal 20 is in ohmic contact with the N-type second polysilicon body 14 in the second trench in the ESD protection third trench 5, and the connection metal 21 is in ohmic contact with the N-type second polysilicon body 14 in the second trench in the ESD protection second trench 4 and the N-type second polysilicon body 12 in the first trench in the ESD protection third trench 5, respectively.

In one embodiment of the present invention, a schottky diode cell for reducing carrier lifetime is further included in the termination protection region, wherein,

in the cross section of the power semiconductor device, the schottky diode unit includes a P-type first doped region 30 formed in the N-type epitaxial layer 1 of the semiconductor substrate, a diode first trench 32 formed in the P-type first doped region 30, and a diode second trench 35 formed in the P-type first doped region 30;

The diode second groove 35 is positioned under the diode first groove 32, the groove width of the diode second groove 35 is smaller than that of the diode first groove 32, the diode second groove 35 is filled with a polysilicon body 34 in the diode groove, and the polysilicon body 34 in the diode groove is insulated and isolated from the inner wall of the diode second groove 35;

the polysilicon body 34 in the diode groove is in schottky contact with the seed layer 31 in the groove covering the diode first groove 32, and the seed layer 31 in the groove is electrically connected with the front surface first electrode metal 20 filled in the diode first groove 32;

the outer sidewalls of the diode first trench 32 are in contact with the N + doped region 28.

An embodiment of the simultaneous preparation of a schottky diode cell in the termination protection region is shown in fig. 8. In fig. 8, the schottky diode cell is located outside the ESD protection structure, i.e. on the side of the ESD protection structure remote from the active region, with reduced carrier lifetime.

In fig. 8, a P-type first doped region 30 is prepared in an N-type epitaxial layer 1 of a termination protection region, and meanwhile, a diode first trench 32 and a diode second trench 35 are prepared in the P-type first doped region 30, wherein the notch of the diode first trench 32 generally corresponds to the front surface of a semiconductor substrate, and the notch of the diode second trench 35 corresponds to the bottom of the diode first trench 32. The width of the first diode trench 32 is larger than that of the second diode trench 35, and the second diode trench 35 and the first diode trench 32 are generally coaxially distributed.

A second trench insulating oxide layer 36 is disposed on the inner wall of the second trench 35, the second trench insulating oxide layer 36 is typically a silicon dioxide layer, and the polysilicon body 34 in the trench is insulated from the inner wall of the second trench 35 by the second trench insulating oxide layer 36.

Generally, after the diode trench polysilicon body 34 is filled in the diode second trench 35, an in-trench seed layer 31 is disposed on the inner wall of the diode first trench 32, the in-trench seed layer 31 includes a Ti layer and/or a TiN layer, and a schottky contact is formed between the in-trench seed layer 31 and the diode trench polysilicon body 34, at this time, the schottky diode 33 is formed.

During metal deposition, the front first electrode metal 20 generally fills the diode first trench 32, and the front first electrode metal 20 is electrically connected to the in-trench seed layer 31. In fig. 8, n+ doped regions 28 are also formed in the P-type first doped region 30, the n+ doped regions 28 are distributed on both sides of the diode first trench 32, and the n+ doped regions 28 are in contact with the outer wall of the diode first trench 32.

In one embodiment of the present invention, a P-type second doped region 29 is disposed within a P-type first doped region 30, wherein,

the doping concentration of the P-type second doping region 29 is greater than the doping concentration of the P-type first doping region 30;

The outer wall of the diode first groove 32 is covered by the P-type second doping region 29, the diode second groove 35 penetrates through the P-type second doping region 29 below the groove bottom of the diode first groove 32, and the groove bottom of the diode second groove 35 is below the P-type second doping region 29;

the n+ doped region 28 is located within the P-type second doped region 29.

In fig. 8, the range of the P-type second doped region 29 is smaller than that of the P-type first doped region 30, and the P-type second doped region 29 is used to wrap the outer wall of the diode first trench 32, i.e. the shape of the P-type second doped region 29 is generally consistent with that of the diode first trench 32, and the n+ doped region 28 is located in the P-type second doped region 29. The depth of the diode second trench 35 is greater than the thickness of the P-type second doped region 29 below the bottom of the diode first trench 32, and at this time, the diode second trench 35 penetrates through the P-type second doped region 29, and the bottom of the diode second trench 35 is located below the P-type second doped region 29.

In one embodiment of the present invention, in the cross section of the power semiconductor device, the polysilicon body 27 outside the diode trench is further included and distributed on both sides of the notch of the diode first trench 32, wherein,

the diode outside-slot polysilicon body 27 is supported on the N-type epitaxial layer 1 through the outside-slot polysilicon insulating spacer 26, and is insulated from the front first electrode metal 20 filled in the diode first groove 32 through the outside-slot polysilicon insulating spacer 26;

The polysilicon body 27 outside the diode trench does not overlap with the N + doped region 28.

In fig. 8, the outside polysilicon bodies 27 are further disposed on two sides outside the notch of the diode first trench 32, the outside polysilicon bodies 27 are located above the N-type epitaxial layer 1, the outside polysilicon insulating spacers 26 are typically silicon dioxide layers, and the outside polysilicon bodies 27 are covered by the outside polysilicon insulating spacers 26, so that insulating isolation between the N-type epitaxial layer 1 and the front first electrode metal 20 can be simultaneously realized.

In the power semiconductor cross section, the polysilicon body 27 outside the diode slot is in a strip shape, the first end of the polysilicon body 27 outside the diode slot is adjacent to the first diode slot 32, but the first end of the polysilicon body 27 outside the diode slot is not overlapped with the n+ doped region 28, specifically, when the polysilicon body 27 outside the diode slot projects towards the n+ doped region 28, the first end of the polysilicon body 27 outside the diode slot is not overlapped with the n+ doped region 28, and the second end of the polysilicon body 27 outside the P-type first doped region 30.

The n+ doped region 28 is electrically connected to the front side first electrode metal 20 through an in-groove seed layer 31, which enables normal extraction of the power device, such as source extraction for MOSFET type devices, and emitter extraction for IGBT type devices. The use of N + doped regions 28 may further enhance the anti-ESD effect.

As can be seen from fig. 8 and the above description, the P-type first doped region 30 forms a PN junction with the N-type epitaxial layer 1, and the schottky diode 33 and the PN junction together form a body diode, and when the body diode is turned on, a part of current flows through the schottky diode 33 in the form of majority carriers, so that minority carriers injected into the N-type epitaxial layer 1 when the power semiconductor is turned on and stored excess charges can be reduced, and the body diode can be recovered more quickly when turned off.

In one embodiment of the invention, in the termination protection region, further termination voltage withstand trenches 3 are included, wherein,

on the cross section of the power semiconductor device, a terminal withstand voltage trench 3 is positioned between the ESD protection structure and the active region;

the terminal voltage-resistant groove 3 penetrates through the P-type third doping region 38 distributed in the terminal protection region, and the bottom of the terminal voltage-resistant groove 3 and the bottom of the ESD protection groove are both positioned below the P-type third doping region 38;

terminal pressure-resistant conductive polysilicon 9 is filled in the terminal pressure-resistant groove 3, and the terminal pressure-resistant conductive polysilicon 9 is insulated and isolated from the inner wall of the terminal pressure-resistant groove 3 through a pressure-resistant groove insulating oxide layer 7 in the terminal pressure-resistant groove 3;

The termination voltage-resistant conductive polysilicon 9 is in ohmic contact with the front first electrode metal 20.

Fig. 6 and fig. 7 each show an embodiment in which terminal dielectric breakdown voltage trenches 3 are also provided in the terminal protection area, and one terminal dielectric breakdown voltage trench 3 is shown in fig. 6 and fig. 7, and of course, the number of terminal dielectric breakdown voltage trenches 3 may be selected according to actual needs, so as to meet actual application requirements. The terminal voltage-resistant trench 3 is located in the N-type epitaxial layer 1, in the figure, the terminal voltage-resistant trench 3 penetrates through the P-type third doped region 38 of the terminal protection region, and the P-type third doped region 38 is generally formed by the same process step as the P-type base region 16 in the active region.

The terminal voltage-resistant conductive polysilicon 9 is insulated and isolated from the terminal voltage-resistant groove 3 where the terminal voltage-resistant conductive polysilicon 9 is located through the voltage-resistant groove insulating oxide layer 7, the terminal voltage-resistant conductive polysilicon 9 is in ohmic contact with the front first electrode metal 20, and the voltage resistance of the terminal protection area in reverse cut-off can be improved by utilizing the terminal voltage-resistant groove 3.

In one embodiment of the invention, a plurality of cells distributed in parallel are included in the active region, wherein the cells adopt a trench structure.

In order to be compatible with the ESD protection structure process, the cell preferably adopts a trench structure, and when the cell adopts the trench structure, the cell may be specifically in the form of a common trench gate or in the form of an SGT, and the case of adopting the SGT is specifically exemplified below.

In one embodiment of the invention, the cells employ an SGT structure, wherein,

the cell comprises a cell groove 2, wherein the cell groove 2 penetrates through a P-type base region 16 traversing the active region, and the bottom of the cell groove 2 is positioned below the P-type base region 16;

a first electrode conductive polysilicon 6 and a second electrode conductive polysilicon 11 are arranged in the cell groove 2, and the second electrode conductive polysilicon 11 is positioned above the first electrode conductive polysilicon 6;

the cell second electrode conductive polysilicon 11 is insulated and isolated from the cell first electrode conductive polysilicon 6, and the cell first electrode conductive polysilicon 6 and the cell second electrode conductive polysilicon 11 are insulated and isolated from the inner wall of the cell groove 2;

the first electrode conductive polysilicon 6 of the cell is in ohmic contact with the first electrode metal 20 of the front side, the second electrode conductive polysilicon 11 of the cell is in ohmic contact with the second electrode metal 19 of the front side, the first electrode metal 20 of the front side is also in ohmic contact with the P-type base region 16 and the N+ source region 17 distributed in the P-type base region 16, and the N+ source region 17 is in ohmic contact with the outer side wall of the cell groove 2.

In fig. 6 and 7, it is shown that one cell in the active region takes the form of an SGT structure, and the case of other cells in the active region can be referred to as illustration and description. In the figure, the cell includes a cell trench 2, and the cell trench 2 and the terminal voltage-resistant trench 3 can be generally manufactured by the same trench etching process, so that the cell trench 2 and the terminal voltage-resistant trench 3 generally have the same trench depth. In order to satisfy the normal operation of the active region, P-type base region 16 is typically disposed within the active region, and n+ source region 17, P-type base region 16 is typically formed across the active region, as will be appreciated from the foregoing description, in the fabrication of P-type base region 16, P-type third doped region 38 is typically formed within the termination protection region. The N + source regions 17 are typically distributed in sidewall contact over the respective outer sides of the cell trenches 2.

An SGT structure with an up-down structure is shown in fig. 6 and 7, and includes a first electrode conductive polysilicon 6 and a second electrode conductive polysilicon 11, where the first electrode conductive polysilicon 6 is located at the lower part of the cell trench 2, and the second electrode conductive polysilicon 11 is located at the upper part of the cell trench 2, and the structure is consistent with the prior art. In fig. 6 and 7, the top of the outer sidewall of the termination trench 3 is contacted with an n+ doped region 37, and the n+ doped region 37 is generally formed by the same process step as the n+ source region 17.

The trench type power semiconductor device can be prepared and formed through the following process steps, and specifically, the preparation method of the power semiconductor device comprises the following steps:

when a metal layer is prepared above the front surface of the semiconductor substrate, front surface first electrode metal 20 for forming a front surface first electrode, front surface second electrode metal 19 for forming a front surface second electrode are in ohmic contact with an ESD protection polysilicon unit, so that the ESD protection polysilicon unit is connected in series between the front surface first electrode and the front surface second electrode of the power semiconductor device.

Preparing an ESD protection structure, specifically, preparing an ESD protection groove unit firstly and then preparing an ESD protection polysilicon unit; in preparing the front electrode of the power semiconductor device, the front first electrode metal 20 for forming the front first electrode, the front second electrode metal 19 for forming the front second electrode are in ohmic contact with the ESD protection polysilicon unit, so that the ESD protection polysilicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device.

In order to be compatible with the preparation process of the trench type cell, in one embodiment of the present invention, the method further comprises the step of preparing an active region in a central region of the semiconductor substrate, wherein when the cell in the active region adopts an SGT structure, the preparation method comprises:

carrying out groove etching on the front surface of the semiconductor substrate to at least obtain a cell groove 2 in the N-type epitaxial layer 1;

oxidizing the front surface of the semiconductor substrate to grow a first insulating oxide layer in the cell groove 2, and depositing polysilicon in the cell groove 2 where the first insulating oxide layer grows to form a polysilicon filling column filling the cell groove 2;

etching the polysilicon filling column in the cell groove 2 to obtain a cell conductive polysilicon column in the cell groove 2 after etching, and simultaneously preparing an ESD protection groove unit in the N-type epitaxial layer;

Oxidizing the front surface of the semiconductor substrate to obtain cell first electrode conductive polysilicon 6 in a cell groove 2, a lower insulating oxide layer 39 in the groove for wrapping the cell first electrode conductive polysilicon 6, an upper insulating oxide layer in the groove for covering the upper side wall of the cell groove 2 and an ESD protection groove insulating oxide layer for covering the inner wall of the ESD protection groove unit;

polysilicon deposition is carried out on the cell groove 2 and the ESD protection groove unit to obtain cell second electrode conductive polysilicon 11 positioned in the cell groove, and the required ESD protection polysilicon unit is formed in the ESD protection groove unit based on the process steps of preparing a P-type base region 16 and an N+ source region 17 in an active region;

depositing a dielectric layer on the front surface of the semiconductor substrate to obtain an insulating dielectric layer 18 covering the front surface of the semiconductor substrate, wherein the insulating dielectric layer 18 covers the ESD protection groove units and the notches of the cell grooves 2;

etching the contact hole on the insulating dielectric layer 18, and depositing metal on the insulating dielectric layer 18 with the contact hole formed, so as to form at least a front first electrode metal 20 for forming a front first electrode and a front second electrode metal 19 for forming a front second electrode, wherein,

The front first electrode metal 20 is in ohmic contact with the cell first electrode conductive polysilicon 6 and the ESD protection polysilicon unit, and the front second electrode metal 19 is in ohmic contact with the cell second electrode conductive polysilicon 11 and the ESD protection polysilicon unit.

When the cell adopts the trench structure, trench etching needs to be performed on the front surface of the semiconductor substrate to prepare at least the cell trenches 2, the number, distribution and trench etching process steps of the cell trenches 2 can be selected according to actual needs, as shown in fig. 1, and in fig. 1, the terminal voltage-resistant trench 3 is also prepared and formed during trench etching.

After etching to obtain the cell groove 2, performing thermal oxidation on the front surface of the semiconductor substrate to form a first insulating oxide layer after thermal oxidation, wherein the first insulating oxide layer is distributed on the surface of the N-type epitaxial layer 1 and covers the cell groove 2 and the corresponding inner wall of the terminal voltage-resistant groove 3. The first insulating oxide layer is a silicon dioxide layer.

After the first insulating oxide layer is formed, polysilicon deposition is performed, at this time, polysilicon filling columns are formed in the cell trenches 2, and terminal voltage-resistant conductive polysilicon 9 is simultaneously formed in the terminal voltage-resistant trenches 3. After the polysilicon is deposited, the first insulating oxide layer on the surface of the N-type epitaxial layer 1 is completely removed by utilizing a CMP process, photoresist is used as a blocking layer of the terminal voltage-resistant conductive polysilicon 9 and the like, and polysilicon photoetching and polysilicon etching are carried out, so that after etching, a cell conductive polysilicon column positioned in the cell groove 2 is obtained, and the terminal voltage-resistant conductive polysilicon 9 cannot be etched due to shielding.

In addition, the region where the ESD protection trench unit needs to be formed is not blocked by photoresist, so when the polysilicon is etched, the ESD protection trench unit is formed in the terminal protection region at the same time, the depth of the ESD protection trench unit is consistent with the depth of the polysilicon etched, the situation of the ESD protection trench unit can be referred to the above description, and the process will be specifically described for different implementation situations of the ESD protection trench unit.

After etching to form the ESD protection trench unit, processing by adopting a technical means commonly used in the technical field and performing an oxidation process again to form a second insulating oxide layer 10, oxidizing the cell conductive polysilicon pillars when forming the second insulating oxide layer, forming a cell first electrode conductive polysilicon 6 based on the oxidized cell conductive polysilicon pillars, and simultaneously forming an intra-trench upper insulating oxide layer by using the remaining first insulating oxide layer in the cell trench 2 in cooperation with the intra-trench lower insulating oxide layer 39 wrapping the cell first electrode conductive polysilicon 6, and forming an intra-trench upper insulating oxide layer by using the second insulating oxide layer 10 covering the upper inner wall of the cell trench 2. The second insulating oxide layer 10 generally covers the surface of the N-type epitaxial layer 1, and at the same time, the ESD protection trench insulating oxide layer is formed by using the second insulating oxide layer 10 covering the inner wall of the ESD protection trench cell, as shown in fig. 2. In fig. 2, a cell trench upper window 8 is formed at the upper portion of the cell trench 2, and deposition of the cell second electrode conductive polysilicon 11 is facilitated by using the cell trench upper window 8.

Polysilicon deposition is required again after the above process steps,

polysilicon deposition is performed on the cell trench 2 and the ESD protection trench unit to obtain a cell second electrode conductive polysilicon 11 located in the cell trench, and the process steps for preparing the P-type base region 16 and the n+ source region 17 in the active region are based to form a required ESD protection polysilicon unit in the ESD protection trench unit. Generally, polysilicon deposition is first performed, and then P-type base region 16 and n+ source region 17 are prepared, as described in detail below with respect to various embodiments of the process for ESD protection trench cells.

In one embodiment of the present invention, when the ESD protection trench unit includes the ESD protection first trench 22, the method for preparing the ESD protection polysilicon unit includes:

forming an in-ESD trench polysilicon body within the ESD protection first trench 22 based on the polysilicon deposition;

when the P-type base region 16 is formed, P-type impurity ions of the P-type base region 16 are prepared and injected into polysilicon bodies in the ESD grooves;

in the preparation of the n+ source region 17, N-type impurity ions are selectively injected into the polysilicon body in the ESD trench to form a first polysilicon cell group, wherein in the first polysilicon cell group, an in-trench N-type first polysilicon body 23-an in-trench P-type first polysilicon body 24-an in-trench N-type first polysilicon body 23 arrangement is formed.

When the ESD protection trench unit only includes the ESD protection first trench 22, the polysilicon body in the ESD protection first trench 22 is formed by simultaneous deposition in the ESD protection first trench 22, and the polysilicon body in the ESD protection first trench 22 is filled with the polysilicon body in the ESD protection first trench 22, so that the width of the ESD protection first trench 22 is enough to satisfy the polysilicon body in the ESD protection required by deposition.

In the preparation of the P-type base region 16, P-type impurity ions may be implanted into the front surface of the semiconductor substrate, after which the P-type base region 16 may be formed in the active region, and at the same time, a P-type third doped region 38 may be formed in the termination protection region, and at this time, the doping type of the ESD trench polysilicon body changes to P-type.

In the case of n+ source region 17, a selective alignment implantation is generally required by using a photolithography mask, so that N-type impurity ions may be selectively implanted into the ESD trench polysilicon body by means of the alignment implantation of n+ source region 17, the process conditions for N-type impurity ion implantation may be selected as required to ensure the formation of n+ source region 17, and the doping type may be adjusted to N-type in the designated region of the ESD trench polysilicon body to form the first polysilicon cell group.

Therefore, when the first unit group of the polysilicon is formed by utilizing the polysilicon in the ESD groove, the first unit group of the polysilicon is compatible with the preparation process of the traditional groove type power semiconductor device, and the cost is not increased. In addition, as is apparent from the above description, since the inner wall of the ESD protection first trench 22 is covered with the ESD protection trench insulation oxide layer, the formed polysilicon first cell group is insulated from the inner wall of the ESD protection first trench 22 by the ESD protection trench insulation oxide layer.

Thereafter, the insulating dielectric layer 18 may be prepared by using a conventional technical means in the art, and metal deposition may be performed on the insulating dielectric layer 18 to prepare the front first electrode metal 20 and the front second electrode metal 19, and specific connection and matching conditions of the front first electrode metal 20 and the front second electrode metal 19 may be referred to the above description, which is not repeated herein.

In another embodiment of the present invention, when the ESD protection trench unit includes the ESD protection second trench 4 and the ESD protection third trench 5, the method for preparing the ESD protection polysilicon unit includes:

on the section of the power semiconductor device, when polysilicon is deposited, cell second electrode conductive polysilicon 11 is obtained in a cell groove, and simultaneously, two N-type second polysilicon bodies in grooves are prepared in an ESD protection second groove 4 and an ESD protection third groove 5;

filling the second ESD protection trench 4 and the third ESD protection trench 5 with an in-trench P-type second polysilicon body 15, wherein the in-trench P-type second polysilicon body 15 is in contact with the N-type second polysilicon bodies in the trenches at both sides so as to form a polysilicon second cell group based on the in-trench P-type second polysilicon body 15 and the N-type second polysilicon bodies in the trenches distributed at both sides of the in-trench P-type second polysilicon body 15;

Performing P-type impurity ion implantation on the front surface of the semiconductor substrate to form a P-type base region 16 in the active region;

n-type impurity ions are implanted in the front surface of the semiconductor substrate to form an n+ source region 17 in the active region, and the N-type impurity ions are also implanted into N-type second polysilicon bodies in the grooves in the second groove 4 and the third groove 5 for ESD protection;

during metal deposition, a connection metal 21 is further included on the insulating dielectric layer 18, and the connection metal 21 is in ohmic contact with an N-type second polysilicon body in a groove in the ESD protection second trench 4 and a corresponding N-type second polysilicon body in a groove in the ESD protection third trench 5.

Fig. 2 and 3 show an embodiment in which the ESD protection trench unit includes the ESD protection second trench 4 and the ESD protection third trench 5, in general, the groove width of the ESD protection second trench 4 is consistent with the groove width of the ESD protection third trench 5, and the groove width of the ESD protection second trench 4 and the groove width of the ESD protection third trench 5 are 2 to 2.5 times as large as the groove width of the cell trench 2.

And when polysilicon deposition is carried out after the second groove 4 and the third groove 5 are obtained, obtaining the conductive polysilicon 11 of the second electrode in the cell groove, and simultaneously preparing two N-type second polysilicon bodies in the grooves in the second groove 4 and the third groove 5. As can be seen from fig. 3 and the above description, the two in-groove N-type second polysilicon bodies may be the first in-groove N-type second polysilicon body 12 and the second in-groove N-type second polysilicon body 14, and the first in-groove N-type second polysilicon body 12 and the second in-groove N-type second polysilicon body 14 may be integrated or independent two forms, and at this time, an in-groove P-type second polysilicon body filling region 13 is formed in the central regions of the ESD protection second trench 4 and the ESD protection third trench 5.

In the implementation, when the first in-groove N-type second polysilicon body 12 and the second in-groove N-type second polysilicon body 14 are formed by deposition, the thickness of the deposited layer is 30% of the designed width of the ESD trench, and the relationship between the width of the ESD protection second trench 4, the width of the ESD protection third trench 5 and the width of the cell trench 2 is utilized to obtain the cell second electrode conductive polysilicon 11, and the in-groove P-type second polysilicon body filling region 13 can be formed, as shown in fig. 3.

Thereafter, P-type polysilicon filling is performed in the ESD protection second trench 4 and the ESD protection third trench 5, and the P-type polysilicon is filled in the in-trench P-type second polysilicon body filling region 13 to form an in-trench P-type second polysilicon body 15, as shown in fig. 4, at this time, i.e., a polysilicon second cell group is formed.

After the second polysilicon unit group is formed, the P-type base region 16 and the n+ source region 14 are prepared, and the specific process of preparing the P-type base region 16 and the n+ source region 14 may refer to the above description, and the specific process may be based on that the P-type base region 16 and the n+ source region 14 can be prepared. Because the P-type base region 16 is prepared by using a common injection mode, when the n+ source region 14 is prepared, N-type impurity ions are injected into the first trench N-type second polysilicon body 12 and the region where the second trench N-type second polysilicon body 14 is located, so as to ensure the reliability of forming the polysilicon second unit group in the ESD protection second trench 4 and the ESD protection third trench 5.

In fig. 5, when the P-type base region 16 and the n+ source region 14 are formed in the active region, the P-type third doped region 38 and the n+ doped region 37 are also formed in the terminal protection region at the same time, and the P-type third doped region 38 and the n+ doped region 37 may be described above, so that the distribution of the P-type third doped region 38 and the n+ doped region 37 may be selected according to the actual process requirements, which is not described herein.

After the P-type base region 16 and the n+ source region 14 are formed, the insulating dielectric layer 18 is prepared and metal deposition is performed, and in this embodiment, the front first electrode metal 20, the front second electrode metal 19 and the connection metal 21 are formed at the same time after the metal deposition, and the specific function and connection relationship are as described above with reference to fig. 6. The process conditions and processes for forming the front first electrode metal 20, the front second electrode metal 19, and the connection metal 21 after deposition may be selected according to requirements using conventional processes, and specific process conditions and the like.

In fig. 6, the specific connection between the front first electrode metal 20 and the cell first electrode conductive polysilicon 6, the terminal voltage-resistant conductive polysilicon 9, and the N-type second polycrystalline ohmic contact in the rightmost trench in the ESD protection third trench 5, and the front second electrode metal 19 and the connection metal 21 will be referred to the above description, and will not be repeated here.

In specific implementation, when a schottky diode unit needs to be prepared in the terminal protection area at the same time, the diode first trench 32 and the cell trench 2 may be formed by the same trench etching step, after the diode first trench 32 is formed by etching, the diode second trench 35 may be obtained by etching the trench at the bottom of the diode first trench 32, and the specific process conditions and processes for forming the diode first trench 32 and the diode second trench 35 by etching may be selected according to actual needs.

In addition, the seed layer 31 in the groove, the P-type first doped region 30, the polysilicon body 34 in the groove of the schottky diode unit and the like can be prepared and formed by adopting the technical means commonly used in the technical field, and specific process conditions, steps and the like can be selected according to requirements so as to meet the process compatibility with the groove type power semiconductor device.

Claims

1. An ESD-resistant groove type power semiconductor device comprises a semiconductor substrate, an active region prepared in the central region of the semiconductor substrate and a terminal protection region surrounding the active region; characterized by further comprising an ESD protection structure prepared in the terminal protection area, wherein,

The ESD protection polycrystalline silicon unit is in metal ohmic contact with a front first electrode for forming a front first electrode of the power semiconductor device and a front second electrode for forming a front second electrode of the power semiconductor device, so that the ESD protection polycrystalline silicon unit is connected in series between the front first electrode and the front second electrode of the power semiconductor device;

2. The ESD resistant trench power semiconductor device of claim 1, wherein said ESD protection polysilicon cells comprise at least one first set of polysilicon cells, wherein,

3. The ESD-resistant trench power semiconductor device of claim 1, wherein the ESD protection trench cell comprises an ESD protection second trench and an ESD protection third trench juxtaposed to the ESD protection second trench, wherein,

4. The ESD resistant trench power semiconductor device of claim 1 wherein a second conductivity type second doped region is disposed within the second conductivity type first doped region, wherein,

5. The ESD resistant trench power semiconductor device of claim 1 further comprising extra-trench polysilicon bodies disposed on either side of the diode first trench notch in a cross-section of said power semiconductor device wherein,

6. The ESD-resistant trench power semiconductor device of claim 1, wherein the in-trench seed layer comprises a Ti layer and/or a TiN layer.

7. The ESD-resistant trench power semiconductor device of any of claims 1 to 6, further comprising termination voltage-resistant trenches within the termination protection region, wherein,

8. An ESD-resistant trench power semiconductor device according to any of claims 1 to 6, comprising a plurality of parallel distributed cells in the active region, wherein,

the cells adopt a groove structure.

9. The ESD resistant trench power semiconductor device of claim 8 wherein said cells are of SGT configuration wherein,

10. A method for preparing an ESD-resistant trench power semiconductor device, which is used for preparing the power semiconductor device of claim 1, wherein the method for preparing the power semiconductor device comprises the following steps:

when preparing a metal layer above the front surface of a semiconductor substrate, ohmic contact is made between front surface first electrode metal for forming a front surface first electrode and front surface second electrode metal for forming a front surface second electrode and an ESD protection polysilicon unit, so that the ESD protection polysilicon unit is connected in series between the front surface first electrode and the front surface second electrode of a power semiconductor device;

11. The method of manufacturing an ESD protection trench type power semiconductor device of claim 10, wherein when the ESD protection trench cell comprises an ESD protection first trench, the method of manufacturing an ESD protection polysilicon cell comprises:

12. The method of manufacturing an ESD protection trench type power semiconductor device of claim 10, wherein when the ESD protection trench cell comprises the ESD protection second trench and the ESD protection third trench, the method of manufacturing the ESD protection polysilicon cell comprises:

13. The method for manufacturing the ESD protection trench type power semiconductor device according to claim 12, wherein bottoms of the ESD protection second trench and the ESD protection third trench are located below the second conductivity type base region;

14. The method for manufacturing an ESD protection trench type power semiconductor device according to any one of claims 10 to 13, further comprising a termination voltage-resistant trench formed in the termination protection region during trench etching, wherein,