CN220086039U

CN220086039U - Power semiconductor device integrated with RC absorber

Info

Publication number: CN220086039U
Application number: CN202320950694.XU
Authority: CN
Inventors: 范捷
Original assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Current assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Priority date: 2023-04-23
Filing date: 2023-04-23
Publication date: 2023-11-24
Anticipated expiration: 2033-04-23

Abstract

The utility model relates to a power semiconductor device integrated with an RC absorber. The method comprises the steps that a plurality of RC absorbers for absorbing oscillating voltage are prepared between any two adjacent cells in an active region, wherein each RC absorber comprises an absorption doping region and a plurality of absorption grooves, the absorption doping regions are prepared in an epitaxial layer of a semiconductor substrate, absorption polysilicon bodies are filled in the absorption grooves, and the absorption polysilicon bodies are insulated and isolated from the absorption doping regions through insulating isolation layers prepared in the absorption doping regions; the absorption doped region is in contact with the epitaxial layer of the semiconductor substrate. According to the utility model, through the integrated RC absorber, high surge current can be resisted, voltage oscillation in the switching process can be absorbed, the dVds/dt tolerance of the voltage oscillation is improved, the failure of the device caused by the dVds/dt of the voltage oscillation is effectively prevented, and the EMI problem in the switching process is eliminated.

Description

Power semiconductor device integrated with RC absorber

Technical Field

The utility model relates to a power semiconductor device, in particular to a power semiconductor device integrated with an RC absorber.

Background

The MOSFET (metal oxide semiconductor field effect transistor) has advantages of high switching speed, low switching loss, high input impedance, voltage driving, high frequency, and the like, and is widely used as a power switching transistor in various fields such as switching power supplies, automotive electronics, motor driving, and the like.

When the MOSFET device is used as a power switch tube, the MOSFET device works in an ON (ON) -OFF (OFF) rapid cycle conversion state, the internal parasitic capacitance Cds of the MOSFET device is charged and discharged rapidly, and the MOSFET device faces to very high voltage shock dVds/dt and current shock dIds/dt between a drain electrode and a source electrode, and the high voltage shock dVds/dt is superposed in a switch system and can become a main interference source of electric field coupling and magnetic field coupling, namely EMI (electromagnetic interference); therefore, how to effectively reduce the interference of electric field coupling and magnetic field coupling is a technical problem that needs to be solved at present.

Disclosure of Invention

The utility model aims to overcome the defects in the prior art and provides a power semiconductor device of an integrated RC absorber, which can resist high surge current and absorb voltage oscillation in the switching process through the integrated RC absorber, so that the dVds/dt resistance of the voltage oscillation is improved, the failure of the device caused by the dVds/dt is effectively prevented, and the EMI problem in the switching process is eliminated.

According to the technical proposal provided by the utility model, the power semiconductor device integrated with the RC absorber comprises a semiconductor substrate and an active area prepared in the central area of the semiconductor substrate, wherein the active area comprises a plurality of parallel distributed elementary cells,

in the active region, a plurality of RC absorbers for absorbing oscillating voltage are prepared between any two adjacent cells, wherein,

the RC absorber comprises an absorption doped region and a plurality of absorption grooves, wherein the absorption doped region is prepared in an epitaxial layer of a semiconductor substrate, the absorption grooves are filled with absorption polysilicon bodies, and the absorption polysilicon bodies are insulated and isolated from the absorption doped region through insulating isolation layers prepared in the absorption doped region;

the conductivity type of the absorption doped region is consistent with that of the semiconductor substrate, the doping concentration of the absorption doped region is larger than that of the epitaxial layer, and the absorption doped region is in contact with the epitaxial layer of the semiconductor substrate.

When the RC absorber comprises a plurality of absorption grooves, the absorption grooves are distributed in parallel in the absorption doping area, wherein,

the absorption polysilicon bodies filled in the absorption grooves are connected into a whole, and the insulating isolation layer covers the inner walls of the absorption grooves and covers the absorption doped regions between the adjacent absorption grooves.

When the doping type of the semiconductor substrate is the first conductivity type and the cell in the active region adopts a groove structure, the cell groove is vertically distributed in the epitaxial layer of the semiconductor substrate, and the bottom of the cell groove is positioned below a base region traversing the second conductivity type in the active region;

and for the absorption groove in the RC absorber, the absorption groove penetrates through the second conductive type base region, the absorption doping region is in contact with the second conductive type base region, and the bottom of the absorption groove is also positioned below the second conductive type base region.

And the active region further comprises a first conductive type source region which is contacted with the outer side wall of the cell groove, the first conductive type source region is positioned in the second conductive type base region, and the first conductive type source region and the second conductive type base region are in ohmic contact with source metal above the epitaxial layer.

The absorption doped region has a doping concentration greater than that of the first conductivity type source region.

When the cell in the active region adopts an SGT structure, the cell of the SGT structure comprises cell source electrode conductive polysilicon positioned in a cell groove and cell grid electrode conductive polysilicon positioned in the cell groove, wherein,

in the unitary cell groove, the cell grid conductive polysilicon is positioned above the cell source conductive polysilicon, the cell grid conductive polysilicon is insulated and isolated from the cell source conductive polysilicon through an in-groove insulating oxide layer in the cell groove, and the cell grid conductive polysilicon and the cell source conductive polysilicon are insulated and isolated from the inner wall of the cell groove through an in-groove insulating oxide layer;

ohmic contact is formed between the cell source electrode conductive polysilicon and the source metal, and ohmic contact is formed between the cell gate electrode conductive polysilicon and the gate metal;

the bottom of the cell gate conductive polysilicon and the bottom of the absorbing polysilicon body are located below the second conductivity type base region.

The absorption polysilicon body and the cell grid conductive polysilicon are formed by filling in the same process step.

And an insulating dielectric layer covering the epitaxial layer, wherein,

the source metal is insulated and isolated from the cell gate conductive polysilicon by an insulating dielectric layer.

The insulating isolation layer includes a silicon dioxide layer.

The power semiconductor device further comprises a back electrode structure on the back surface of the semiconductor substrate, and the back electrode junction is matched with the back surface of the semiconductor substrate, so that the formed power semiconductor device is a MOSFET type power device or an IGBT type power device.

In the "first conductivity type" and "second conductivity type", for an N-type power semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power semiconductor device, the first conductivity type and the second conductivity type refer to the type that is the opposite of an N-type power semiconductor device.

The utility model has the advantages that: a plurality of absorption grooves are arranged in the absorption doped region, an absorption polysilicon body is filled in the absorption grooves, and the absorption polysilicon body and the absorption doped region form a MIS capacitor structure form through an insulating isolation layer; the absorption doped region is contacted with the epitaxial layer, so that an RC absorption branch can be formed when the power semiconductor device works, the formed RC absorption branch can be used for absorbing oscillating voltage in the switching process, the tolerance of the voltage oscillation dVds/dt is improved, the device is effectively prevented from being invalid due to the voltage oscillation dVds/dt, and the EMI problem in the switching process is eliminated;

when the plurality of absorption grooves are distributed in parallel, comb-tooth-shaped forms can be formed, the capacitance area of the RC absorber can be effectively increased, and the EMI interference resistance effect is further improved

Drawings

Fig. 1 is a schematic diagram of an embodiment of a power semiconductor device of the present utility model.

Fig. 2-5 are cross-sectional views of one embodiment of a process for fabricating a power semiconductor device according to the present utility model, wherein,

fig. 2 is a cross-sectional view of the insulating isolation oxide layer of the present utility model after it has been prepared.

Fig. 3 is a cross-sectional view of the cell gate conductive polysilicon and the absorbing polysilicon body prepared in accordance with the present utility model.

Fig. 4 is a cross-sectional view of the present utility model after a contact hole is formed.

Fig. 5 is a cross-sectional view of the present utility model after source metal is formed.

Reference numerals illustrate: the semiconductor device comprises a 1-epitaxial layer, a 2-cell trench, a 3-P type base region, a 4-insulating dielectric layer, a 5-source metal, a 6-cell trench lower insulating oxide layer, a 7-cell source conductive polysilicon, an 8-cell gate conductive polysilicon, a 9-absorption doped region, a 10-absorption polysilicon body, an 11-insulating isolation layer, a 12-N+ source region, a 13-absorption trench, a 14-insulating isolation oxide layer, a 15-cell trench upper insulating oxide layer and a 16-contact hole.

Detailed Description

The utility model will be further described with reference to the following specific drawings and examples.

In order to resist high surge current and absorb voltage oscillation in the switching process, improve the tolerance of the voltage oscillation dVds/dt, effectively prevent the device from losing efficacy caused by the voltage oscillation dVds/dt, eliminate the EMI problem in the switching process, and take the first conductivity type as N type as an example for the power semiconductor device of the integrated RC (resistance-capacitance) absorber, in one embodiment of the utility model, the power semiconductor device comprises a semiconductor substrate and an active area prepared in the central area of the semiconductor substrate, the active area comprises a plurality of cells distributed in parallel,

the RC absorber comprises an absorption doped region 9 and a plurality of absorption grooves 13, wherein the absorption doped region 9 is prepared in the epitaxial layer 1 of the semiconductor substrate, the absorption grooves 13 are filled with absorption polysilicon bodies 10, and the absorption polysilicon bodies 10 are insulated and isolated from the absorption doped region 9 through insulating isolation layers 11 prepared in the absorption doped region 9;

the conductivity type of the absorption doped region 9 is consistent with that of the semiconductor substrate, the doping concentration of the absorption doped region 9 is larger than that of the epitaxial layer 1, and the absorption doped region 9 is in contact with the epitaxial layer 1 of the semiconductor substrate.

Specifically, for an N-type power semiconductor device, the conductivity type of the semiconductor substrate is N-type, and the semiconductor substrate may be made of a conventional material, for example, may be in the form of silicon, SIC, or the like, and may be specifically selected according to actual needs, so as to meet actual application requirements. Generally, an active region is prepared in a central region of a semiconductor substrate, the active region is generally distributed on the front surface of the semiconductor substrate, and the function of the active region is consistent with that of the existing power semiconductor device. The semiconductor substrate generally comprises an n+ substrate and an N-type epitaxial layer 1 positioned on the n+ substrate, wherein the doping concentration of the epitaxial layer is generally smaller than that of the n+ substrate; the active region is prepared on the front side of the semiconductor substrate, which generally means that the active region is prepared in the epitaxial layer 1. The active region generally comprises a plurality of cells, and the cells in the active region are connected in parallel into a whole.

As can be seen from the above description, the power semiconductor device may have voltage oscillation during the switching process, so that in order to absorb the oscillation voltage, an RC absorber needs to be prepared in the active area, specifically, the RC absorber may be distributed between any two adjacent cells, as shown in fig. 1 and 5, which illustrates a case of distributing one RC absorber between two adjacent cells. Of course, a plurality of RC absorbers or no RC absorbers may be disposed between two adjacent cells, and the distribution of the RC absorbers in the active region may be selected according to actual needs, so as to meet the requirement of absorbing the oscillating voltage in the switching process.

Specifically, the RC absorber comprises an absorption doped region 9 and an absorption trench 13, wherein the absorption doped region 9 is made of N-type conductivity, the absorption trench 13 extends vertically downwards from the front surface of the epitaxial layer 1, and the bottom of the absorption trench 13 is located in the absorption doped region 9. The absorption polysilicon body 10 is filled in the absorption groove 13, the absorption polysilicon body 10 is insulated and isolated from the absorption doped region 9 through the insulation isolation layer 11, and at the moment, the absorption polysilicon body 10 and the absorption doped region 9 form a MIS capacitor structure form through the insulation isolation layer 11; the absorption doped region 9 is in contact with the epitaxial layer 1, so that an RC absorption branch can be formed when the power semiconductor device works, oscillation voltage absorption in the switching process can be realized by utilizing the formed RC absorption branch, the voltage oscillation dVds/dt tolerance is improved, the device is effectively prevented from losing efficacy caused by the voltage oscillation dVds/dt, and the EMI problem in the switching process is eliminated.

In one embodiment of the present utility model, when the RC absorber includes a plurality of absorption trenches 13, the plurality of absorption trenches 13 are arranged in parallel in the absorption doped region 9, wherein,

the absorption polysilicon bodies 10 filled in the absorption trenches 13 are connected with each other into a whole, and the insulating isolation layer 11 covers the inner walls of the absorption trenches 13 and covers the absorption doped regions 9 between adjacent absorption trenches 13.

An embodiment of an RC absorber is shown in fig. 1 and 5, which includes three absorption trenches 13 arranged in parallel, each absorption trench 13 is filled with an absorption polysilicon body 10, and all the absorption polysilicon bodies 10 are connected to each other as a whole.

The insulating isolation layer 11 is a silicon dioxide layer, and in order to achieve the purpose of insulating isolation, the insulating isolation layer 11 generally covers the inner wall of the absorption groove 13; since the absorption polysilicon bodies 10 in the absorption trenches 13 are connected together, the insulation isolation layer 11 also needs to cover the absorption doped regions 9 between adjacent absorption trenches 13, and the distribution position of the insulation isolation layer 11 is specifically in order to satisfy the insulation isolation between the absorption polysilicon bodies 10 and the absorption doped regions 9.

When the plurality of absorption grooves 13 are distributed in parallel, comb-tooth-shaped forms can be formed, the capacitance area of the RC absorber can be effectively increased, and the effect of resisting EMI interference is further improved.

In particular, the cells in the active region may be planar or trench, and the type of the cells may be selected as desired. In one embodiment of the utility model, when the doping type of the semiconductor substrate is N conductive type and the cell in the active region adopts a trench structure, the cell trench 2 is vertically distributed in the epitaxial layer 1 of the semiconductor substrate, and the bottom of the cell trench 2 is positioned below the P-type base region 3 in the active region;

for the absorption groove 13 in the RC absorber, the absorption groove 13 penetrates through the P-type base region 3, the absorption doped region 9 is in contact with the P-type base region 3, and the bottom of the absorption groove 13 is also positioned below the P-type base region 3.

When the cell adopts the trench structure, the cell at least comprises cell trenches 2, the cell trenches 2 are vertically distributed in the epitaxial layer 1, the notch of the cell trench 2 corresponds to the surface of the epitaxial layer 1, and in fig. 1 and 5, the depth of the cell trench 2 is greater than the depth of the absorption trench 13, that is, the bottom of the absorption trench 13 is located above the bottom of the cell trench 2. In fig. 1 and 5, three absorption grooves 13 are distributed between two cell grooves 2.

In general, a P-type base region 3 is disposed in the epitaxial layer 1, and the P-type base region 3 generally traverses the active region, that is, the P-type base region 3 is distributed in the active region. The cell groove 2 and the absorption groove 13 penetrate through the P-type base region 3, and the groove bottom of the cell groove 2 and the groove bottom of the absorption groove 3 are positioned below the P-type base region 3.

In order to form a conductive channel, in general, in the active region, an n+ source region 12 is further included in contact with the outer sidewall of the cell trench 2, where the n+ source region 12 is located in the P-type base region 3, and the n+ source region 12 and the P-type base region 3 are in ohmic contact with the source metal 5 above the epitaxial layer 1.

Specifically, the source metal 5 is in ohmic contact with the n+ source region 12, i.e., a source electrode of a MOSFET-type device or an emitter of an IGBT-type device may be formed using the source metal 5. N+ source region 12 in P-type base region 3, n+ source region 12 needs to be in contact with the outer sidewall of cell trench 2, and of course, P-type base region 3 needs to be in contact with the outer sidewall of cell trench 2, but since absorption trench 13 is surrounded by absorption doped region 9, absorption trench 13 is isolated from P-type base region 3 by absorption doped region 9.

In one embodiment of the present utility model, the doping concentration of the absorption doped region 9 is greater than the doping concentration of the n+ source region 12, and at this time, the doping concentration of the n+ source region 12 is greater than the doping concentration of the epitaxial layer 1, and the doping concentration of the absorption doped region 9 is greater than the doping concentration of the n+ source region 12.

In one embodiment of the present utility model, when the cell in the active region adopts the SGT structure, the cell of the SGT structure includes the cell source conductive polysilicon 7 in the cell trench 2 and the cell gate conductive polysilicon 8 in the cell trench 2, wherein,

in the unitary cell groove 2, the cell grid conductive polysilicon 8 is positioned above the cell source conductive polysilicon 7, the cell grid conductive polysilicon 8 is insulated and isolated from the cell source conductive polysilicon 7 through an in-groove insulating oxide layer in the cell groove 3, and the cell grid conductive polysilicon 8 and the cell source conductive polysilicon 7 are insulated and isolated from the inner wall of the cell groove through the in-groove insulating oxide layer;

the cell source electrode conductive polysilicon 7 is in ohmic contact with the source metal 5, and the cell gate electrode conductive polysilicon 8 is in ohmic contact with the gate metal;

the bottom of the cell gate conductive polysilicon 8 and the bottom of the absorber polysilicon body 10 are located below the P-type base region 3.

One embodiment of the SGT structure in an up-down configuration is shown in fig. 1 and 5, which includes a cell source conductive polysilicon 7 and a cell gate conductive polysilicon 8, the cell gate conductive polysilicon 8 being located above the cell source conductive polysilicon 7, typically the width of the cell gate conductive polysilicon 8 being greater than the width of the cell source conductive polysilicon 7. The cell gate conductive polysilicon 8 is insulated from the cell conductive polysilicon 7 and from the inner wall of the cell trench 2.

In the figure, the insulation oxide layer in the groove comprises a cell groove lower insulation oxide layer 6 positioned at the lower part of the cell groove 2 and a cell groove upper insulation oxide layer 15 positioned at the upper part, wherein the cell groove lower insulation oxide layer 6 and the cell groove upper insulation oxide layer 15 are both silicon dioxide layers, the thickness of the cell groove lower insulation oxide layer 6 is larger than that of the cell groove upper insulation oxide layer 15, the cell groove lower insulation oxide layer 6 covers the inner wall and the bottom wall of the lower part of the cell groove 2, and the cell groove upper insulation oxide layer 15 covers the inner wall of the upper part of the cell groove 2. Of course, the insulating oxide layer in the groove can also take other forms, so as to meet the requirement of insulating isolation.

In the implementation, the cell source electrode conductive polysilicon 7 is in ohmic contact with the source metal 5, and the cell gate electrode conductive polysilicon 8 is in ohmic contact with the gate metal, so that the gate metal can be used for forming a gate electrode of a MOSFET device or forming a gate electrode of an IGBT device, which is in accordance with the prior art.

In one embodiment of the present utility model, the bottom of the cell gate conductive polysilicon 8 and the bottom of the absorbing polysilicon body 10 are located below the P-type base region 3, and specifically, the absorbing polysilicon body 10 and the cell gate conductive polysilicon 8 are formed by filling in the same process step.

In addition, an insulating dielectric layer 4 is further included to cover the epitaxial layer 1, wherein the source metal 5 is insulated from the cell gate conductive polysilicon 8 by the insulating dielectric layer 4.

In fig. 1 and 5, an insulating dielectric layer 4 is covered on the epitaxial layer 1, and insulating isolation between the source metal 5 and the cell gate conductive polysilicon 8 is achieved by using the insulating dielectric layer 4, where the material of the insulating dielectric layer 4 includes PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass).

In one embodiment of the utility model, the semiconductor device further comprises a back electrode structure on the back surface of the semiconductor substrate, and the back electrode junction is matched with the back surface of the semiconductor substrate, so that the formed power semiconductor device is a MOSFET type power device or an IGBT type power device.

Those skilled in the art will appreciate that the same front side cell structure may be used for either MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type power devices or IGBT (Insulated Gate Bipolar Transistor) type power devices, but the back side electrode structures may be different. The specific form of the back electrode structure and the case of forming a MOSFET type power device or an IGBT type power device using the back electrode structure are consistent with the prior art.

The power semiconductor device shown in fig. 1 can be manufactured through the process steps of fig. 2 to 5, and a specific process will be described below.

In the process, it is generally necessary to provide a semiconductor substrate and prepare a cell trench 2 in an epitaxial layer 1 of the semiconductor substrate, where the cell trench 2 extends vertically downward from the surface of the epitaxial layer 1, and the depth of the cell trench 2 is generally smaller than the thickness of the epitaxial layer 1. When preparing the cellular groove 2, a groove etching process commonly used in the technical field can be adopted for the epitaxial layer 1, and specific groove etching process conditions and processes can be selected according to actual needs so as to realize preparation of the required cellular groove 2.

After the cellular trench 2 is formed, oxide layer growth and polysilicon deposition are performed, and generally, after the oxide layer growth, polysilicon deposition is performed, and the deposited polysilicon needs to be etched, and when the polysilicon is etched, the epitaxial layer 1 is etched, so that the absorption trench 13 is simultaneously prepared in the epitaxial layer 1. After forming the absorption trench 13, an oxide layer growth process is performed, at this time, a cell source conductive polysilicon 7, a cell trench lower insulating oxide layer 6 wrapping the cell source conductive polysilicon 7, and an insulating isolation oxide layer 14 are formed, and in fig. 2, the insulating isolation oxide layer 14 covers the inner wall of the upper portion in the cell trench 2, covers the inner wall of the absorption trench 13, and covers the front surface of the epitaxial layer 1.

Polysilicon deposition is performed on the front surface of the semiconductor substrate to thin the deposited polysilicon to obtain the cell gate conductive polysilicon 8 and the absorption polysilicon body 10. Thereafter, P-type impurity ions are implanted to form a P-type base region 3 in the epitaxial layer 1, and N-type impurity ions are implanted to form an n+ source region 12 and an absorption doped region 9, as shown in fig. 3. In the process, the conditions of ion implantation and the like can be selected according to the needs, so that the P-type base region 3, the n+ source region 12 and the absorption doped region 9 can be prepared.

And depositing a dielectric layer on the front surface of the semiconductor substrate to obtain an insulating dielectric layer 4, wherein the insulating dielectric layer 4 covers the epitaxial layer 1, and the insulating dielectric layer 4 can cover the cell grid conductive polysilicon 8.

The insulating dielectric layer 4 is etched to form a contact hole 16, as shown in fig. 4, the contact hole 16 penetrates through the dielectric layer 4 and penetrates into the P-type base region 3, and the outer side wall of the contact hole 16 is also in contact with the n+ source region 12.

After etching to obtain the contact hole 16, metal deposition is performed above the front surface of the semiconductor substrate to form source metal 5 and gate metal, the source metal 5 is covered on the insulating dielectric layer 4 and filled in the contact hole 16, and the source metal 5 filled in the contact hole 16 can directly contact with the P-type base region 3 and the n+ source region 12, as shown in fig. 5, so that the preparation of the cell is completed.

Of course, the power semiconductor device can also be manufactured by adopting other processes, and the specific process can be selected according to the needs, so that the RC absorption region can be manufactured in the active region of the power semiconductor device.

Claims

1. A power semiconductor device integrated with RC absorber comprises a semiconductor substrate and an active region prepared in the central region of the semiconductor substrate, wherein the active region comprises a plurality of parallel distributed cells,

2. The integrated RC absorber power semiconductor device of claim 1, wherein the plurality of absorption trenches are juxtaposed in the absorption doped region when the RC absorber includes a plurality of absorption trenches therein, wherein,

3. The power semiconductor device of claim 1, wherein when the doping type of the semiconductor substrate is the first conductivity type and the cells in the active region are in a trench structure, the cell trenches are vertically distributed in the epitaxial layer of the semiconductor substrate, and the bottoms of the cell trenches are positioned below the base region of the second conductivity type in the active region;

4. A power semiconductor device integrated with an RC absorber as in claim 3 further comprising a first conductivity type source region in contact with the cell trench outer sidewall within the active region, the first conductivity type source region being located within the second conductivity type base region, and the first conductivity type source region and the second conductivity type base region being in ohmic contact with the source metal over the epitaxial layer.

5. The integrated RC absorber power semiconductor device of claim 4, wherein the absorption doping region has a doping concentration greater than a doping concentration of the first conductivity type source region.

6. The integrated RC absorber power semiconductor device of claim 4, wherein when the cells in the active region are SGT, the SGT-structured cells comprise cell source conductive polysilicon in the cell trench and cell gate conductive polysilicon in the cell trench, wherein,

7. The integrated RC absorber power semiconductor device of claim 6, wherein the absorber polysilicon body is filled with the same process step as the cell gate conductive polysilicon.

8. The integrated RC absorber power semiconductor device of claim 5, further comprising an insulating dielectric layer overlying the epitaxial layer, wherein,

9. The integrated RC absorber power semiconductor device of claim 1, wherein the insulating isolation layer comprises a silicon dioxide layer.

10. The power semiconductor device of any one of claims 1 to 9, further comprising a back electrode structure on the back side of the semiconductor substrate, the back electrode junction cooperating with the back side of the semiconductor substrate such that the power semiconductor device formed is a MOSFET-type power device or an IGBT-type power device.