CN117650161A - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN117650161A CN117650161A CN202311433549.5A CN202311433549A CN117650161A CN 117650161 A CN117650161 A CN 117650161A CN 202311433549 A CN202311433549 A CN 202311433549A CN 117650161 A CN117650161 A CN 117650161A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title abstract description 9
- 239000002184 metal Substances 0.000 claims description 88
- 230000004888 barrier function Effects 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device includes: a drift layer of the first conductivity type; a field stop layer of a first conductivity type; a collector layer of a second conductivity type; a first emitter layer of the first conductivity type, the collector layer being circumferentially disposed outside the first emitter layer; a ring layer of the second conductivity type, the ring layer corresponding to the junction of the collector layer and the first emitter layer, the ring layer being provided with a plurality of trench portions therein; and the well layer of the second conductivity type is arranged on two sides of the ring layer and at least partially corresponds to the collector layer and the first emitter layer, and a plurality of groove parts are arranged on the part of the well layer corresponding to the collector layer. Therefore, on the premise of ensuring the voltage-resistant capability of the semiconductor device, the conduction voltage drop of the second semiconductor device type region is improved, and the working performance of the semiconductor device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
RC-IGBT (reverse conducting type insulated gate bipolar transistor reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor) and FRD (fast recovery diode Fast Recovery Diode) on the same chip, so that the IGBT has the characteristics of forward conduction and reverse conduction, and has the advantages of small size, high power density, low cost, high reliability and the like.
In the related art, the FRD area and the IGBT area have the same design of grooves and contact holes, so that on one hand, the grooves occupy a certain area of the FRD area, the effective PN junction area is reduced, the forward voltage drop is increased, and on the other hand, the FRD area adopts the same technological process as the IGBT area, the potential barrier voltage drop is larger, and the forward voltage drop is larger.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to propose a semiconductor device having a lower forward conduction voltage drop.
The invention further provides a manufacturing method of the semiconductor device.
The semiconductor device according to an embodiment of the present invention includes: a drift layer of the first conductivity type; a field stop layer of a first conductivity type, the field stop layer being disposed on a lower surface of the drift layer; a collector layer of a second conductivity type provided on a lower surface of the field stop layer; a first emitter layer of a first conductivity type, the first emitter layer being disposed on a lower surface of the field stop layer, the collector layer being circumferentially disposed outside the first emitter layer; a ring layer of a second conductivity type, the ring layer being disposed within the drift layer, an upper surface of the ring layer constituting at least a portion of an upper surface of the drift layer, the ring layer corresponding to a junction of the collector layer and the first emitter layer, the ring layer being provided with a plurality of trench portions; the well layer of the second conductivity type is arranged in the drift layer, the upper surface of the well layer forms at least part of the upper surface of the drift layer, the well layer is arranged on two sides of the ring layer and at least partially corresponds to the collector layer and the first emitter layer, and a plurality of groove parts are arranged on the part of the well layer corresponding to the collector layer.
Therefore, the junction between the ring layer and the collector layer as well as the first emitter layer is correspondingly provided with a plurality of groove parts, the well layer is arranged on two sides of the ring layer and at least partially corresponds to the collector layer and the first emitter layer, and the part of the well layer corresponding to the collector layer is provided with the plurality of groove parts, so that the conduction voltage drop of the second semiconductor device type region is improved on the premise of ensuring the voltage-resistant capability of the semiconductor device, and the working performance of the semiconductor device is improved.
In some examples of the invention, the depth of the well layer in the up-down direction is smaller than the depth of the ring layer in the up-down direction.
In some examples of the invention, the depth of the trench portion in the up-down direction is greater than the depth of the well layer in the up-down direction, and the depth of the trench portion in the up-down direction is less than the depth of the ring layer in the up-down direction.
In some examples of the present invention, the cross section in the up-down direction of the ring layer is arc-shaped, and the cross section in the up-down direction of the well layer is rectangular.
In some examples of the present invention, second emitter layers are disposed on two sides of the trench, a dielectric layer is disposed on upper surfaces of the ring layer and the well layer, a first contact hole is formed between two adjacent trench portions, a second contact hole is formed on a portion of the dielectric layer corresponding to the first emitter layer, an emitter metal layer is disposed on an upper surface of the dielectric layer, at least a portion of the emitter metal layer penetrates through the first contact hole and is electrically connected with the second emitter layer, at least a portion of the emitter metal layer penetrates through the second contact hole and is electrically connected with a portion of the well layer located in the middle of the ring layer, a plurality of trench portions are disposed at intervals in a first direction, and a length of the second contact hole in the first direction is greater than a length of the first contact hole in the first direction.
In some examples of the present invention, a barrier metal layer is disposed on the surface of the dielectric layer, the barrier metal layer is located between the dielectric layer and the emitter metal layer, a third contact hole is formed in a portion of the barrier metal layer corresponding to the second contact hole, and at least a portion of the emitter metal layer penetrates through the third contact hole and the second contact hole and is electrically connected to a portion of the well layer located in the middle of the ring layer.
The manufacturing method of the semiconductor device according to the embodiment of the invention comprises the following steps: preparing a drift layer; implanting a ring layer of a second conductivity type in the drift layer, and annealing the ring layer; etching a groove part in the drift layer, and arranging an oxidation insulating layer on the upper surface of the drift layer; a well layer of a second conductivity type is implanted in the drift layer and annealed, wherein the well layer is located on both sides of the ring layer.
In some examples of the present invention, the implanting a well layer of a second conductivity type in the drift layer and annealing the well layer, wherein after the step of locating the well layer on both sides of the ring layer, the method of manufacturing the semiconductor device further includes: injecting a second emitter layer into the drift layer; a dielectric layer is arranged on the upper surface of the oxidation insulating layer; and a first contact hole is formed in the dielectric layer between the two adjacent groove parts, and a second contact hole is formed in the dielectric layer at a position corresponding to the well layer and positioned in the middle of the ring layer, wherein the length of the second contact hole in the first direction is greater than that of the first contact hole in the first direction.
In some examples of the present invention, after the step of forming a first contact hole in the dielectric layer between two adjacent trench portions, and forming a second contact hole in a portion of the dielectric layer between the well layer and the ring layer, the method for manufacturing the semiconductor device further includes: a barrier metal layer is arranged on the upper surface of the dielectric layer, the side walls of the dielectric layer corresponding to the first contact hole and the second contact hole, and the upper surfaces of the ring layer and the well layer; and etching parts of the barrier metal layer corresponding to the second contact hole and the two opposite side walls of the groove parts at the two sides of the second contact hole so as to etch a third contact hole.
In some examples of the present invention, after the step of etching the portions of the barrier metal layer corresponding to the second contact hole and the opposite sidewalls of the trench portion on both sides of the second contact hole to etch the third contact hole, the method for manufacturing the semiconductor device further includes: an emitter metal layer is arranged on the upper surface of the barrier metal layer, at least part of the emitter metal layer penetrates through the first contact hole and is electrically connected with the second emitter layer, and at least part of the emitter metal layer penetrates through the third contact hole and the second contact hole and is electrically connected with the part of the well layer located in the middle of the ring layer; a field stop layer is arranged on the lower surface of the drift layer; a collector layer of a second conductivity type is provided on a lower surface of the field stop layer; a first emitter layer is arranged at a position of the collector layer corresponding to the middle of the ring layer; and a collector metal layer is arranged on the lower surface of the collector layer.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention along A-A;
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of structure 1 according to an embodiment of the invention;
FIG. 5 is a cross-sectional view of structure 2 according to an embodiment of the invention;
FIG. 6 is a cross-sectional view of structure 3 according to an embodiment of the invention;
FIG. 7 is a cross-sectional view of structure 4 according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view of structure 5 according to an embodiment of the invention;
FIG. 9 is a cross-sectional view of structure 6 according to an embodiment of the invention;
fig. 10 is a cross-sectional view of structure 7 according to an embodiment of the invention.
Reference numerals:
100. a semiconductor device;
101. an active region; 1011. a first semiconductor device type region; 1012. a second semiconductor device type region; 102. a termination region;
10. a drift layer;
20. a field stop layer; 21. a collector layer; 22. a first emitter layer; 23. a collector metal layer;
30. a well layer; 31. a hoop layer; 32. a second emitter layer; 33. a dielectric layer; 331. a first contact hole; 332. a second contact hole; 34. a barrier metal layer; 341. a third contact hole; 35. an emitter metal layer;
40. a groove portion; 41. oxidizing the insulating layer; 42. and (3) polycrystalline silicon.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device according to an embodiment of the present invention, which may employ a method of manufacturing the semiconductor device, is described below with reference to fig. 1 to 10. The semiconductor apparatus 100 may be an RC-IGBT, the first semiconductor device type region 1011 may be an IGBT region, and the second semiconductor device type region 1012 may be an FRD region. In the following description, N and P denote conductivity types of semiconductors, and in the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type.
As shown in conjunction with fig. 1 and 2, a semiconductor device 100 according to the present invention may mainly include: a drift layer 10 of a first conductivity type, a field stop layer 20 of a first conductivity type, a collector layer 21 of a second conductivity type, a first emitter layer 22 of a first conductivity type, a ring layer 31 of a second conductivity type, and a well layer 30 of a second conductivity type.
Specifically, a second conductivity type ring layer 31 and a second conductivity type well layer 30 are provided within the first conductivity type drift layer 10, an upper surface of the ring layer 31 constitutes at least a part of an upper surface of the drift layer 10, an upper surface of the well layer 30 constitutes at least a part of an upper surface of the drift layer 10, the upper surface of the first conductivity type drift layer 10 is provided with the second conductivity type well layer 30, the first conductivity type first emitter layer 22 located in the well layer 30, the dielectric layer 33 located above the first emitter layer 22, and the emitter metal layer 35 located above the dielectric layer 33, a lower surface of the first conductivity type drift layer 10 is provided with the first conductivity type field stop layer 20, the second conductivity type collector layer 21 and the first conductivity type first emitter layer 22 located at a lower surface of the field stop layer 20, and the lowermost collector metal layer 23.
Further, the semiconductor apparatus 100 includes an active region 101 and a termination region 102 surrounding the active region 101, the collector layer 21 is circumferentially disposed outside the first emitter layer 22, a region corresponding to the collector layer 21 in the up-down direction is a first semiconductor device type region 1011, and a region corresponding to the first emitter layer 22 in the up-down direction is a second semiconductor device type region 1012, namely: the active region 101 of the semiconductor apparatus 100 may include a first semiconductor device type region 1011 and a second semiconductor device type region 1012, the emitter metal layer 35 may be used not only as an emitter terminal of the first semiconductor device type region 1011 but also as an anode terminal of the second semiconductor device type region 1012, and the collector metal layer 23 may be used not only as a collector terminal of the first semiconductor device type region 1011 but also as a cathode terminal of the second semiconductor device type region 1012, so that the first semiconductor device type region 1011 may implement forward conduction of the semiconductor apparatus 100, and the second semiconductor device type region 1012 may implement reverse conduction of the semiconductor apparatus 100, so that the semiconductor apparatus 100 may have characteristics of both forward conduction and reverse conduction.
As shown in fig. 2, the ring layer 31 corresponds to the boundary between the collector layer 21 and the first emitter layer 22, a plurality of trench portions 40 are provided in the ring layer 31, the well layer 30 is provided on both sides of the ring layer 31 and at least partially corresponds to the collector layer 21 and the first emitter layer 22, and a plurality of trench portions 40 are provided in a portion of the well layer 30 corresponding to the collector layer 21.
Specifically, the ring layer 31 corresponds to the interface of the collector layer 21 and the first emitter layer 22, that is: a ring layer 31 is provided at the interface of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, and well layers 30 are provided on both sides of the ring layer 31, the well layers 30 at least partially corresponding to the collector layer 21 and the first emitter layer 22, that is: the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are each provided with the well layer 30.
By providing a plurality of trench portions 40 in the ring layer 31, and providing a plurality of trench portions 40 in the well layer 30 at portions corresponding to the collector layer 21, namely: the trench portion 40 is disposed in the first semiconductor device type region 1011, and the trench portion 40 is not disposed in the second semiconductor device type region 1012, so that on one hand, the oxide insulating layer 41 and the polysilicon 42 can be sequentially deposited in the trench portion 40, and on the other hand, the gate can be formed at the trench portion 40, thereby ensuring the normal operation of the first semiconductor device type region 1011, and on the other hand, the trench portion 40 at the second semiconductor device type region 1012 can be omitted, so that the second semiconductor device type region 1012 is only a planar PN junction, thereby effectively increasing the effective area of the PN junction, reducing the forward conduction voltage drop of the second semiconductor device type region 1012, and thus, improving the operation performance of the semiconductor device 100.
Further, since the trench portion 40 at the second semiconductor device type region 1012 is omitted, the width of the second semiconductor type dopant required to be implanted in the first semiconductor device type region 1011 is far greater than the width of the second semiconductor type dopant required to be implanted in the second semiconductor device type region 1012, if the same implantation dose and annealing conditions are adopted, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 will be smaller than those of the first semiconductor device type region 1011, resulting in a problem of withstand voltage of the semiconductor apparatus 100, and by providing the ring layer 31 and the well layer 30 respectively, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be increased, ensuring that the junction depth and doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and ensuring the withstand voltage capability of the semiconductor apparatus 100.
Thus, by making the junction between the ring layer 31 and the collector layer 21 and the first emitter layer 22 correspond to each other, the ring layer 31 is provided with a plurality of grooves 40, the well layer 30 is disposed on both sides of the ring layer 31 and at least partially corresponds to the collector layer 21 and the first emitter layer 22, and the well layer 30 is provided with a plurality of grooves 40 at a portion corresponding to the collector layer 21, so that on the premise of ensuring the voltage-withstanding capability of the semiconductor device 100, the conduction voltage drop of the second semiconductor device type region 1012 can be improved, and the operation performance of the semiconductor device 100 can be improved.
As shown in fig. 2, the depth of the well layer 30 in the up-down direction is smaller than the depth of the ring layer 31 in the up-down direction. Specifically, by setting the depth in the up-down direction of the well layer 30 smaller than the depth in the up-down direction of the ring layer 31, it is possible to further secure the junction depth and the doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 to be the same as those of the first semiconductor device type region 1011, and thus it is possible to secure the withstand voltage capability of the second semiconductor device type region 1012 and even the semiconductor apparatus 100.
As shown in fig. 2, the depth of the trench portion 40 in the up-down direction is larger than the depth of the well layer 30 in the up-down direction, and the depth of the trench portion 40 in the up-down direction is smaller than the depth of the ring layer 31 in the up-down direction.
Specifically, by setting the depth of the trench portion 40 in the up-down direction to be greater than the depth of the well layer 30 in the up-down direction, the trench portion 40 located in the first semiconductor device type region 1011 of the well layer 30 can penetrate through the well layer 30 to reach the drift layer 10, thereby ensuring the normal operation of the first semiconductor device 100.
Further, the depth of the trench 40 in the up-down direction is set smaller than the depth of the ring layer 31 in the up-down direction, so that the ring layer 31 can surround the trench 40 at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, thereby ensuring that the junction depth and the doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as those of the first semiconductor device type region 1011, ensuring that the withstand voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and ensuring the operation performance of the semiconductor apparatus 100.
As shown in fig. 2, the cross section of the ring layer 31 in the up-down direction is arc-shaped, and the cross section of the well layer 30 in the up-down direction is rectangular.
Specifically, by making the cross section of the well layer 30 in the up-down direction rectangular, the lower surface of the well layer 30 is parallel to the upper surface of the drift layer 10, so that the well layer 30 of the second semiconductor device type region 1012 can be uniformly distributed and the depth of the second semiconductor device type region 1011 is the same as that of the first semiconductor device type region 1012, the operation performance of the second semiconductor device type region 1012 can be ensured, and the junction depths and doping concentrations of the middle part of the first semiconductor device type region 1011 in the first direction and the middle part of the second semiconductor device type region 1012 in the first direction are ensured to be the same.
Further, by making the cross section of the ring layer 31 in the up-down direction arc-shaped, the lower surface of the ring layer 31 is arc-shaped, so that the ring layer 31 can enclose the trench portion 40 located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, it is possible to ensure that the junction depth and the doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as those of the first semiconductor device type region 1011.
In this way, the withstand voltage of the first semiconductor device type region 1011 and the withstand voltage of the second semiconductor device type region 1012 can be made the same, the withstand voltage capability of the semiconductor apparatus 100 can be ensured, and the operation performance of the semiconductor apparatus 100 can be ensured.
As shown in fig. 2, the second emitter layer 32 is disposed on two sides of the trench 40, the dielectric layer 33 is disposed on the upper surfaces of the ring layer 31 and the well layer 30, the first contact hole 331 is disposed between two adjacent trench 40, the second contact hole 332 is disposed on the dielectric layer 33 at a portion corresponding to the first emitter layer 22, the emitter metal layer 35 is disposed on the upper surface of the dielectric layer 33, at least a portion of the emitter metal layer 35 penetrates through the first contact hole 331 and is electrically connected with the second emitter layer 32, at least a portion of the emitter metal layer 35 penetrates through the second contact hole 332 and is electrically connected with a portion of the well layer 30 located in the middle of the ring layer 31, the plurality of trench 40 are disposed at intervals in the first direction, and the length of the second contact hole 332 in the first direction is greater than the length of the first contact hole 331 in the first direction.
Specifically, by providing the dielectric layer 33 on the upper surfaces of the ring layer 31 and the well layer 30, the dielectric layer 33 can protect the well layer 30, and the risk of damage to the semiconductor device 100 can be reduced.
By providing the second emitter layer 32 on both sides of the trench portion 40, the first contact hole 331 is formed between the dielectric layer 33 corresponding to two adjacent trench portions 40, so that at least a portion of the emitter metal layer 35 may penetrate through the first contact hole 331 and be electrically connected to the second emitter layer 32, thereby ensuring normal operation of the first semiconductor device type region 1011.
Further, by opening the second contact hole 332 at the portion of the dielectric layer 33 corresponding to the first emitter layer 22, the length of the second contact hole 332 in the first direction is greater than the length of the first contact hole 331 in the first direction, and the second contact hole 332 directly corresponds to the second semiconductor device type region 1012, so that the second semiconductor device type region 1012 is different from the first semiconductor device type region 1011 in that a plurality of first contact holes 331 are provided, and only one second contact hole 332 is provided at the second semiconductor device type region 1012, so that at least part of the emitter metal layer 35 penetrates through the second contact hole 332 to be electrically connected with the portion of the well layer 30 located in the middle of the ring layer 31, namely: the emitter metal layer 35 is brought into contact with the well layer 30 of the second semiconductor device type region 1012, so that normal operation of the second semiconductor device type region 1012 can be ensured.
As shown in fig. 2, a barrier metal layer 34 is disposed on the surface of the dielectric layer 33, the barrier metal layer 34 is located between the dielectric layer 33 and the emitter metal layer 35, a third contact hole 341 is formed in a portion of the barrier metal layer 34 corresponding to the second contact hole 332, and at least a portion of the emitter metal layer 35 penetrates through the third contact hole 341 and the second contact hole 332. And is electrically connected to a portion of the well layer 30 located in the middle of the ring layer 31.
Specifically, in view of the smaller width of the first contact hole 331 on the dielectric layer 33, in order to facilitate the arrangement of the emitter metal layer 35 and ensure the contact between the emitter metal layer 35 and the second emitter layer 32, a barrier metal layer 34 may be disposed on the surface of the dielectric layer 33, and then the emitter metal layer 35 may be deposited, so that the barrier metal layer 34 is located between the dielectric layer 33 and the emitter metal layer 35, thereby ensuring the normal extraction of current and ensuring the normal operation of the first semiconductor device type region 1011 and even the semiconductor device 100.
Further, considering that the width of the second contact hole 332 is larger, on the premise that the electrical connection between the emitter metal layer 35 and the portion of the well layer 30 located in the middle of the ring layer 31 is not affected, the third contact hole 341 is formed in the portion of the barrier metal layer 34 corresponding to the second contact hole 332, so that the barrier metal layer 34 at the second semiconductor device type region 1012 can be omitted, at least part of the emitter metal layer 35 can penetrate through the third contact hole 341 and the second contact hole 332 and be directly electrically connected with the portion of the well layer 30 located in the middle of the ring layer 31, contact resistance can be reduced, forward conduction voltage drop of the second semiconductor device type region 1012 can be reduced, and the working performance of the second semiconductor device type region 1012 and even the semiconductor device 100 can be improved.
As shown in fig. 3, the method of manufacturing the semiconductor device 100 according to the present invention may mainly include the steps of: preparing a drift layer 10; injecting a ring layer 31 of the second conductivity type into the drift layer 10, and annealing the ring layer 31; a trench portion 40 is etched in the drift layer 10, and an oxide insulating layer 41 is provided on the upper surface of the drift layer 10; the well layer 30 of the second conductivity type is implanted in the drift layer 10, and the well layer 30 is annealed, wherein the well layer 30 is located at both sides of the ring layer 31.
Specifically, in manufacturing the semiconductor apparatus 100, the first conductivity type drift layer 10 is provided, the second conductivity type ring layer 31 may be implanted into the drift layer 10, and the ring layer 31 may be annealed, the ring layer 31 may be located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, then the trench portion 40 may be etched only at the location of the drift layer 10 corresponding to the first semiconductor device type region 1011, and the oxide insulating layer 41 may be disposed on the upper surface of the drift layer 10, and then the second conductivity type well layer 30 may be implanted into the drift layer 10, and the well layer 30 may be annealed, such that the upper surfaces of the well layer 30 and the ring layer 31 may together constitute the upper surface of the drift layer 10.
In this way, the trench portion 40 arrangement at the second semiconductor device type region 1012 can be eliminated, the effective area of the PN junction of the second semiconductor device type region 1012 can be increased, and the forward conduction voltage drop of the second semiconductor device type region 1012 can be reduced.
And, since the implantation dose and the annealing time of the ring layer 31 are larger than those of the well layer 30, the junction depth and the doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be ensured to be the same, the voltage withstanding capability of the semiconductor apparatus 100 can be ensured by adopting the mode of the first ring layer 31 implantation and the second well layer 30 implantation.
As shown in fig. 3, after the step of implanting the well layer 30 of the second conductivity type in the drift layer 10 and annealing the well layer 30, in which the well layer 30 is located at both sides of the ring layer 31, the manufacturing method of the semiconductor device 100 may further include: injecting a second emitter layer 32 into the drift layer 10; a dielectric layer 33 is provided on the upper surface of the oxide insulating layer 41; a first contact hole 331 is formed between two adjacent trench portions 40 corresponding to the dielectric layer 33, and a second contact hole 332 is formed at a portion of the dielectric layer 33 corresponding to the well layer 30 located in the middle of the ring layer 31, where the length of the second contact hole 332 in the first direction is greater than the length of the first contact hole 331 in the first direction.
Specifically, after the well layer 30 of the second conductivity type is implanted in the drift layer 10 and the well layer 30 is annealed, the second emitter layer 32 may be implanted to both sides of the trench portion 40 in the drift layer 10, then the dielectric layer 33 is disposed on the surface of the oxide insulating layer 41, the dielectric layer 33 covers the well layer 30, the ring layer 31, the second emitter layer 32 and the oxide insulating layer 41, and then the first contact hole 331 and the second contact hole 332 are correspondingly opened on the dielectric layer 33, wherein the first contact hole 331 corresponds to a region between two adjacent trench portions 40, that is: the second emitter layer 32 may be exposed through the first contact hole 331, and the second contact hole 332 may correspond to a portion of the well layer 30 located in the middle of the ring layer 31, that is: the corresponding well layer 30 under the second semiconductor device type region 1012 may be exposed through the second contact hole 332.
It will be appreciated that the width of the well layer 30 corresponding to the second semiconductor device type region 1012 is much greater than the width between two adjacent trench portions 40, so: the length of the second contact hole 332 in the first direction is much longer than the length of the first contact hole 331 in the first direction.
Further, as shown in fig. 3, after the step of forming the first contact hole 331 in the dielectric layer 33 between the two adjacent trench portions 40, and forming the second contact hole 332 in the dielectric layer 33 corresponding to the portion of the well layer 30 located in the middle of the ring layer 31, the method for manufacturing the semiconductor device 100 may further include: a barrier metal layer 34 is arranged on the upper surface of the dielectric layer 33, the side walls of the dielectric layer 33 corresponding to the first contact hole 331 and the second contact hole 332, and the upper surfaces of the ring layer 31 and the well layer 30; the barrier metal layer 34 is etched to form a third contact hole 341 corresponding to the second contact hole 332 and portions of the opposite sidewalls of the trench 40 on both sides of the second contact hole 332.
Specifically, after the first contact hole 331 is formed between the dielectric layer 33 corresponding to two adjacent trench portions 40, and the second contact hole 332 is formed in the dielectric layer 33 corresponding to the portion of the well layer 30 located in the middle of the ring layer 31, the barrier metal layer 34 may be disposed on the upper surface of the dielectric layer 33, the sidewalls of the dielectric layer 33 corresponding to the first contact hole 331 and the second contact hole 332, and the upper surfaces of the ring layer 31 and the well layer 30, and portions of the second contact hole 332 and the opposite sidewalls of the trench portions 40 on both sides of the second contact hole 332 may be etched, so that the third contact hole 341 may be etched.
On the one hand, the barrier metal layer 34 of the first semiconductor device type region 1011 still exists, so that the barrier metal layer 34 can be in contact with the second emitter layer 32, the later-stage emitter metal layer 35 and the second emitter layer 32 can be conveniently and electrically connected, and the normal operation of the first semiconductor device type region 1011 is ensured, on the other hand, the barrier metal layer 34 of the second semiconductor device type region 1012 can be omitted, the later-stage emitter metal layer 35 can be conveniently and directly and electrically connected with the well layer 30 of the second semiconductor device type region 1012, and the conduction voltage drop of the second semiconductor device type region 1012 can be reduced.
As shown in fig. 3, after etching the portions of the barrier metal layer 34 corresponding to the second contact hole 332 and the opposite sidewalls of the trench portion 40 on both sides of the second contact hole 332 to etch the third contact hole 341, the method for manufacturing the semiconductor device 100 may further include: an emitter metal layer 35 is arranged on the upper surface of the barrier metal layer 34, at least part of the emitter metal layer 35 penetrates through the first contact hole 331 and is electrically connected with the second emitter layer 32, and at least part of the emitter metal layer 35 penetrates through the third contact hole 341 and the second contact hole 332 and is electrically connected with the part of the well layer 30 located in the middle of the ring layer 31; a field stop layer 20 is provided on the lower surface of the drift layer 10; a collector layer 21 of the second conductivity type is provided on the lower surface of the field stop layer 20; a first emitter layer 22 is provided at a position of the collector layer 21 corresponding to the middle of the ring layer 31; a collector metal layer 23 is provided on the lower surface of the collector layer 21.
Specifically, after the barrier metal layer 34 is etched corresponding to the second contact hole 332 and portions of opposite sidewalls of the trench 40 on both sides of the second contact hole 332 to etch the third contact hole 341, an emitter metal layer 35 may be disposed on the upper surface of the barrier metal layer 34, such that at least a portion of the emitter metal layer 35 penetrates through the first contact hole 331 to contact the second emitter layer 32, and at least a portion of the emitter metal layer 35 may penetrate through the third contact hole 341 and the second contact hole 332 to communicate with the well layer 30, then a field stop layer 20 is disposed on the lower surface of the drift layer 10, and further, a collector layer 21 of the second conductivity type is disposed on the lower surface of the field stop layer 20, a first emitter layer 22 is disposed at a position corresponding to the middle of the ring layer 31 of the collector layer 21, and finally, a collector metal layer 23 is disposed on the lower surfaces of the collector layer 21 and the first emitter layer 22, and the collector metal layer 23 is electrically connected to the collector layer 21 and the first emitter layer 22.
Thus, the semiconductor device 100 can be manufactured such that the semiconductor device 100 includes the first semiconductor device type region 1011 and the second semiconductor device type region 1012, and such that the semiconductor device 100 has a low on-voltage drop, and such that the semiconductor device 100 has a better voltage withstand capability.
The method of fabricating the semiconductor device 100 is described below by way of example with reference to fig. 2 and fig. 4-10, the semiconductor device 100 being an RC-IGBT:
as shown in fig. 4, an N-substrate material is provided as the drift layer 10. Forming structure 1.
As shown in fig. 5, a P-type halo layer 31 implant and anneal is performed on the basis of structure 1. Forming structure 2.
As shown in fig. 6, on the basis of the structure 2, a trench portion 40 is etched, and an oxide insulating layer 41 and a deposited polysilicon 42 are sequentially grown in the trench portion 40, and then the polysilicon 42 is etched. Forming structure 3.
As shown in fig. 7, a P-type well layer 30 implant and anneal is performed on the basis of structure 3. Forming structure 4.
As shown in fig. 8, on the basis of structure 4, an n+ second emitter layer 32 implant and anneal is performed, and then a dielectric layer 33 is deposited thereon. Forming structure 5.
As shown in fig. 9, on the basis of the structure 5, a first contact hole 331 and a second contact hole 332 are etched on the dielectric layer 33, and then a Ti or TiN barrier metal layer 34 is deposited on the dielectric layer 33. Forming structure 6.
As shown in fig. 10, on the basis of the structure 6, a third contact hole 341 is etched on the barrier metal layer 34, ensuring that the FRD region has no barrier metal layer 34. Forming structure 7.
As shown in fig. 2, on the basis of the structure 7, an emitter metal layer 35 is prepared by metal sputtering, and then a collector metal layer 23 is prepared by n+ field stop layer 20 implantation, p+ collector layer 21 implantation, FRD region n+ first emitter layer 22 implantation, laser annealing, and metal sputtering in this order. The semiconductor device 100 is finally formed.
It should be noted that other structures and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a drift layer (10) of a first conductivity type;
a field stop layer (20) of a first conductivity type, the field stop layer (20) being provided on a lower surface of the drift layer (10);
a collector layer (21) of a second conductivity type, the collector layer (21) being provided on a lower surface of the field stop layer (20);
a first emitter layer (22) of a first conductivity type, the first emitter layer (22) being disposed on a lower surface of the field stop layer (20), the collector layer (21) being circumferentially disposed around an outer side of the first emitter layer (22);
a ring layer (31) of a second conductivity type, the ring layer (31) being disposed within the drift layer (10), an upper surface of the ring layer (31) constituting at least a portion of an upper surface of the drift layer (10), the ring layer (31) corresponding to a junction between the collector layer (21) and the first emitter layer (22), a plurality of trench portions (40) being disposed within the ring layer (31);
a well layer (30) of a second conductivity type, the well layer (30) is disposed in the drift layer (10), an upper surface of the well layer (30) forms at least part of an upper surface of the drift layer (10), the well layer (30) is disposed on both sides of the ring layer (31) and at least partially corresponds to the collector layer (21) and the first emitter layer (22), and a plurality of trench portions (40) are disposed on a portion of the well layer (30) corresponding to the collector layer (21).
2. The semiconductor device according to claim 1, wherein a depth in an up-down direction of the well layer (30) is smaller than a depth in an up-down direction of the ring layer (31).
3. The semiconductor device according to claim 2, wherein a depth of the trench portion (40) in an up-down direction is larger than a depth of the well layer (30) in an up-down direction, and a depth of the trench portion (40) in the up-down direction is smaller than a depth of the ring layer (31) in the up-down direction.
4. The semiconductor device according to claim 2, wherein a cross section in an up-down direction of the ring layer (31) is arc-shaped, and a cross section in an up-down direction of the well layer (30) is rectangular.
5. The semiconductor device according to claim 1, wherein second emitter layers (32) are disposed on both sides of the trench portions (40), dielectric layers (33) are disposed on upper surfaces of the ring layers (31) and the well layers (30), first contact holes (331) are disposed between the two adjacent trench portions (40) corresponding to the dielectric layers (33), second contact holes (332) are disposed on portions of the dielectric layers (33) corresponding to the first emitter layers (22), emitter metal layers (35) are disposed on upper surfaces of the dielectric layers (33), at least portions of the emitter metal layers (35) penetrate through the first contact holes (331) and are electrically connected with the second emitter layers (32), at least portions of the emitter metal layers (35) penetrate through the second contact holes (332) and are electrically connected with portions of the well layers (30) located in the middle of the ring layers (31), and a plurality of the trench portions (40) are disposed at intervals in a first direction and have a length larger than the first contact holes (331) in the first direction.
6. The semiconductor device according to claim 5, wherein a barrier metal layer (34) is disposed on the surface of the dielectric layer (33), the barrier metal layer (34) is located between the dielectric layer (33) and the emitter metal layer (35), a third contact hole (341) is formed in a portion of the barrier metal layer (34) corresponding to the second contact hole (332), and at least a portion of the emitter metal layer (35) penetrates through the third contact hole (341) and the second contact hole (332) and is electrically connected to a portion of the well layer (30) located in the middle of the ring layer (31).
7. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to any one of claims 1 to 6, comprising:
preparing a drift layer (10);
-implanting a ring layer (31) of a second conductivity type in the drift layer (10), and annealing the ring layer (31);
etching a trench portion (40) in the drift layer (10), and providing an oxide insulating layer (41) on the upper surface of the drift layer (10);
a well layer (30) of a second conductivity type is implanted in the drift layer (10), and the well layer (30) is annealed, wherein the well layer (30) is located on both sides of the ring layer (31).
8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of implanting a well layer (30) of a second conductivity type in the drift layer (10) and annealing the well layer (30), wherein the well layer (30) is located on both sides of the ring layer (31), further comprises:
injecting a second emitter layer (32) into the drift layer (10);
a dielectric layer (33) is arranged on the upper surface of the oxidation insulating layer (41);
a first contact hole (331) is formed in the dielectric layer (33) between two adjacent corresponding groove parts (40), and a second contact hole (332) is formed in the dielectric layer (33) corresponding to the part of the well layer (30) located in the middle of the ring layer (31), wherein the length of the second contact hole (332) in the first direction is greater than that of the first contact hole (331).
9. The method of manufacturing a semiconductor device according to claim 8, wherein a first contact hole (331) is formed in the dielectric layer (33) between two adjacent trench portions (40), and a second contact hole (332) is formed in a portion of the dielectric layer (33) located in the middle of the ring layer (31) corresponding to the well layer (30), wherein a length of the second contact hole (332) in a first direction is longer than a length of the first contact hole (331), and further comprising:
a barrier metal layer (34) is arranged on the upper surface of the dielectric layer (33), the side walls of the dielectric layer (33) corresponding to the first contact hole (331) and the second contact hole (332), and the upper surfaces of the ring layer (31) and the well layer (30);
and etching parts of the barrier metal layer (34) corresponding to the second contact hole (332) and the two opposite side walls of the groove part (40) at two sides of the second contact hole (332) so as to etch a third contact hole (341).
10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of etching portions of the barrier metal layer (34) corresponding to the second contact hole (332) and opposite side walls of the trench portion (40) on both sides of the second contact hole (332) to etch the third contact hole (341) further comprises:
an emitter metal layer (35) is arranged on the upper surface of the barrier metal layer (34), at least part of the emitter metal layer (35) penetrates through the first contact hole (331) and is electrically connected with the second emitter layer (32), and at least part of the emitter metal layer (35) penetrates through the third contact hole (341) and the second contact hole (332) and is electrically connected with the part of the well layer (30) located in the middle of the ring layer (31);
a field stop layer (20) is provided on the lower surface of the drift layer (10);
a collector layer (21) of a second conductivity type is provided on the lower surface of the field stop layer (20);
a first emitter layer (22) is arranged at a position of the collector layer (21) corresponding to the middle of the ring layer (31);
a collector metal layer (23) is provided on the lower surface of the collector layer (21).
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