CN112086507A - SiC MOSFET device cell and manufacturing method thereof - Google Patents
SiC MOSFET device cell and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000005684 electric field Effects 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims description 112
- 229910052751 metal Inorganic materials 0.000 claims description 112
- 239000004065 semiconductor Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 21
- 210000000746 body region Anatomy 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 150000002739 metals Chemical class 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 230000036961 partial effect Effects 0.000 claims description 2
- 230000002441 reversible effect Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000011084 recovery Methods 0.000 abstract description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 230000002829 reductive effect Effects 0.000 description 6
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Abstract
The invention discloses a SiC MOSFET device unit cell and a manufacturing method thereof, and provides a technical scheme of a buried electric field shielding region directly grounded aiming at the defects that the chip area is limited and the dynamic loss is increased due to poor grounding effect of an electric field shielding region at the bottom of a grooved gate SiC MOSFET grooved gate, the conduction voltage drop of a body diode is large, and the reverse recovery charge is large. The invention can more effectively form electric field protection on the groove gate oxide layer and realize low reverse conduction voltage drop by integrating the low-leakage anti-parallel Schottky diode.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, relates to a high-voltage semiconductor device, and particularly relates to a SiC MOSFET device cell and a manufacturing method thereof.
Background
SiC devices are three generations of semiconductor devices, and their inherent physical properties make them very suitable for applications such as high frequency and high power. The critical breakdown electric field is about 3e 6V/cm, so that the electric field of the trench gate oxide is too high when the trench gate oxide is in voltage resistance, and the reliability of the gate oxide is seriously insufficient. Therefore, in the design of the SiC MOSFET device unit cell, the electric field protection of the channel oxide layer must be considered, and the reliability problem caused by the long-term exposure of the gate oxide layer to the strong electric field is avoided. Currently, the most common and effective method is to provide a grounded P-type electric field shielding region at the bottom of the trench gate. Generally, the electric field shielding region is grounded through a junction terminal, and the distance from the cell region to the terminal region increases as the chip current increases, so that the distributed resistance of the long-distance P-type electric field shielding region increases, which leads to a deterioration in grounding effect, and finally leads to an increase in MOSFET dynamic resistance and an increase in dynamic loss. Therefore, this scheme will limit the single chip current magnitude.
In addition, the intrinsic conduction voltage drop of the anti-parallel PN junction freewheeling diode integrated with the MOSFET manufactured by the silicon carbide material is about 3V due to the large forbidden bandwidth of the silicon carbide material, and the conduction loss of the silicon carbide material is too high. Therefore, the Schottky Barrier Diode with low turn-on voltage drop is integrated in the same chip: SBD is an important development direction for SiC MOSFET device cells. Generally, the SBD needs to provide an additional P-type electric field shielding region to protect the schottky junction to prevent the leakage current from sharply increasing due to the barrier lowering. The extra electric field protection occupies the channel area, so that the channel density is reduced and the device resistance is increased.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a SiC MOSFET device unit cell and a manufacturing method thereof. The invention integrates the anti-parallel Schottky diode with low conduction voltage drop and low leakage current under the condition of realizing the maximum channel density, and forms excellent electric field protection for the gate oxide and the Schottky junction.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a SiC MOSFET device cell, comprising: the device comprises a first main surface and a second main surface of a semiconductor, an N-voltage-withstanding layer arranged between the first main surface and the second main surface, an N-type buffer layer, a heavily doped N-type substrate, two P-type electric field shielding layers, an N-type layer, an N-type epitaxial layer, a gate oxide layer, a polysilicon gate, a metal gate electrode, two P-type body regions, two N + source regions, two Schottky metal regions, two source metals arranged on the first main surface and a drain metal arranged on the second main surface;
the heavily doped N-type substrate is fixedly connected with the second main surface; the N-type buffer layer is positioned on the upper surface of the heavily doped N-type substrate; the pressure-resistant layer is positioned on the upper surface of the N-type buffer layer; the two P-type electric field shielding regions are respectively positioned on the partial upper surface of the voltage-resistant layer; the N-type layer is positioned between the two P-type electric field shielding regions; the N-type epitaxial layer is arranged on the P-type electric field shielding region and the upper surface of the N-type layer; a groove is arranged from the first main surface to the N-type epitaxial layer in the semiconductor and used for manufacturing a groove gate; the groove is not in contact with the P-type electric field shielding layer and the N-type layer; the groove is formed by a groove wall gate oxide layer and a heavily doped polysilicon gate filled in the groove; a P-type body region is respectively arranged in the semiconductor outside the groove walls on the two sides of the groove; the two P-type body regions are positioned on the upper surface of the N-type epitaxial layer and are in contact with the groove wall; two N + source regions are respectively arranged between the upper surfaces of the two P-type body regions and the first main surface; the two N + source regions are in contact with the groove wall, and each N + source region is covered with a source metal; a metal gate electrode covers the polysilicon gate; each of the Schottky metal regions is in contact with a source metal;
the two Schottky metal regions are respectively positioned on two sides of the groove and penetrate into the semiconductor body from the first main surface, penetrate into the semiconductor body by a distance larger than the distance from the groove bottom to the first main surface, and are respectively contacted with an N + source region, a P-type body region, an N-type epitaxial layer, an N-type layer and a P-type electric field shielding layer on two sides of the groove; an N-type Schottky contact, namely a Schottky junction interface, is formed at the interface of each Schottky metal region and the N-type epitaxial layer;
the two P-type electric field shielding regions are respectively positioned at two sides of a central line perpendicular to the first main surface at the center of the groove and extend a distance w from Schottky junction interfaces at two sides of the groove to the central direction of the grooveThe doping concentration is 1 x 1018cm-3Above, wherein, the distance w>0.5um；
And the doping concentrations of the N-type region and the N-type epitaxial layer are both greater than the doping concentration of the N-voltage-resistant layer.
The source metal and the Schottky metal region can be a single metal material or a plurality of layers of metals; the source metal and schottky metal regions may be the same metal material.
A manufacturing method of SiC MOSFET device unit cells comprises the following steps:
a1, injecting ions into an N-type layer and two P-type electric field shielding regions which are mutually contacted on the surface of the N-voltage-resistant layer, and epitaxially growing an N-type epitaxial layer and two P-type body regions on the N-voltage-resistant layer;
a2, implanting ions, etching, annealing at high temperature, growing gate oxide and depositing polysilicon on the first main surface of the semiconductor in the step A1 to obtain a primary MOS tube;
a3, for a preliminary MOS tube, if two Schottky metal regions and two source metals are made of the same material, depositing a source metal region, photoetching, and etching the source metal region to obtain two source metals and a metal gate electrode; if the two materials are different, depositing a Schottky metal region, etching the metal outside the groove where the two Schottky metal regions are located, depositing a source metal region, photoetching, and etching the source metal region to obtain two source metals and a metal gate electrode;
a4, growing a passivation layer on the surface of the MOS tube obtained in the step A3 by adopting CVD, and depositing metal on the second main surface to obtain drain metal;
and A5, annealing the MOS tube obtained in the step A4 to obtain ohmic contact, and finishing the manufacture of the SiC MOSFET device unit cell.
Further, the step a2 includes the following sub-steps:
a21, photoetching two windows of N + source regions, and forming N-type heavy doping by ion implantation to obtain two N + source regions;
a22, covering the MOS tube obtained in the step A21 with a protective carbon film, and then annealing the MOS tube at a high temperature of 1600-1800 ℃ to activate impurities and remove the carbon film;
a23, taking deposited metal Ni or a dielectric layer of the MOS tube with the carbon film removed as a hard mask layer, and photoetching a groove and positions of two Schottky metal regions; etching the two Schottky metal regions and the hard mask layer at the groove position by adopting ICP or RIE, and continuously etching by adopting ICP or RIE to etch the semiconductors at the two Schottky metal regions and the groove position to the depth required by the groove;
a24, reserving the hard mask layer in A23, coating photoresist, and exposing the positions of two Schottky metal regions; etching is continuously performed in a self-aligning mode by utilizing the hard mask layer in the A23 until the depth of the two Schottky metal regions reaches the two P-type electric field shielding regions below the two Schottky metal regions; removing the photoresist and the mask layer;
a25, growing a gate oxide layer on the wall and bottom of the etched groove by thermal oxidation or CVD deposition; and depositing a polysilicon gate, and etching off the polysilicon in the region outside the groove after photoetching to obtain a primary MOS tube.
The invention has the beneficial effects that:
1. the bottom of the groove gate where the groove is located is not directly provided with a P-type electric field shielding region, so that the electric field shielding region under the groove gate is prevented from being grounded (namely connected with a source electrode) by additional process steps in the traditional structure; the invention carries out electric field protection by extending the P-type electric field shielding regions at two sides to the direction of the groove grid; the P-type electric field shielding regions on both sides form an electrical connection to ground by penetrating into the Schottky metal region of the semiconductor
2. The Schottky metal region is in Schottky contact with the N-type epitaxial layer above the electric field shielding region when penetrating into the semiconductor connection electric field shielding region, and the distance w between the P-type electric field shielding region and the Schottky interface is greater than 0.5um, so that very strong electric field protection is formed on a Schottky junction, and the electric leakage is very small; the Schottky diode is adopted to replace a body diode for reverse conduction, so that reverse conduction voltage drop and reverse recovery charge can be greatly reduced.
3. The width of the N-type region under the groove gate can be flexibly adjusted by adjusting the distance between the two P-type electric field shielding regions, and the closer the distance is, the stronger the electric field protection on the groove oxide layer and the Schottky junction is; the smaller the electric field concentration effect at the edge of the P-type electric field shielding region is, the higher the breakdown voltage is; meanwhile, the JFET resistance introduced by the N-type region and the N-type epitaxial layer can be reduced by adjusting the concentration of the N-type region and the N-type epitaxial layer, so that the minimum specific on-resistance is obtained.
Drawings
Fig. 1 is a schematic view of a SiC MOSFET device cell in two dimensions of example 1;
fig. 2 is a flowchart of a manufacturing method of a SiC MOSFET device cell for embodiment 1;
FIG. 3 is a comparison of the electric field distribution of the oxide layer of Rohm company for a conventional doubtrenchMOSFET and example 1 at one design parameter for the same cell size;
wherein, 1, a pressure resistance layer; 2. an N-type buffer layer; 3. heavily doping the N-type substrate; 4. a drain metal; 5. a P-type electric field shielding region; 6. a Schottky metal region; 7. an N-type region; 8. an N-type epitaxial layer; 9. a gate metal; 10. an N + source region; 11. a P-type body region; 12. heavily doping the polysilicon; 13. a gate oxide layer; 14. and a source metal.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
In the description of the present invention, it is to be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", "left", "right", and the like, indicate orientations or positional relationships based on those shown in the drawings, are used merely to facilitate the description of the present invention and to simplify the description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or an implicit indication of the number of technical features. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or more of the features.
Example 1, an example of the present invention is shown in fig. 1: a SiC MOSFET device cell, comprising: the semiconductor structure comprises a semiconductor first main surface (the front surface of the semiconductor in figure 1) and a semiconductor second main surface (the back surface of the semiconductor in figure 1), an N-voltage-withstanding layer 1 arranged between the first main surface and the second main surface, an N-type buffer layer 2, a heavily-doped N-type substrate 3, two P-type electric field shielding layers 5, an N-type layer 7, an N-type epitaxial layer 8, a gate oxide layer 13, a polysilicon gate 12, a metal gate electrode 9, two P-type body regions 11, two N + source regions 10, two Schottky metal regions 6, two source metals 14 arranged on the first main surface and a drain metal 4 arranged on the second main surface;
the heavily doped N-type substrate 3 is fixedly connected with the second main surface; the N-type buffer layer 2 is positioned on the upper surface of the heavily doped N-type substrate 3; the voltage-resistant layer 1 is positioned on the upper surface of the N-type buffer layer 2; the two P-type electric field shielding regions 5 are respectively positioned on the upper surface of part of the voltage-resistant layer 1; the N-type layer 7 is positioned between the two P-type electric field shielding regions 5; the N-type epitaxial layer 8 is arranged on the upper surfaces of the P-type electric field shielding region 5 and the N-type layer 7; a groove is arranged from the first main surface to the N-type epitaxial layer 8 in the semiconductor, and the groove is not in contact with the P-type electric field shielding layer 5 and the N-type layer 7; the groove is composed of a groove wall gate oxide layer 13 and a groove inner filling heavily doped polysilicon gate 12; a P-type body region 11 is respectively arranged in the semiconductor outside the two side groove walls of the groove; the two P type body regions 11 are positioned on the upper surface of the N type epitaxial layer 8 and are in contact with the groove wall; two N + source regions 10 are respectively arranged between the upper surfaces and the first main surface of the two P-type body regions 11; the two N + source regions 10 are in contact with the trench wall, and each N + source region 10 is covered with a source metal 14; the polysilicon gate 12 is covered with a metal gate electrode 9; each of the schottky-metal regions 6 is in contact with one source metal 14;
the two Schottky metal regions 6 are respectively positioned at two sides of the groove and penetrate into the semiconductor body from the first main surface, penetrate into the semiconductor body by a distance larger than the distance from the groove bottom to the first main surface, and are respectively contacted with an N + source region 10, a P-type body region 11, an N-type epitaxial layer 8, an N-type layer 7 and a P-type electric field shielding layer 5 at two sides of the groove; an N-type Schottky contact, namely a Schottky junction interface, is formed at the contact interface of each Schottky metal region 6 and the N-type epitaxial layer 8;
the two P-type electric field shielding regions 5 are respectively positioned at two sides of a central line perpendicular to the first main surface at the center of the groove, extend a distance w from Schottky junction interfaces at two sides of the groove to the central direction of the groove, and have doping concentration of 1 × 1018cm-3Above, wherein, the distance w>0.5um；
The doping concentration of the N-type region 7 and the doping concentration of the N-type epitaxial layer 8 are both greater than the doping concentration of the N-voltage-withstanding layer 1.
The source metal 14 and the schottky metal region 6 may be a single metal material or may be a plurality of layers of metals; the source metal 14 and the schottky metal region 6 may be the same metal material.
As shown in fig. 2, a method for manufacturing a SiC MOSFET device cell includes the steps of:
a1, implanting ions into an N-type layer 7 and two P-type electric field shielding regions 5 which are mutually contacted on the surface of the N-voltage-resistant layer 1, and epitaxially growing an N-type epitaxial layer 8 and two P-type body regions 11 on the N-voltage-resistant layer 1;
a2, implanting ions, etching, annealing at high temperature, growing gate oxide and depositing polysilicon on the first main surface of the semiconductor in the step A1 to obtain a primary MOS tube;
a3, for the preliminary MOS transistor, if the two Schottky metal regions 6 and the two source metals 14 are made of the same material, depositing a source metal region, photoetching, and etching the source metal region to obtain the two source metals 14 and a metal gate electrode 9; if the two materials are different, depositing a Schottky metal region, etching the metal outside the groove where the two Schottky metal regions 6 are located, depositing a source metal region, photoetching, and etching the source metal region to obtain two source metals 14 and a metal gate electrode 9;
a4, growing a passivation layer on the surface of the MOS tube obtained in the step A3 by adopting CVD, and depositing metal on the second main surface to obtain drain metal 4;
and A5, annealing the MOS tube obtained in the step A4 to obtain ohmic contact, and finishing the manufacture of the SiC MOSFET device unit cell.
The step A2 comprises the following sub-steps:
a21, firstly, photoetching two windows of the N + source region 10, and forming N-type heavy doping by adopting ion implantation to obtain two N + source regions 10;
a22, covering the MOS tube obtained in the step A21 with a protective carbon film, and then annealing the MOS tube at a high temperature of 1600-1800 ℃ to activate impurities and remove the carbon film;
a23, taking deposited metal Ni or a dielectric layer of the MOS tube with the carbon film removed as a hard mask layer, and photoetching a groove and the positions of two Schottky metal regions 6; etching off the two Schottky metal regions 6 and the hard mask layer at the groove position by adopting ICP or RIE, and continuously etching by adopting ICP or RIE to etch the semiconductors at the positions of the two Schottky metal regions 6 and the groove position to the depth required by the groove;
a24, reserving the hard mask layer in A23, coating photoresist, and exposing the positions of two Schottky metal regions 6; etching is continued by utilizing the hard mask layer in A23 in a self-alignment manner until the depth of the two Schottky metal regions 6 reaches the two P-type electric field shielding regions 5 below the two Schottky metal regions respectively; removing the photoresist and the mask layer;
a25, growing a gate oxide layer 13 on the wall and bottom of the etched groove by thermal oxidation or CVD deposition; and depositing a polysilicon gate 12, and etching away polysilicon in the region outside the groove after photoetching to obtain a primary MOS tube.
Fig. 3 compares the electric field distribution of a conventional structure, which is a doubtretrenchmosfet from rowm, and of the present invention, which has the same voltage-resistant region 1 and the same cell width of 2.4um, according to example 1. Voltage-proof region 1 doped with 1e16 cm-3Length 7.5um, channel mobility all setIs 30cm2Vs, channel length 0.5um, P-type body region 11 doped 2e17 cm-3The gate oxide layer 13 is 50nm thick. N-type region 7 and N-type epitaxial layer 8 are both doped 1.2e17 cm-3The P-type electric field shielding region 5 extends by a distance w of 0.55 um. The simulation result is as follows: the traditional structure has breakdown voltage BV of 1156V and specific on-resistance Ron,sp＝1.27mΩ·cm2BV 1218V, specific on-resistance Ron,sp＝1.25mΩ·cm2. The breakdown voltage of the invention is improved by 5.3% under almost the same specific on-resistance. More importantly, the Schottky diode with the conduction voltage drop of about 1.5V is integrated, the reverse conduction voltage drop of the conventional structure is about 3V and is reduced by about 50%, and the reverse recovery charge is greatly reduced due to the unipolar conduction of the Schottky. Meanwhile, as can be seen from fig. 3, the maximum electric field E of the gate oxide layer 13 of the present inventionox_maxCompared with the traditional structure, the grid voltage is reduced by 45.9 percent and is lower than the critical electric field 3MV/cm required by reliability, and the invention is proved to have higher grid voltage reliability.
Claims (3)
1. A SiC MOSFET device cell, comprising: the transistor comprises a first main surface, a second main surface, an N-voltage-withstanding layer (1) arranged between the first main surface and the second main surface, an N-type buffer layer (2), a heavily-doped N-type substrate (3), two P-type electric field shielding layers (5), an N-type layer (7), an N-type epitaxial layer (8), a gate oxide layer (13), a polysilicon gate (12), a metal gate electrode (9), two P-type body regions (11), two N + source regions (10), two Schottky metal regions (6), two source metals (14) arranged on the first main surface and a drain metal (4) arranged on the second main surface;
the heavily doped N-type substrate (3) is fixedly connected with the second main surface; the N-type buffer layer (2) is positioned on the upper surface of the heavily doped N-type substrate (3); the pressure-resistant layer (1) is positioned on the upper surface of the N-type buffer layer (2); the two P-type electric field shielding regions (5) are respectively positioned on the partial upper surface of the pressure-resistant layer (1); the N-type layer (7) is positioned between the two P-type electric field shielding regions (5); the N-type epitaxial layer (8) is arranged on the upper surfaces of the P-type electric field shielding region (5) and the N-type layer (7); a groove is arranged from the first main surface to an N-type epitaxial layer (8) in the semiconductor and is used for manufacturing a groove gate; the groove is not in contact with the P-type electric field shielding layer (5) and the N-type layer (7); the groove is composed of a groove wall gate oxide layer (13) and a groove inner filling heavily doped polysilicon gate (12); a P-type body region (11) is respectively arranged in the semiconductor outside the groove walls on the two sides of the groove; the two P-type body regions (11) are positioned on the upper surface of the N-type epitaxial layer (8) and are in contact with the groove wall; two N + source regions (10) are respectively arranged between the upper surfaces and the first main surface of the two P-type body regions (11); the two N + source regions (10) are in contact with the groove wall, and each N + source region (10) is covered with a source metal (14); the polysilicon gate (12) is covered with a metal gate electrode (9); each of said schottky-metal regions (6) being in contact with a source metal (14);
the two Schottky metal regions (6) are respectively positioned at two sides of the groove and penetrate into the semiconductor body from the first main surface, penetrate into the semiconductor body by a distance larger than the distance from the groove bottom to the first main surface, and are respectively contacted with an N + source region (10), a P-type body region (11), an N-type epitaxial layer (8), an N-type layer (7) and a P-type electric field shielding layer (5) at two sides of the groove; an N-type Schottky contact, namely a Schottky junction interface, is formed at the contact interface of each Schottky metal region (6) and the N-type epitaxial layer (8);
the two P-type electric field shielding regions (5) are respectively positioned at two sides of a central line perpendicular to the first main surface of the center of the groove, extend a distance of w from Schottky junction interfaces at two sides of the groove to the central direction of the groove, and have doping concentration of 1 × 1018cm-3Above, wherein, the distance w>0.5um；
The doping concentration of the N-type region (7) and the doping concentration of the N-type epitaxial layer (8) are both greater than that of the N-voltage-resistant layer (1).
2. A method for manufacturing a SiC MOSFET device unit cell is characterized by comprising the following steps:
a1, implanting ions into an N-type layer (7) and two P-type electric field shielding regions (5) which are mutually contacted on the surface of the N-voltage-resistant layer (1), and epitaxially growing an N-type epitaxial layer (8) and two P-type body regions (11) on the N-voltage-resistant layer (1);
a2, implanting ions, etching, annealing at high temperature, growing gate oxide and depositing polysilicon on the first main surface of the semiconductor in the step A1 to obtain a primary MOS tube;
a3, for a preliminary MOS transistor, if two Schottky metal regions (6) and two source metals (14) are made of the same material, depositing a source metal region, photoetching, and etching the source metal region to obtain two source metals (14) and a metal gate electrode (9); if the two materials are different, depositing a Schottky metal region, etching the metal outside the groove where the two Schottky metal regions (6) are located, depositing a source metal region, photoetching, and etching the source metal region to obtain two source metals (14) and a metal gate electrode (9);
a4, growing a passivation layer on the surface of the MOS tube obtained in the step A3 by adopting CVD, and depositing metal on the second main surface to obtain drain metal (4);
and A5, annealing the MOS tube obtained in the step A4 to obtain ohmic contact, and finishing the manufacture of the SiC MOSFET device unit cell.
3. The method of claim 2, wherein the step a2 includes the sub-steps of:
a21, firstly, photoetching two windows of the N + source region (10), and forming N-type heavy doping by adopting ion implantation to obtain two N + source regions (10);
a22, covering the MOS tube obtained in the step A21 with a protective carbon film, and then annealing the MOS tube at a high temperature of 1600-1800 ℃ to activate impurities and remove the carbon film;
a23, taking deposited metal Ni or a dielectric layer of the MOS tube with the carbon film removed as a hard mask layer, and photoetching a groove and the positions of two Schottky metal regions (6); etching the two Schottky metal regions (6) and the hard mask layer at the groove position by adopting ICP or RIE, and continuously etching by adopting ICP or RIE to etch the semiconductors at the positions of the two Schottky metal regions (6) and the groove to the depth required by the groove;
a24, reserving the hard mask layer in A23, coating photoresist, and exposing the positions of two Schottky metal regions (6); etching is continuously carried out in a self-alignment mode by utilizing the hard mask layer in the A23 until the depth of the two Schottky metal regions (6) reaches the two P-type electric field shielding regions (5) below the two Schottky metal regions respectively; removing the photoresist and the mask layer;
a25, growing a gate oxide layer (13) on the wall and bottom of the etched groove by thermal oxidation or CVD deposition; and depositing a polysilicon gate (12), and etching off the polysilicon in the region outside the groove after photoetching to obtain a primary MOS tube.
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