CN111863618B - Method for manufacturing semiconductor device - Google Patents
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- CN111863618B CN111863618B CN201910352525.4A CN201910352525A CN111863618B CN 111863618 B CN111863618 B CN 111863618B CN 201910352525 A CN201910352525 A CN 201910352525A CN 111863618 B CN111863618 B CN 111863618B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 266
- 238000000034 method Methods 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 294
- 239000011229 interlayer Substances 0.000 claims abstract description 91
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 78
- 229920005591 polysilicon Polymers 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 47
- 238000002347 injection Methods 0.000 claims abstract description 3
- 239000007924 injection Substances 0.000 claims abstract description 3
- 230000036961 partial effect Effects 0.000 claims description 8
- 230000002829 reductive effect Effects 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 description 15
- 238000002513 implantation Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a preparation method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a first groove in the semiconductor substrate of the non-primitive cell region, forming a gate oxide layer on the inner wall of the first groove and the semiconductor substrate of the non-primitive cell region, filling a polysilicon gate in the first groove and forming a polysilicon gate layer on the gate oxide layer and the first groove; forming a semiconductor layer on the polysilicon gate layer; performing well injection on the cell region to form a well region; forming a working structure in the cell region and forming a protection structure on the non-cell region; forming an interlayer dielectric layer, forming contact holes in the interlayer dielectric layer and on the first groove, forming a metal interconnection layer on the interlayer dielectric layer, and connecting the working structure and the protection structure through the metal interconnection layer and the contact holes. One end of the protection structure is led out by utilizing the first groove and the polycrystalline silicon gate layer, so that the condition that the surface of the semiconductor layer is damaged due to the fact that the two ends of the protection structure are interconnected on an interlayer dielectric layer above the semiconductor layer to form a metal interconnection opening area is effectively avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
A Semiconductor device generally includes a working structure and a protection structure for protecting the working structure, such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOS Transistor) which may generate static electricity during production, assembly, testing or transportation, and may damage the MOS Transistor when the static voltage is high, so that a diode is usually added as an electrostatic discharge (ESD) protection structure to be connected in parallel with the MOS Transistor to protect the MOS Transistor.
In a specific manufacturing process of a semiconductor device, field oxide is generally formed in a non-cell region of a semiconductor substrate as an isolation ring, self-aligned well implantation is performed on the semiconductor substrate using the field oxide as a mask to form a well region in the cell region, a semiconductor layer is deposited on the field oxide, the semiconductor layer is doped to form a protection structure on the non-cell region, the well region is doped to form a working structure in the cell region, and then an interlayer dielectric layer is deposited and a contact hole is formed in the interlayer dielectric layer to lead out an electrode.
In the above process, to realize the self-aligned mask well implantation, the field oxide needs to reach a certain thickness, which is set as h1, and the semiconductor layer deposited on the field oxide also has a certain thickness, which is set as h2, that is, on the semiconductor substrate, the surface of the protection structure on the non-cell region is higher than the surface of the working structure in the cell region by h1+ h2 (such as 8000A), the upper surface of the interlayer dielectric layer is flat, so that the thickness of the interlayer dielectric layer above the protective structure on the non-cell area is smaller than that of the interlayer dielectric layer above the cell area by h1+ h2, the interlayer dielectric layer above the protective structure is thinner, thus, in the subsequent processes, such as the process of forming and etching the metal layer, because the interlayer dielectric layer is easy to be lost, the protective structure is easy to be exposed outside to damage the protective structure, and the reliability of the semiconductor device is failed.
Disclosure of Invention
Therefore, a new method for manufacturing a semiconductor device is provided to solve the technical problem that an interlayer dielectric layer above a protection structure in the semiconductor device formed by the existing method for manufacturing the semiconductor device is thin.
A method for manufacturing a semiconductor device, the semiconductor device comprising a working structure and a protection structure for protecting the working structure, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a cell region and a non-cell region;
forming a first groove in the semiconductor substrate of the non-primitive cell region, forming a gate oxide layer on the inner wall of the first groove and the semiconductor substrate of the non-primitive cell region, filling a polysilicon gate in the first groove and forming a polysilicon gate layer on the gate oxide layer and the first groove;
forming a semiconductor layer with first conductivity type doping on the polycrystalline silicon grid layer of the non-cell region;
performing first conductive type well injection on the semiconductor substrate of the cell region by taking the semiconductor layer as a mask, and forming a well region in the semiconductor substrate of the cell region;
doping the well region to form a working structure in the cell region, and doping the semiconductor layer to form a protection structure on the non-cell region;
forming an interlayer dielectric layer on the working structure and the protection structure, forming contact holes in the interlayer dielectric layer and on the first groove, forming a metal interconnection layer connected with the contact holes on the interlayer dielectric layer, and connecting the working structure and the protection structure through the metal interconnection layer and the contact holes.
In one embodiment, the thickness of the gate oxide layer on the bottom wall of the first trench is smaller than the thickness of the gate oxide layer on the side wall of the first trench and the semiconductor substrate of the non-cell region.
In one embodiment, the thickness of the gate oxide layer on the bottom wall of the first trench is 70% of the thickness of the gate oxide layer on the semiconductor substrate of the side wall or the non-cell region of the first trench, and the proportion is gradually reduced as the thickness of the gate oxide layer is increased.
In one embodiment, the thickness of the polysilicon gate layer ranges from 400A to 600A.
In one embodiment, the operation structure is a VDMOS transistor, and when forming the first trench in the semiconductor substrate in the non-cell region, the method further includes:
and forming a second groove in the semiconductor substrate of the cell region, forming a gate oxide layer on the inner wall of the second groove, and filling the second groove with a polysilicon gate.
In one embodiment, the protection structure is a diode, the well region is doped to form a working structure in the cell region, and before the first conductive type well implantation is performed on the semiconductor substrate in the cell region, the method includes:
and doping the second conduction type in the well region to form a source region, and doping the second conduction type in a partial region of the semiconductor layer to form a first conduction type semiconductor structure and a second conduction type semiconductor structure which are parallel.
In one embodiment, the semiconductor layer forms a plurality of first conductivity type semiconductor structures and a plurality of second conductivity type semiconductor structures, the number of the first conductivity type semiconductor structures is different from that of the second conductivity type semiconductor structures, the first conductivity type semiconductor structures and the second conductivity type semiconductor structures are alternately arranged, and one first trench is respectively corresponding to the lower portions of the semiconductor structures at the middle position and the outermost position.
In one embodiment, forming an interlayer dielectric layer on the working structure and the protective structure, forming a contact hole in the interlayer dielectric layer and on the first trench, and forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, the working structure and the protective structure being connected through the metal interconnection layer and the contact hole, includes:
forming an interlayer dielectric layer on the source region, the second groove, the first conductive type semiconductor structure and the second conductive type semiconductor structure, forming a first contact hole on the interlayer dielectric layer above the source region and leading out a source electrode connected with the source region, forming a second contact hole on the interlayer dielectric layer above the second groove and leading out a grid electrode connected with the polysilicon gate, forming a third contact hole on the interlayer dielectric layer above the semiconductor structure at the middle position and leading out a first electrode of a diode connected with the polysilicon gate, forming a fourth contact hole on the first groove below the semiconductor structure at the outermost position and leading out a second electrode of the diode connected with the polysilicon gate, and forming a metal interconnection layer on the interlayer dielectric layer to connect the first electrode with the source electrode and connect the second electrode with the grid electrode.
In one embodiment, the doping of the second conductivity type is performed on the well region to form a source region, and the doping of the second conductivity type is performed on a partial region of the semiconductor layer to form a first conductivity type semiconductor structure and a second conductivity type semiconductor structure which are parallel to each other, including:
and forming a doping window on the well region and the semiconductor layer by sharing one mask plate, and simultaneously doping the second conductivity type in the well region and the semiconductor layer.
In one embodiment, the cell region is located at a middle position of the semiconductor substrate, and the non-cell region is located at a periphery of the semiconductor substrate and surrounds the cell region.
According to the preparation method of the semiconductor device, the first groove is formed in the semiconductor substrate of the non-cell area, the gate oxide layer is formed on the inner wall of the first groove and the semiconductor substrate of the non-cell area, the first groove is filled with the polysilicon gate, the polysilicon gate layer is formed on the gate oxide layer and the first groove, and the semiconductor layer with the first conductive type doping is formed on the polysilicon gate layer of the non-cell area, wherein the first groove isolation is adopted to replace the field oxygen isolation, the field oxygen photoetching level can be omitted, and the semiconductor layer can be connected with the first groove through the polysilicon gate layer. In the subsequent process, an interlayer dielectric layer is formed on the working structure and the protection structure, contact holes are formed in the interlayer dielectric layer and on the first groove, a metal interconnection layer connected with the contact holes is formed on the interlayer dielectric layer, and the working structure and the protection structure are connected through the metal interconnection layer and the contact holes, wherein one end of the protection structure is led out by using the first groove structure, so that the problem that the surface of a semiconductor layer is damaged due to the fact that the two ends of the protection structure are interconnected with the interlayer dielectric layer above the semiconductor layer to form a metal interconnection layer opening area is avoided, the problem that the semiconductor device fails due to the fact that the interlayer dielectric layer above the protection structure is thin is effectively solved, the process control difficulty is reduced, and the product quality is improved.
Drawings
FIGS. 1 a-1 c are schematic cross-sectional views of a semiconductor device illustrating steps associated with a method of fabricating the semiconductor device, in accordance with one embodiment;
FIG. 2 is a flowchart of a method for manufacturing a semiconductor device in another embodiment;
FIGS. 3 a-3 i are schematic cross-sectional views of a semiconductor device according to another embodiment of the method for fabricating the semiconductor device;
fig. 4 a-4 c are schematic device plan views corresponding to relevant steps of a semiconductor device manufacturing method in another embodiment.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The process steps for preparing the Semiconductor device are illustrated by taking a Vertical Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor (VDMOS Transistor, hereinafter referred to as VDMOS Transistor) connected with a diode as an example, wherein the VDMOS Transistor is a working structure, the diode is an electrostatic protection structure, and the preparation steps comprise:
step S102: a semiconductor substrate is provided, the semiconductor substrate includes a cell region and a non-cell region, and field oxide is formed on the non-cell region.
As shown in fig. 1a, the semiconductor substrate 110 includes a cell region a and a non-cell region B, and after a layer of field oxide is formed on the semiconductor substrate 110 by thermal oxidation, the field oxide in the cell region a is removed by photolithography and etching processes, and the field oxide 120 in the non-cell region B is remained.
Step S104: forming a groove in the semiconductor substrate of the cell region, forming a gate oxide layer on the inner wall of the groove, filling a polysilicon gate in the groove, and injecting a first conductive type well into the semiconductor substrate of the cell region by taking field oxygen as a mask to form a well region.
As shown in fig. 1b, a trench is formed in the semiconductor substrate 110 of the cell region by photolithography and etching processes, a gate oxide layer 111 is formed on the inner wall of the trench, a polysilicon gate 112 is filled in the trench, and self-aligned well implantation is performed on the semiconductor substrate of the cell region by using field oxide 120 as a mask, so as to form a well region 113. The field oxide 120 needs to reach a certain thickness h1 to be used as a self-aligned mask for well implantation, i.e., the thickness of the field oxide 120 is h 1.
Step S106: forming a semiconductor layer on the field oxide, and doping the semiconductor layer with a first conductivity type to form a first conductivity type semiconductor structure, doping the semiconductor layer with a second conductivity type to form a second conductivity type semiconductor structure, the first conductivity type semiconductor structure and the second conductivity type semiconductor structure forming a PN junction, doping the well region with a second conductivity type to form a source region, forming an interlayer dielectric layer on the semiconductor layer, the trench and the source region, and forming a contact hole in the interlayer dielectric layer, leading out a first pole of the diode from the first conductive type semiconductor structure through the contact hole, leading out a second pole of the diode from the second conductive type semiconductor structure, leading out a source electrode from the source region, leading out a grid electrode from the polysilicon grid, and forming a metal interconnection layer on the interlayer dielectric layer, connecting the first pole and the grid through the metal interconnection layer, and connecting the second pole and the source.
As shown in fig. 1c, a semiconductor layer is deposited on the field oxide layer 120, the semiconductor layer has a thickness h2, and the semiconductor layer is doped with the first conductivity type and the second conductivity type, so that part of the semiconductor layer has the first conductivity type and part of the semiconductor layer has the second conductivity type, i.e. the semiconductor layer is formed with a first conductivity type semiconductor structure 131 and a second conductivity type semiconductor structure 132, and the first conductivity type semiconductor structure 131 and the second conductivity type semiconductor structure 132 form a PN junction, and the PN junction is a diode. At the same time, the well region is doped with the second conductivity type to form a source region 114. An interlayer dielectric layer 140 covers the source region 114, the trench and the semiconductor layer, a contact hole 150 is formed in the interlayer dielectric layer, specifically, a first pole of a contact hole leading-out diode is formed in the interlayer dielectric layer 140 above the first conductive type semiconductor 131, a second pole of the contact hole leading-out diode is formed in the interlayer dielectric layer 140 above the second conductive type semiconductor 132, a contact hole leading-out source electrode is formed in the interlayer dielectric layer 140 above the source region 114, and a contact hole leading-out gate electrode (not shown in the figure) is formed in the interlayer dielectric layer 140 above the polysilicon gate 112. A metal interconnection layer 160 is formed on the interlayer dielectric layer 140, a first pole and a gate electrode are connected and a second pole and a source electrode are connected through the metal interconnection layer 160, and a drain electrode is formed on the back surface of the semiconductor substrate, thereby forming a VDMOS device with diode electrostatic protection.
In the semiconductor device formed by the semiconductor preparation method, the thickness of the field oxide 120 is h1, the thickness of the semiconductor layer is h2, the thickness of the interlayer dielectric layer 140 above the semiconductor layer is d1, and the thickness of the interlayer dielectric layer 140 above the source region 114 is d2, so that d2-d1 is h1+ h2, that is, the thickness of the interlayer dielectric layer above the non-cell region is thinner than that of the interlayer dielectric layer above the cell region by h1+ h2 (such as 8000A). Because the contact hole is required to be formed in the interlayer dielectric layer, the size of the contact hole is limited by the process line width, so that the thickness of the interlayer dielectric layer above the primitive cell region cannot exceed a certain value, the interlayer dielectric layer above the non-primitive cell region is thin, and particularly the interlayer dielectric layer corresponding to the position of the thickness d3 is the weakest working control point in the subsequent process. In a subsequent process such as a metal etching process, the interlayer dielectric layer is lost, and when the interlayer dielectric layer above the non-cell region is thin, the interlayer dielectric layer above the non-cell region is likely to be removed in the metal etching process to damage a protection structure below the interlayer dielectric layer, so that the semiconductor device fails.
Based on this, the present disclosure also provides another method for manufacturing a semiconductor device, which can increase the thickness of an interlayer dielectric layer above a protection structure and avoid forming a metal interconnection open region above the protection structure, as shown in fig. 2, the method includes:
in step S202, a semiconductor substrate is provided, the semiconductor substrate including a cell region and a non-cell region.
As shown in fig. 3a, a semiconductor substrate 210 is provided, the semiconductor substrate 210 including a cell region M and a non-cell region N. In one embodiment, the cell region M is located at the middle of the semiconductor substrate 210, and the non-cell region N is located at the periphery of the semiconductor substrate 210 and surrounds the cell region M.
Step S204, forming a first groove in the semiconductor substrate of the non-cell region, forming a gate oxide layer on the inner wall of the first groove and the semiconductor substrate of the non-cell region, filling a polysilicon gate in the first groove and forming a polysilicon gate layer on the gate oxide layer and the first groove.
As shown in fig. 3b, a plurality of trenches, which are referred to as first trenches 211, are formed on the semiconductor substrate 210 in the non-cell region by photolithography and etching processes, the first trenches 211 serve as isolation rings instead of field oxide structures, then a gate oxide layer 212 is formed on the inner wall of the first trenches 211 and the semiconductor substrate 210 in the non-cell region by a thermal oxidation process, a layer of polysilicon is deposited by a deposition process, the polysilicon is filled in the first trenches 211, the polysilicon is removed by an etch-back process and stays on the polysilicon to form a polysilicon gate 213 in the first trenches 211 and a polysilicon gate 214 on the gate oxide layer 212 and the first trenches 211. In one embodiment, the gate oxide thickness of the bottom wall of the first trench is less than the gate oxide thickness on the semiconductor substrate of the first trench sidewall and the non-cell region, for example, the gate oxide thickness of the bottom wall of the first trench is 70% of the gate oxide thickness on the semiconductor substrate of the first trench sidewall or the non-cell region, and the ratio gradually decreases as the gate oxide thickness increases. In one embodiment, the thickness of the polysilicon gate layer 214 ranges from 400A to 600A.
In one embodiment, as shown in fig. 3c, when forming the first trench 211, an oxide layer may be grown on the semiconductor substrate 210, the oxide layer may be made of TEOS (tetraethylorthosilicate) dielectric material, then a photoresist is coated on the oxide layer, a desired trench pattern (TR pattern) is formed on the oxide layer of the non-primitive region by photolithography, TEOS is etched out as a hard mask by using a dry etching oxide layer mode, then the photoresist is removed, the desired trench is etched out by using an etching process, and finally, TEOS functioning as a hard mask is completely stripped by using a wet process, so that a plurality of trenches of the non-primitive region are completely formed. Next, a gate oxide layer 212 is grown on the inner wall of the first trench and the semiconductor substrate 210 through a thermal oxidation process, a layer of polysilicon is deposited on the gate oxide layer 212 through a deposition process, the polysilicon is filled in the first trench 211, the polysilicon is removed through an etch-back process, and stays on the polysilicon layer when the polysilicon remains about 500A, so as to form a polysilicon gate layer 214 on the gate oxide layer 212 and the first trench 211.
In step S206, a semiconductor layer with a first conductive type dopant is formed on the polysilicon gate layer of the non-cell region.
As shown in fig. 3d, a semiconductor layer 220 with a first conductivity type doping is formed on the polysilicon gate layer 214 of the non-cell region, in one embodiment, the semiconductor layer 220 is a polysilicon layer of the first conductivity type, and the semiconductor layer 220 may be other polycrystalline semiconductor materials. In one embodiment, a polysilicon layer is deposited on the polysilicon gate layer 214 by a deposition process, the polysilicon layer is doped with a first conductivity type by a doping process to form a first conductivity type polysilicon layer, the polysilicon layer in a non-primitive region is etched by a first photolithography and etching process to form a first conductivity type doped semiconductor layer 220, the semiconductor layer 220 is used to form a protection structure, the polysilicon gate layer 214 except the semiconductor layer 220 is etched by a second etching process, and the polysilicon gate layer 214 can be etched by using the semiconductor layer 220 as a mask in the second etching process, thereby omitting the first photolithography process.
Step S208, a first conductive type well is implanted into the semiconductor substrate in the cell region using the semiconductor layer as a mask, and a well region is formed in the semiconductor substrate in the cell region.
In one embodiment, when the operating structure is a VDMOS transistor, before the first conductive type well implantation is performed on the semiconductor substrate in the cell region, the method further includes: and forming a second groove in the semiconductor substrate of the cell region, forming a gate oxide layer on the inner wall of the second groove, and filling the second groove with a polysilicon gate.
It can be understood that, when the operating structure is a VDMOS transistor, since a plurality of trenches are required to be formed in corresponding regions, a plurality of trenches can be formed in the cell region and the non-cell region respectively in the same step. For example, referring to fig. 3c, an oxide layer may be grown on the entire semiconductor substrate 210, the oxide layer may be made of TEOS dielectric material, then a photoresist is coated on the oxide layer, a desired trench pattern is formed on the oxide layer in the primitive cell region and the non-primitive cell region by photolithography, the oxide layer is etched by using a dry etching mode to use TEOS as a hard mask, then the photoresist is removed, the desired trench is etched by using an etching process, and finally the TEOS used as the hard mask is completely stripped by using a wet etching process, so that a plurality of first trenches 21 in the primitive cell region are completely formed and a plurality of second trenches 215 in the non-primitive cell region are completely formed, as shown in fig. 3e, in one embodiment, a planar structure diagram after the trenches are formed on the semiconductor substrate 210 is shown in fig. 4 a. Next, a gate oxide layer 212 is grown on the inner walls of the first trench 211, the second trench 215 and the semiconductor substrate 210 by a thermal oxidation process, and a layer of polysilicon is deposited on the gate oxide layer 212 by a deposition process, the polysilicon is filled in the first trench 211 and the second trench 215, and then the polysilicon is removed by an etch-back process and stays on the polysilicon layer when the polysilicon remains about 500A, so as to form polysilicon gates 213 in the first trench 211 and the second trench 215, respectively, and a polysilicon gate layer 214 is formed on the first trench 211, the second trench 215 and the gate oxide layer 212, as shown in fig. 3 e. Next, a polysilicon layer is deposited on the polysilicon gate layer 214 by a deposition process, the polysilicon layer is doped with a first conductivity type by a doping process to form a first conductivity type polysilicon layer, then the polysilicon layer in the primitive cell region and the polysilicon layer in a part of the non-primitive cell region are etched by a first photolithography and etching process to form a first conductivity type doped semiconductor layer 220, and all the polysilicon gate layer 214 except the semiconductor layer 220 are etched by a second etching process, as shown in fig. 3 f. Next, a first conductive type well implantation is performed on the semiconductor substrate 210 in the cell region using the semiconductor layer 220 as a mask, and a well region 216 is formed in the semiconductor substrate 210 in the cell region, as shown in fig. 3 g.
Step S210 is to dope the well region to form a working structure in the cell region, and dope the semiconductor layer to form a protection structure on the non-cell region.
The working structure is formed in the semiconductor substrate 210 by using the semiconductor substrate 210 in the cell region as a base, and the protection structure is formed on the semiconductor substrate 210 by using the semiconductor layer 220 on the semiconductor substrate 210 in the non-cell region as a base. After the semiconductor layer 220 and the well 216 are formed in steps S206 and S208, a working structure is formed in the cell region by doping, and a protection structure is formed on the non-cell region.
Step S212 is to form an interlayer dielectric layer on the working structure and the protection structure, form contact holes in the interlayer dielectric layer and on the first trench, form a metal interconnection layer connected to the contact holes on the interlayer dielectric layer, and connect the working structure and the protection structure through the metal interconnection layer and the contact holes.
An operation structure and a protection structure are formed through step S210, wherein the operation structure is formed in the semiconductor substrate 210 of the cell region, and the protection structure is formed in the semiconductor layer 220. As shown in fig. 3i, after the working structure and the protection structure are formed, an interlayer dielectric layer 230 is deposited, a contact hole is formed in the interlayer dielectric layer 230 and formed in the first trench 211, electrodes of the working structure and the protection structure are led out through the contact hole, and then a metal interconnection layer is deposited on the interlayer dielectric layer and connected with the contact hole, and the working structure and the protection structure are connected through the metal interconnection layer and the contact hole.
Step S210 and step S212 are described below by taking the example that the operating structure is a VDMOS transistor and the protection structure is a diode, wherein the semiconductor substrate 210 has the second conductivity type.
In step S210, doping the well region to form a working structure in the cell region, and doping the semiconductor layer to form a protection structure on the non-cell region, including: and doping the second conduction type in the well region to form a source region, and doping the second conduction type in a partial region of the semiconductor layer to form a first conduction type semiconductor structure and a second conduction type semiconductor structure which are parallel.
As shown in fig. 3h, the well region 216 is doped to form a source region 217, a partial region of the semiconductor layer 220 is doped with a second conductivity type to convert the first conductivity type semiconductor of the partial region into a second conductivity type semiconductor, so that the semiconductor layer forms a first conductivity type semiconductor structure 221 and a second conductivity type semiconductor structure 222 which are arranged in parallel, wherein the first conductivity type semiconductor structure 221 is a region of the semiconductor layer which is not doped with the second conductivity type, the second conductivity type semiconductor structure 222 is a region of the semiconductor layer which is doped with the second conductivity type, and the first conductivity type semiconductor structure 221 and the second conductivity type semiconductor structure 222 which are arranged in parallel form a PN junction.
In an embodiment, with continued reference to fig. 3h, the semiconductor layer 220 forms a plurality of first conductivity-type semiconductor structures 221 and a plurality of second conductivity-type semiconductor structures 222, the number of the first conductivity-type semiconductor structures 221 is different from that of the second conductivity-type semiconductor structures 222, the first conductivity-type semiconductor structures 221 and the second conductivity-type semiconductor structures 222 are alternately arranged, and one first trench is respectively corresponding to the lower side of the semiconductor structures at the middle position and the outermost position, wherein a first pole of the diode is led out from the semiconductor structure at the middle position, and a second pole of the diode is led out from the semiconductor structure at the outermost position, thereby forming a plurality of parallel diodes in a vertical structure. The diode junction area can be increased through the longitudinal structure, and the protection capability of the diode on the MOS tube is improved.
In one embodiment, the doping of the second conductivity type is performed on the well region to form a source region, and the doping of the second conductivity type is performed on a partial region of the semiconductor layer to form a first conductivity type semiconductor structure and a second conductivity type semiconductor structure which are arranged in parallel, and the doping of the second conductivity type is performed on the partial region of the semiconductor layer to form the first conductivity type semiconductor structure and the second conductivity type semiconductor structure which are arranged in parallel, and the doping of the second conductivity type semiconductor structure comprises the following steps: and forming a doping window on the well region and the semiconductor layer by sharing one mask plate, and simultaneously doping the second conductivity type in the well region and the semiconductor layer. The doping windows are formed above the cell region and on part of the semiconductor layer by sharing one mask plate, and the well region and part of the semiconductor layer are doped with the second conductivity type, so that the process steps can be saved.
In step S212, forming an interlayer dielectric layer on the working structure and the protection structure, forming a contact hole in the interlayer dielectric layer and on the first trench, and forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, and connecting the working structure and the protection structure through the metal interconnection layer and the contact hole, including: forming an interlayer dielectric layer on the source region, the second groove, the first conductive type semiconductor structure and the second conductive type semiconductor structure, forming a first contact hole on the interlayer dielectric layer above the source region and leading out a source electrode connected with the source region, forming a second contact hole on the interlayer dielectric layer above the second groove and leading out a grid electrode connected with the polysilicon gate, forming a third contact hole on the interlayer dielectric layer above the semiconductor structure at the middle position and leading out a first electrode of a diode connected with the polysilicon gate, forming a fourth contact hole on the first groove below the semiconductor structure at the outermost position and leading out a second electrode of the diode connected with the polysilicon gate, and forming a metal interconnection layer on the interlayer dielectric layer to connect the first electrode with the source electrode and connect the second electrode with the grid electrode.
As shown in fig. 3i, a layer of interlayer dielectric layer 230 is deposited on the source region 217, the second trench 215, and the first conductive type semiconductor structure 221 and the second conductive type semiconductor structure 222 by using a standard process, and the surface of the interlayer dielectric layer 230 is planarized. Then, a first contact hole 231 is formed in the interlayer dielectric layer 230 above the source region 217 and leads out a source electrode connected to the source region 217, a second contact hole (not shown) is formed in the interlayer dielectric layer 230 above the second trench 215 and leads out a gate electrode connected to the polysilicon gate 212, a third contact hole 232 is formed in the interlayer dielectric layer 230 above the second conductive type semiconductor structure 222 at the middle position and leads out a first electrode of a diode connected to the polysilicon gate, and a fourth contact hole (not shown) is formed in the first trench 211 below the second conductive type semiconductor structure 222 at the outermost position and leads out a second electrode of the diode connected to the polysilicon gate, and in one embodiment, a schematic plane structure after the contact holes are formed is shown in fig. 4 b. A metal interconnection layer is formed on the interlayer dielectric layer 230, the metal interconnection layer includes a first metal bar 241 connected to the first contact hole 231, a second metal bar (not shown) connected to the second contact hole, a third metal bar 242 connected to the third contact hole 232, and a fourth metal bar (not shown) connected to the fourth contact hole, the first electrode is connected to the source electrode, the second electrode is connected to the gate electrode through the metal interconnection layer and the contact holes, and in a specific embodiment, a schematic plane structure of the formed metal interconnection layer is shown in fig. 4 c. In one embodiment, the first contact hole 231 for leading out the source penetrates the source region 217 and extends to the well region 216, and the third contact hole 232 for leading out the first pole of the diode penetrates the second conductive type semiconductor structure 222 at the middle position and extends into the first trench 211 below the semiconductor structure. Meanwhile, a drain is formed on one side of the semiconductor substrate 210, which is far away from the interlayer dielectric layer, so that the parallel connection of the VDMOS tube and the diode is completed, and the electrostatic protection function of the VDMOS is realized by using the diode.
In the embodiment, the trench isolation is adopted to replace the field oxide process so as to meet the requirement of non-cell region on voltage resistance, effectively reduce the step difference between the protection structure region and other regions under the condition of reducing the number of photoetching layers, and obviously improve the process window of the subsequent metal etching process. Meanwhile, through optimizing the design of the protection structure, one end of the protection structure is led out through a groove below the semiconductor layer and is connected with the grid electrode, and the other end of the protection structure is connected with the source electrode through a through hole formed in the semiconductor layer, so that the phenomenon that a metal opening area is formed in the top of the semiconductor layer is avoided, the control difficulty of the reduction amount of the interlayer dielectric layer in the subsequent metal etching process is effectively solved, and the reliability problem caused by damage to the semiconductor layer due to a large amount of loss of the interlayer dielectric layer is solved. In addition, the protection structure adopts a longitudinal structure, the junction area of a PN junction in the protection structure is increased, the protection capability of the protection structure is improved, the production cost is reduced, the product performance is improved, and meanwhile, the process reliability of the product is improved.
In one embodiment, the semiconductor substrate includes an epitaxial layer of a semiconductor base grown from a semiconductor base. In one embodiment, the first conductive type may be a P-type and the second conductive type may be an N-type, or the first conductive type may be an N-type and the second conductive type may be a P-type. When the first conduction type is P type, the VDMOS tube formed by the method is an N type VDMOS tube, and when the first conduction type is N type, the VDMOS tube formed by the method is a P type VDMOS tube. The above embodiment specifically uses a VDMOS Transistor as a working structure, and in other embodiments, the VDMOS Transistor may also be a Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor (LDMOS Transistor for short) or other Semiconductor devices having a well implantation process.
According to the preparation method of the semiconductor device, the first groove is formed in the semiconductor substrate of the non-cell area, the gate oxide layer is formed on the inner wall of the first groove and the semiconductor substrate of the non-cell area, the first groove is filled with the polysilicon gate, the polysilicon gate layer is formed on the gate oxide layer and the first groove, and the semiconductor layer with the first conductive type doping is formed on the polysilicon gate layer of the non-cell area, wherein the first groove isolation is adopted to replace the field oxygen isolation, the field oxygen photoetching level can be omitted, and the semiconductor layer can be connected with the first groove through the polysilicon gate layer. In the subsequent process, an interlayer dielectric layer is formed on the working structure and the protection structure, contact holes are formed in the interlayer dielectric layer and on the first groove, a metal interconnection layer connected with the contact holes is formed on the interlayer dielectric layer, and the working structure and the protection structure are connected through the metal interconnection layer and the contact holes, wherein one end of the protection structure is led out by using the first groove structure, so that the problem that the surface of a semiconductor layer is damaged due to the fact that the two ends of the protection structure are interconnected with the interlayer dielectric layer above the semiconductor layer to form a metal interconnection layer opening area is avoided, the problem that the semiconductor device fails due to the fact that the interlayer dielectric layer above the protection structure is thin is effectively solved, the process control difficulty is reduced, and the product quality is improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device including an operating structure and a protection structure that protects the operating structure, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a cell region and a non-cell region;
forming a first groove in the semiconductor substrate of the non-cell region, forming a gate oxide layer on the inner wall of the first groove and the semiconductor substrate of the non-cell region, filling a polysilicon gate in the first groove and forming a polysilicon gate layer on the gate oxide layer and the first groove;
forming a semiconductor layer with first conductivity type doping on the polycrystalline silicon grid layer of the non-cell region;
performing first conductive type well injection on the semiconductor substrate of the cell region by taking the semiconductor layer as a mask, and forming a well region in the semiconductor substrate of the cell region;
doping the well region to form the working structure in the cell region, and doping the semiconductor layer to form the protection structure on the non-cell region;
forming an interlayer dielectric layer on the working structure and the protection structure, forming contact holes in the interlayer dielectric layer and on the first groove, forming a metal interconnection layer connected with the contact holes on the interlayer dielectric layer, and connecting the working structure and the protection structure through the metal interconnection layer and the contact holes;
and leading out one end of the protection structure through the contact hole by using the first groove so as to prevent the metal interconnection layers at the two ends of the protection structure from forming a metal interconnection layer opening area on the interlayer dielectric layer above the semiconductor layer.
2. The method of claim 1, wherein a gate oxide thickness of the bottom wall of the first trench is less than a gate oxide thickness on the sidewalls of the first trench and the semiconductor substrate of the non-cell region.
3. The method for preparing a semiconductor device according to claim 2, wherein the thickness of the gate oxide layer on the bottom wall of the first trench is 70% of the thickness of the gate oxide layer on the semiconductor substrate of the first trench sidewall or the non-cell region, and the proportion is gradually reduced as the thickness of the gate oxide layer is increased.
4. The method according to claim 1, wherein the thickness of the polysilicon gate layer is in a range of 400A to 600A.
5. The method of claim 1, wherein the active structure is a VDMOS transistor, and further comprises, before the implanting of the first conductive type well into the semiconductor substrate of the cell region:
and forming a second groove in the semiconductor substrate of the cell region, forming a gate oxide layer on the inner wall of the second groove, and filling a polysilicon gate in the second groove.
6. The method of claim 5, wherein the protection structure is a diode, the doping the well region to form the working structure in the cell region, and the doping the semiconductor layer to form the protection structure on the non-cell region comprise:
and doping the second conduction type on the well region to form a source region, and doping the second conduction type on a partial region of the semiconductor layer to form a first conduction type semiconductor structure and a second conduction type semiconductor structure which are parallel.
7. The method according to claim 6, wherein the semiconductor layer forms a plurality of the first conductivity-type semiconductor structures and a plurality of the second conductivity-type semiconductor structures, the first conductivity-type semiconductor structures and the second conductivity-type semiconductor structures are different in number, the first conductivity-type semiconductor structures and the second conductivity-type semiconductor structures are alternately arranged, and one first trench is respectively corresponding to a lower portion of the semiconductor structure at the middle position and at the outermost position.
8. The method as claimed in claim 7, wherein the forming an interlayer dielectric layer on the working structure and the protection structure, and forming a contact hole in the interlayer dielectric layer and on the first trench, and forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, the connecting the working structure and the protection structure through the metal interconnection layer and the contact hole comprises:
forming an interlayer dielectric layer on the source region, the second trench, the first conductive type semiconductor structure and the second conductive type semiconductor structure, forming a first contact hole on the interlayer dielectric layer above the source region and leading out a source electrode connected with the source region, forming a second contact hole on the interlayer dielectric layer above the second groove and leading out a grid connected with the polysilicon gate, forming a third contact hole on the interlayer dielectric layer above the semiconductor structure at the middle position and leading out a first pole of the diode connected with the polysilicon gate, forming a fourth contact hole on the first trench under the semiconductor structure at the outermost position and leading out a second pole of the diode connected with the polysilicon gate, and forming a metal interconnection layer on the interlayer dielectric layer to connect the first pole with the source electrode and connect the second pole with the grid electrode.
9. The method of claim 6, wherein the doping the well region with the second conductivity type to form a source region and the doping the semiconductor layer with the second conductivity type to form a first conductivity type semiconductor structure and a second conductivity type semiconductor structure in parallel comprises:
and forming a doping window on the well region and the semiconductor layer by sharing one mask plate, and simultaneously doping the second conductivity type in the well region and the semiconductor layer.
10. The method as claimed in any one of claims 1 to 9, wherein the cell region is located at a middle position of the semiconductor substrate, and the non-cell region is located at a periphery of the semiconductor substrate and surrounds the cell region.
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| US20100123185A1 (en) * | 2008-11-20 | 2010-05-20 | Force Mos Technology Co Ltd. | MSD integrated circuits with trench contact structures for device shrinkage and performance improvement |
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源系统有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
| US20170278837A1 (en) * | 2016-03-25 | 2017-09-28 | Force Mos Technology Co., Ltd | Semiconductor power device having shielded gate structure and esd clamp diode manufactured with less mask process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100123185A1 (en) * | 2008-11-20 | 2010-05-20 | Force Mos Technology Co Ltd. | MSD integrated circuits with trench contact structures for device shrinkage and performance improvement |
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源系统有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
| US20170278837A1 (en) * | 2016-03-25 | 2017-09-28 | Force Mos Technology Co., Ltd | Semiconductor power device having shielded gate structure and esd clamp diode manufactured with less mask process |
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