CN113035950B

CN113035950B - IGBT chip and preparation method thereof

Info

Publication number: CN113035950B
Application number: CN201911355591.3A
Authority: CN
Inventors: 李迪; 宁旭斌; 肖强; 覃荣震
Original assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Current assignee: Zhuzhou CRRC Times Semiconductor Co Ltd
Priority date: 2019-12-25
Filing date: 2019-12-25
Publication date: 2022-08-05
Anticipated expiration: 2039-12-25
Also published as: CN113035950A

Abstract

The disclosure provides an IGBT chip and a preparation method thereof. The IGBT chip includes: a terminal protection area and a cellular area; the cell area comprises an IGBT cell and a temperature sensing area, wherein the temperature sensing area comprises a first conduction type substrate, a field oxide layer positioned above the substrate, a first polycrystalline silicon layer and a second polycrystalline silicon layer which are arranged above the field oxide layer side by side, and a first electrode, a second electrode and a third electrode which are positioned above the first polycrystalline silicon layer and the second polycrystalline silicon layer and are isolated from each other; the first polycrystalline silicon layer is used for forming a positive temperature coefficient thermistor, and the second polycrystalline silicon layer is used for forming a negative temperature coefficient thermistor. According to the IGBT chip, the positive temperature coefficient thermistor (PTC) and the negative temperature coefficient thermistor (NTC) are integrated in the IGBT cell area, the NTC and the PTC are connected in series to amplify an electrical signal generated by temperature change, the temperature detection sensitivity is improved, and the performance and the reliability of the IGBT chip are further improved.

Description

IGBT chip and preparation method thereof

Technical Field

The disclosure relates to the technical field of semiconductor devices, in particular to an IGBT chip and a preparation method thereof.

Background

Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar Transistor) and MOSFET (metal oxide semiconductor field effect Transistor), and has become the most widely used semiconductor device in high-voltage, high-current, and high-frequency power electronic applications.

An Intelligent Power Module (IPM) is a switching device that packages an inductive element, a protection circuit, and a driving circuit together inside the module, which can improve the performance and reliability of an IGBT module and reduce the module volume. However, since the IGBT is a high-power semiconductor device, the heat generation phenomenon is severe due to large power loss, and if the temperature of the IGBT is too high, the operation of the module is affected, and the overall performance and reliability of the whole module are affected. In order to ensure the long-term safe operation of the IGBT, the IGBT must be designed for overheat protection while improving its heat dissipation capability. In order to prevent the IGBT from high-temperature thermal failure, a temperature sensor is generally packaged inside a power module in a module packaging process, but the temperature sensor in the structure is far away from an IGBT chip, the detected temperature is smaller than the junction temperature of the chip, and the error is larger.

Disclosure of Invention

In order to overcome the defects in the prior art, the present disclosure provides an IGBT chip and a method for manufacturing the same.

In a first aspect, the present disclosure provides an IGBT chip including a terminal protection region and a cell region;

the cell area comprises an IGBT cell area and a temperature sensing area;

the temperature sensing area comprises a first conduction type substrate, a field oxide layer positioned above the substrate, a first polycrystalline silicon layer and a second polycrystalline silicon layer which are arranged above the field oxide layer at intervals side by side, a first electrode positioned above the first polycrystalline silicon layer and electrically connected with the first polycrystalline silicon layer, a second electrode positioned above the second polycrystalline silicon layer and electrically connected with the second polycrystalline silicon layer, and a third electrode positioned above the first polycrystalline silicon layer and the second polycrystalline silicon layer and simultaneously electrically connected with the first polycrystalline silicon layer and the second polycrystalline silicon layer; wherein the first, second and third electrodes are isolated from each other;

the first polycrystalline silicon layer is used for forming a positive temperature coefficient thermistor, and the second polycrystalline silicon layer is used for forming a negative temperature coefficient thermistor.

According to an embodiment of the present disclosure, preferably, the first and second polysilicon layers are connected in series, in parallel, or in a mixture of series and parallel by the third electrode.

In a second aspect, the present disclosure provides an IGBT chip including a terminal protection region and a cell region;

the cell area comprises an IGBT cell area and a temperature sensing area;

the temperature sensing region comprises a first conductivity type substrate, a first thermistor region located above the substrate, and a second thermistor region located within the substrate;

the first thermistor region comprises a field oxide layer positioned above the substrate, a first polycrystalline silicon layer positioned above the field oxide layer, and a first electrode and a second electrode which are arranged above the first polycrystalline silicon layer and electrically connected with the first polycrystalline silicon layer and are isolated from each other; the first polycrystalline silicon layer is used for forming a negative temperature coefficient thermistor;

the second thermistor region comprises a second conduction type first well region positioned in the substrate, a first conduction type source region and a second conduction type source region which are adjacent and positioned in the first well region, a third electrode positioned above the substrate and electrically connected with the first conduction type source region, and a fourth electrode positioned above the substrate and electrically connected with the first conduction type source region and the second conduction type source region simultaneously; wherein the third and fourth electrodes are isolated from each other; the first conduction type source region is used for forming a positive temperature coefficient thermistor.

According to an embodiment of the present disclosure, preferably, the first thermistor region and the second thermistor region are connected in series, in parallel, or in a mixture of series and parallel by the second electrode and the third electrode.

According to an embodiment of the present disclosure, in the IGBT chip according to any one of the first aspect and the second aspect, the IGBT cell region preferably includes the substrate, a plurality of second well regions of the second conductivity type disposed at intervals in the substrate, a source region of the second conductivity type disposed in the second well region, a source region of the first conductivity type disposed in the second well region and disposed on two sides of the source region of the second conductivity type, a gate oxide layer disposed above the substrate between two adjacent second well regions and covering the substrate and the second well region and the source region of the first conductivity type in the second well region, a gate electrode disposed above the gate oxide layer, and an emitter metal layer disposed above the substrate and electrically connected to the source region of the first conductivity type and the source region of the second conductivity type in the second well region.

According to an embodiment of the present disclosure, preferably, in the IGBT chip according to any one of the first aspect and the second aspect, the IGBT cell region includes the substrate, a plurality of gate trenches disposed at intervals in the substrate, a gate disposed in the gate trench, a gate oxide layer disposed between the gate trench and the gate, a second well region of the second conductivity type located between two adjacent gate trenches, a source region of the second conductivity type located in the second well region, source regions of the first conductivity type located in the second well region and disposed at two sides of the source region of the second conductivity type, and an emitter metal layer located above the substrate and electrically connected to the source regions of the first conductivity type and the source regions of the second conductivity type in the second well region; the depth of the gate trench is greater than that of the second well region, and two ends of the first conduction type source region in the second well region are respectively connected with the gate trench and the second conduction type source region in the second well region.

According to an embodiment of the present disclosure, in the IGBT chip according to any one of the first aspect and the second aspect, the termination protection region preferably includes the substrate and field limiting rings spaced apart from each other in the substrate.

In a third aspect, the present disclosure provides a method for preparing an IGBT chip according to any one of the first aspect, including:

providing a first conductive type substrate;

forming a plurality of second conductive type second well regions arranged at intervals in the substrate;

forming a first conduction type source region and a second conduction type source region in the second well region to form an IGBT cellular region;

forming a field oxide layer above the substrate in the region where the second well regions are not formed to form a temperature sensing region, and forming a gate oxide layer between two adjacent second well regions in the IGBT cell region;

depositing a polysilicon layer above the field oxide layer and the gate oxide layer, etching the polysilicon layer, respectively forming a first polysilicon layer and a second polysilicon layer spaced from each other above the field oxide layer, and forming a gate above the gate oxide layer; wherein the gate is isolated from the second well region, the first conductivity type source region in the second well region, and the substrate by the gate oxide layer;

processing the first polysilicon layer and the grid electrode in a metal silicide mode;

and forming a metal layer above the first polysilicon layer, the second polysilicon layer and the second well region, and etching the metal layer to form a first electrode, a second electrode and a third electrode which are isolated from each other above the first polysilicon layer and the second polysilicon layer respectively, and to form an emitter metal layer above the second well region.

In a fourth aspect, the present disclosure provides a method for preparing an IGBT chip according to any one of the second aspects, including:

providing a first conductive type substrate;

forming a first well region of a second conduction type and a plurality of second well regions of the second conduction type arranged at intervals in the substrate;

forming a first conduction type source region and a second conduction type source region in the first well region and the second well region; wherein, in the first well region, the first conduction type source region and the second conduction type source region are adjacent to form a second thermistor region; in the second well region, the first conduction type source region is positioned at two sides of the second conduction type source region to form an IGBT cellular region;

forming a field oxide layer above the substrate between the first well region and the second well region adjacent to the first well region to form a first thermistor region, and forming a gate oxide layer between two adjacent second well regions in the IGBT cell region;

depositing a polysilicon layer above the field oxide layer and the gate oxide layer, etching the polysilicon layer, respectively forming a first polysilicon layer above the field oxide layer, and forming a gate above the gate oxide layer; wherein the gate is isolated from the second well region, the first conductivity type source region in the second well region, and the substrate by the gate oxide layer;

forming a metal layer over the first polysilicon layer, the first well region, and the second well region, and etching the metal layer to form a first electrode and a second electrode isolated from each other over the first polysilicon layer, a third electrode and a fourth electrode isolated from each other over the first well region, and an emitter metal layer over the second well region.

The embodiment of the disclosure provides an IGBT chip and a preparation method thereof. According to the IGBT chip, the positive temperature coefficient thermistor (PTC) and the negative temperature coefficient thermistor (NTC) are integrated in the IGBT cellular area, the NTC and the PTC are connected in series to amplify an electrical signal generated by temperature change, the temperature detection sensitivity is improved, the performance and the reliability of the IGBT chip are further improved, the application range of the IGBT chip is expanded, the size of the module can be reduced, and the power density of the module is improved. And all parts of the temperature sensing area are the same as all parts of the IGBT unit cell, the extra cost is low, and the process stability is good.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

fig. 1 is a schematic diagram of a front side top view of an IGBT chip shown in an exemplary embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of an IGBT chip having a planar gate structure according to an exemplary embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a thermistor illustrated in an exemplary embodiment of the present disclosure in a front plan view;

fig. 4 is a schematic flowchart illustrating a method for manufacturing an IGBT chip with a planar gate structure according to an exemplary embodiment of the present disclosure;

fig. 5a to 5e are schematic cross-sectional structural diagrams formed by relevant steps of a method for manufacturing an IGBT chip with a planar gate structure according to an exemplary embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional structure diagram of an IGBT chip of another planar gate structure shown in an exemplary embodiment of the present disclosure;

fig. 7 is a schematic flow chart illustrating a method for manufacturing an IGBT chip with another planar gate structure according to an exemplary embodiment of the present disclosure;

fig. 8a to 8e are schematic cross-sectional structural diagrams formed by relevant steps of a manufacturing method of an IGBT chip with another planar gate structure according to an exemplary embodiment of the disclosure;

fig. 9 is a schematic cross-sectional structure diagram of an IGBT chip having a trench gate structure according to an exemplary embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional structure view of an IGBT chip having another trench gate structure according to an exemplary embodiment of the present disclosure;

FIG. 11a is a schematic diagram of a conventional circuit for integrating an NTC in a power module;

FIG. 11b is a schematic diagram of a conventional circuit for integrating an NTC in an IGBT chip;

12a-12c are schematic diagrams of the circuit principle for integrating an NTC and a PTC within an IGBT chip according to an exemplary embodiment of the present disclosure;

FIG. 13 is a graph illustrating resistance versus temperature change for polysilicon having a positive temperature coefficient according to an exemplary embodiment of the present disclosure;

FIG. 14 is a graph illustrating resistance versus temperature change for polysilicon having a negative temperature coefficient in accordance with an exemplary embodiment of the present disclosure;

fig. 15 is a graph showing resistance versus temperature change of a first conductivity type source region having a positive temperature coefficient according to an exemplary embodiment of the present disclosure;

fig. 16 is a schematic diagram illustrating a temperature-dependent voltage variation across an NTC when the NTC and a PTC are connected in series and externally connected to a voltage source, which are integrated in an IGBT chip according to an exemplary embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.

Example one

As shown in fig. 1, an IGBT chip 100 with a planar gate structure includes a terminal protection region 110 and a cell region 120. The cell area 120 is located in the middle of the IGBT chip 100, and the terminal protection area 110 is located at the edge of the IGBT chip 100, surrounding the cell area 120.

The cell region 120 includes an IGBT cell region 121 and a temperature sensing region 122. The temperature sensing region 122 can be located at any position of the cell region 120, and the embodiment takes the case that the temperature sensing region 122 is located at the edge of the cell region 120 as an example.

As shown in fig. 2, the terminal protection region 110 and the cell region 120 each include the substrate 101, the collector layer 102, and the collector metal layer 103 of the IGBT chip.

Illustratively, the substrate 101 is a substrate of a first conductivity type. Collector layer 102 is a collector layer of the second conductivity type and is located below substrate 101. Collector metal layer 103 is located below collector layer 102 and forms an ohmic contact with collector layer 102.

The terminal protection region 110 includes a field limiting ring 1101 to implement a voltage withstanding function. Illustratively, the field limiting rings 1101 are spaced apart within the substrate, an upper surface of the field limiting rings 1101 is flush with an upper surface of the substrate 101, and a depth of the field limiting rings 1101 is not limited herein.

The IGBT cell region 121 includes a gate oxide layer 1211, a gate 1212, a second well region 1213, a second conductive type source region 1214, a first conductive type source region 1215, and an emitter metal layer 1216 in addition to the substrate 101.

In the IGBT cell region 121, the second well regions 1213 are second conductivity type well regions, and are disposed at intervals in the substrate 101, and the upper surfaces thereof are flush with the upper surface of the substrate 101.

The second conductive type source region 1214 is located at the center of the second well region 1213, and has an upper surface flush with the upper surface of the substrate 101. The first conductive type source region 1215 is located in the second well region 1213 on both sides of the second conductive type source region 1214, but does not contact the boundary of the second well region 1213, and has an upper surface level with the upper surface of the substrate 101. The emitter metal layer 1216 is positioned over the second conductive type source region 1214 and the first conductive type source region 1215, and is simultaneously electrically connected with the second conductive type source region 1214 and the first conductive type source region 1215.

The gate oxide layer 1211 is located over the substrate between adjacent two second well regions 1213 while covering the substrate 101, the second well regions 1213 and the source region 1215 of the first conductivity type but not contacting the emitter metal layer 1216. The gate oxide layer 1211 isolates the gate electrode 1212 from the substrate 101, the second well region 1213 and the source region 1215 of the first conductivity type.

The gate 1212 is located over the gate oxide 1211.

It is understood that the IGBT cell region 121 is an IGBT cell having a planar gate structure.

The temperature sensing region 122 includes a substrate 101, a field oxide layer 1221, a first polysilicon layer 1222, a second polysilicon layer 1223, a first electrode 1224, a second electrode 1225, and a third electrode 1226.

A field oxide layer 1221 is located over the substrate 101 for isolating the polysilicon layer from the substrate 101.

The first and

second polysilicon layers

1222 and 1223 are spaced side by side above the field oxide layer 1221.

The first polysilicon layer 1222 is polysilicon processed in a silicide (salicide) manner, and has a positive temperature coefficient of resistance, as in the gate 1212 in the IGBT cell region 121, and the first polysilicon layer 1222 is used to form a positive temperature coefficient thermistor (PTC).

The second polysilicon layer 1223 is not treated by means of a silicide (salicide) and has a negative temperature coefficient of resistance, and the second polysilicon layer 1223 is used to form a negative temperature coefficient thermistor (NTC).

A first electrode 1224 is positioned over the first polysilicon layer 1222 and is electrically connected to the first polysilicon layer 1222, a second electrode 1225 is positioned over the second polysilicon layer 1223 and is electrically connected to the second polysilicon layer 1223, and a third electrode 1226 is positioned over the first polysilicon layer 1222 and the second polysilicon layer 1223 and is simultaneously electrically connected to the first polysilicon layer 1222 and the second polysilicon layer 1223. Wherein the first electrode 1224, the second electrode 1225, and the third electrode 1226 are isolated from each other.

The first electrode 1224, the second electrode 1225, the third electrode 1226, and the emitter metal layer 1216 are the same metal layer, and may be a metal having low contact resistivity, such as aluminum or titanium.

The first polysilicon layer 1222(PTC) and the second polysilicon layer 1223(NTC) are connected in series through the third electrode 1226.

For example, as shown in fig. 3, the PTC may be formed by connecting a plurality of first polysilicon layers 1222 in series, and the NTC may be formed by connecting a plurality of second polysilicon layers 1223 in series.

In this embodiment, the first polysilicon layer 1222 and the second polysilicon layer 1223 may be connected in parallel or in a combination of series and parallel.

Corresponding to the IGBT chip 100, the embodiment of the present disclosure further provides a method for manufacturing the IGBT chip 100, in order to manufacture the IGBT chip. Fig. 4 is a schematic flow chart of a method for manufacturing the IGBT chip 100 according to the embodiment of the present disclosure. Fig. 5a to 5e are schematic cross-sectional structures formed in relevant steps of a method for manufacturing the IGBT chip 100 according to an embodiment of the disclosure. Next, detailed steps of an exemplary method of a method for manufacturing the IGBT chip 100 according to the embodiment of the present disclosure are described with reference to fig. 4 and fig. 5a to 5 e.

As shown in fig. 4, the method for manufacturing the IGBT chip 100 with a planar gate structure according to this embodiment includes the following steps:

s101: a first conductivity type substrate 101 is provided.

S102: a plurality of second conductivity-type second well regions 1213 are formed in the substrate 101 in the IGBT cell region 121 at intervals.

Specifically, step S102 includes: second conductivity type high energy ions are implanted over the substrate 101, second conductivity type second well regions 1213 are formed at intervals in the substrate 101 in the IGBT cell region 121, and field limiting rings 1101 are formed at intervals in the substrate 101 in the terminal protection region 110.

S103: as shown in fig. 5a, second conductive type source regions 1214 and first conductive type source regions 1215 are formed within the second well regions 1213 to form the IGBT cell regions 121.

Specifically, step S103 includes: second conductivity-type high-energy ions are implanted again over the second well regions 1213, forming second conductivity-type source regions 1214 within the second well regions 1213; first conductive type high energy ions are implanted over the second well regions 1213 to form first conductive type source regions 1215 in the second well regions 1213 on both sides of the second conductive type source regions 1214.

S104: as shown in fig. 5b, a field oxide layer 1221 is formed over the substrate 101 in a region where the second well regions 1213 are not formed to form the temperature sensing region 122, and a gate oxide layer 1211 is formed between two adjacent second well regions 1213 in the IGBT cell region 121.

Specifically, a silicon dioxide layer is deposited over the substrate 101, etched through a reticle to form field oxide layers 1221 to form the temperature sensing region 122, and a gate oxide layer 1211 within the IGBT cell region 121, respectively.

S105: as shown in fig. 5c, a polysilicon layer is deposited over the field oxide layer 1221 and the gate oxide layer 1211, and the polysilicon layer is etched, forming a first polysilicon layer 1222 and a second polysilicon layer 1223 spaced apart from each other over the field oxide layer 1221, and forming a gate 1212 over the gate oxide layer 1211, respectively; the gate 1212 is isolated from the second well region 1213, the first conductive type source region 1215 in the second well region 1213, and the substrate 101 by the gate oxide layer 1211.

Specifically, a polysilicon layer is deposited over the field oxide layer 1221 and the gate oxide layer 1211, and the polysilicon layer is etched, and an excess polysilicon layer is etched away to form a first polysilicon layer 1222 and a second polysilicon layer 1223 spaced apart from each other over the field oxide layer 1221, and a gate electrode 1212 is formed over the gate oxide layer 1211, respectively; the gate 1212 is isolated from the second well region 1213, the source region 1215 of the first conductivity type in the second well region 1213, and the substrate 101 by the gate oxide layer 1211.

S106: the first polysilicon layer 1222 and the gate electrode 1212 are processed by means of a metal Silicide (Silicide).

The resistance of the first polysilicon layer 1222 after being treated by means of metal Silicide (Silicide) has a positive temperature coefficient, and the first polysilicon layer 1222 is used to constitute a positive temperature coefficient thermistor (PTC).

While the second polysilicon layer 1223, which has a resistance with a negative temperature coefficient without being processed by means of a silicide (salicide), is used to form a negative temperature coefficient thermistor (NTC) 1223.

At this time, the PTC and NTC have only a difference in the Silicide process, and only the Mask in the Silicide process needs to be adjusted, so that an additional process is not required. And the NTC polysilicon and the PTC polysilicon are etched simultaneously, so that the deviation of the width (W) and the length (L) of the two resistors is almost the same, and the process stability is further improved. When the temperature is detected, the problem of resistance value fluctuation caused by process fluctuation in the semiconductor process is avoided. And the temperature coefficient required by the design can be obtained by adjusting the W and L of the resistor.

S107: as shown in fig. 5d, a metal layer is formed over the first polysilicon layer 1222, the second polysilicon layer 1223, and the second well region 1213 and is etched to form a first electrode 1224, a second electrode 1225, and a third electrode 1226, which are isolated from each other, over the first polysilicon layer 1222 and the second polysilicon layer 1223, respectively, and an emitter metal layer 1216 is formed over the second well region 1213.

Specifically, in the temperature sensing region 122, the first electrode 1224 is electrically connected to the first polysilicon layer 1222, the second electrode 1225 is electrically connected to the second polysilicon layer 1223, and the third electrode 1226 is simultaneously electrically connected to the first polysilicon layer 1222 and the second polysilicon layer 1223. Within IGBT cell region 121, emitter metal layer 1216 forms electrical connections with both second conductivity-type source region 1214 and first conductivity-type source region 1215 located within second well region 1213.

S108: high-energy ions of the second conductivity type are implanted under the substrate 101, a second conductivity type collector layer 102 is formed under the substrate 101,

s109: as shown in fig. 5e, a collector metal layer 103 is formed under collector layer 102 in ohmic contact with collector layer 102.

In the present embodiment, the first conductivity type and the second conductivity type are opposite in conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.

The embodiment of the present disclosure provides an IGBT chip 100 with a planar gate structure, in which a positive temperature coefficient thermistor (PTC) and a negative temperature coefficient thermistor (NTC) are integrated in a cell region 120, and an electrical signal generated by a temperature change is amplified by using the serial connection of the NTC and the PTC resistor, so as to improve temperature detection sensitivity, further improve the performance and reliability of the IGBT chip 100, expand the application range of the IGBT chip 100, reduce the module size, and improve the power density of the module. Moreover, each part of the temperature sensing area 122 is the same as each part of the IGBT cell area 121, so that the additional cost is low and the process stability is good.

Example two

Referring to fig. 6, an IGBT chip 200 with a planar gate structure includes a terminal protection region 210 and a cell region 220. The cell region 220 includes an IGBT cell region 221 and a temperature sensing region 222. The temperature sensing region 222 can be located at any position of the cell region 220, and the embodiment takes the case where the temperature sensing region 222 is located at the edge of the cell region 220 as an example.

The terminal protection region 210 and the cell region 220 each include the substrate 201, the collector layer 202, and the collector metal layer 203 of the IGBT chip.

Illustratively, the substrate 201 is a first conductivity type substrate. The collector layer 202 is a collector layer of the second conductivity type, and is located below the substrate 201. Collector metal layer 203 is situated under collector layer 202 and forms an ohmic contact with collector layer 202.

The terminal protection zone 210 includes a field limiting ring 2101 to implement a voltage withstand function. Illustratively, the field limiting rings 2101 are spaced apart within the substrate, the upper surface of the field limiting rings 2101 is flush with the upper surface of the substrate 201, and the depth of the field limiting rings 2101 is not limited herein.

In addition to the substrate 201, the IGBT cell area 221 includes a gate oxide layer 2211, a gate 2212, a second well area 2213, a second conductive type source area 2214, a first conductive type source area 2215, and an emitter metal layer 2216.

In the IGBT cell region 221, the second well 2213 is a well of the second conductivity type, and is disposed at intervals in the substrate 201, and the upper surface of the second well is flush with the upper surface of the substrate 201.

The second conductive type source region 2214 is located at the center of the second well region 2213, and the upper surface is flush with the upper surface of the substrate 201. The first conductive type source region 2215 is located in the second well region 2213 and on two sides of the second conductive type source region 2214, but does not contact the boundary of the second well region 2213, and the upper surface is flush with the upper surface of the substrate 201. An emitter metal layer 2216 is positioned over the second conductive type source region 2214 and the first conductive type source region 2215 and simultaneously forms an electrical connection with the second conductive type source region 2214 and the first conductive type source region 2215.

The gate oxide layer 2211 is located over the substrate between two adjacent second well regions 2213 while covering the substrate 201, the second well regions 2213, and the source regions 2215 of the first conductivity type but not contacting the emitter metal layer 2216. The gate oxide layer 2211 isolates the gate electrode 2212 from the substrate 201, the second well region 2213 and the source region 2215 of the first conductivity type.

A gate 2212 is located above the gate oxide layer 2211.

It is understood that the IGBT cell region 221 is an IGBT cell having a planar gate structure.

The temperature sensing region 222 includes the substrate 201, a first thermistor region (not shown), and a second thermistor region (not shown).

The first thermistor region is located over the substrate 201, and includes a field oxide layer 2221, a first polysilicon layer 2222, a first electrode 2223, and a second electrode 2224.

In the first thermistor region, a field oxide layer 2221 is located above the substrate 201 for isolating the polysilicon layer from the substrate 201.

The first polysilicon layer 2222 is located above the field oxide layer 2221. In this embodiment, the first polysilicon layer 2222 is the same as the gate 2212 in the IGBT cell area 221, and is not processed by means of silicide (silicide), so the first polysilicon layer 2222 has a negative temperature coefficient of resistance, and the first polysilicon layer 2222 is used to form a negative temperature coefficient thermistor (NTC).

A first electrode 2223 and a second electrode 2224 are located above the first polysilicon layer 2222, and are electrically connected to the first polysilicon layer 2222. Wherein the first electrode 2223 and the second electrode 2224 are isolated from each other.

The second thermistor region includes a first well region 2225, a second conductive type source region 2226, a first conductive type source region 2227, a third electrode 2228, and a fourth electrode 2229, which are disposed in the substrate 201.

In the second thermistor region, the first well region 2225 is a second conductivity type well region, and the doping concentration is the same as that of the second well region 2213 in the IGBT cell region 221.

The first conductive-type source region 2227 is located within the first well region 2225. A second conductivity type source region 2226 is also located within the first well region 2225 and abuts the first conductivity type source region 2227. An upper surface of the first well region 2225, an upper surface of the first conductive-type source region 2227, and an upper surface of the second conductive-type source region 2226 are all flush with the upper surface of the substrate 101.

The third electrode 2228 is positioned above the first conductive-type source region 2227 and is electrically connected to the first conductive-type source region 2227. The fourth electrode 2229 is positioned above the boundary of the first conductive-type source region 2227 and the second conductive-type source region 2226 while forming an electrical connection with the first conductive-type source region 2227 and the second conductive-type source region 2226. In which the third electrode 2228 and the fourth electrode 2229 are isolated from each other.

In the temperature sensing area 222, the first electrode 2223, the second electrode 2224, the third electrode 2228, the fourth electrode 2229, and the emitter metal layer 2216 in the IGBT cell area 221 are the same metal layer, and may be a metal having low contact resistivity, such as aluminum or titanium.

In the second thermistor inner region, the resistance of the first conductive type source region 2227 has a positive temperature coefficient, and the first conductive type source region 2227 is used to constitute a positive temperature coefficient thermistor (PTC). The second conductivity type source region 2226 functions to draw out the first well region 2225, and the second conductivity type source region 2226 and the first conductivity type source region 2227 are adjoined in order to prevent the potential of the first well region 2225 from floating to deplete the first conductivity type source region 2227 resistively.

In the temperature sensing region 222, a first thermistor region (NTC) and a second thermistor region (PTC) are connected in series through a second electrode 2224 and a third electrode 2228.

In this embodiment, the first thermistor region (NTC) and the second thermistor region (PTC) may be connected in parallel or in a combination of series and parallel.

Corresponding to the IGBT chip 200, the embodiment of the present disclosure further provides a method for manufacturing the IGBT chip 200, in order to manufacture the IGBT chip. Fig. 7 is a schematic flow chart of a method for manufacturing an IGBT chip according to an embodiment of the present disclosure. Fig. 8a to 8e are schematic cross-sectional structures formed in relevant steps of a method for manufacturing an IGBT chip according to an embodiment of the present disclosure. Next, detailed steps of an exemplary method of a method for manufacturing the IGBT chip 200 according to the embodiment of the present disclosure will be described with reference to fig. 7 and 8a to 8 e.

As shown in fig. 7, the method for manufacturing the IGBT chip 200 with a planar gate structure according to this embodiment includes the following steps:

s201: a first conductivity type substrate 201 is provided.

S202: a second conductive-type first well region 2225 and a plurality of second conductive-type second well regions 2213 are formed in the substrate 201.

Specifically, step S202 includes: high-energy ions of the second conductivity type are implanted over the substrate 201, and a first well region 2225 of the second conductivity type is formed in the second thermistor region of the temperature sensing region 222, a plurality of second well regions 2213 of the second conductivity type are formed at intervals in the substrate 201 in the IGBT cell region 221, and field limiting rings 2101 are formed at intervals in the substrate 201 in the terminal protection region 210, respectively.

S203: as in fig. 8a, first and second conductivity-type source regions are formed in the first well region 2225 and the second well region 2213; wherein, in the first well region 2225, the first conductive type source region 2227 and the second conductive type source region 2226 are adjacent to form a second thermistor region (not labeled); in the second well region 2213, the first conductive type source regions 2215 are located at both sides of the second conductive type source region 2214 to form the IGBT cell region 221.

Specifically, step S203 includes: second conductivity type high energy ions are implanted again above the first well region 2225 and the second well region 2213, so that a second conductivity type source region 2226 is formed in the first well region 2225, and a second conductivity type source region 2214 is formed in the second well region 2213; high-energy ions of the first conductivity type are implanted over the first well region 2225 and the second well region 2213, so as to form a source region 2227 of the first conductivity type beside the source region 2226 of the second conductivity type in the first well region 2225 and form source regions 2215 of the first conductivity type at two sides of the source region 2214 of the second conductivity type in the second well region 2213, respectively.

S204: as shown in fig. 8b, a field oxide layer 2221 is formed over the substrate 101 between the first well region 2225 and the second well region 2213 adjacent thereto to form a first thermistor region (not labeled in the figure), and a gate oxide layer 2211 is formed between two adjacent second well regions 2213 in the IGBT cell region 221.

Specifically, a silicon dioxide layer is deposited over the substrate 201, and is etched through a mask to form a field oxide layer 2221 in the first thermistor region and a gate oxide layer 2211 in the IGBT cell region 221, respectively.

S205: as shown in fig. 8c, a polysilicon layer is deposited over the field oxide layer 2221 and the gate oxide layer 2211, and the polysilicon layer is etched to form a first polysilicon layer 2222 over the field oxide layer 2221 and a gate 2212 over the gate oxide layer 2211, respectively; the gate 2212 is isolated from the second well 2213, the first conductive source 2215 in the second well 2213 and the substrate 201 by the gate oxide layer 2211.

Specifically, a polysilicon layer is deposited over the field oxide layer 2221 and the gate oxide layer 2211, and the polysilicon layer is etched through a mask to remove an excess polysilicon layer, thereby forming a first polysilicon layer 2222 over the field oxide layer 2221 and a gate 2212 over the gate oxide layer 2211, respectively. The first polysilicon layer 2222 is isolated from the substrate 201 by the field oxide layer 2221, and the gate 2212 is isolated from the second well 2213, the first conductive source 2215 in the second well 2213 and the substrate 201 by the gate oxide layer 2211.

S206: as shown in fig. 8d, a metal layer is formed over the first polysilicon layer 2222, the first well region 2225 and the second well region 2213 and etched to form a first electrode 2223 and a second electrode 2224 isolated from each other over the first polysilicon layer 2222, a third electrode 2228 and a fourth electrode 2229 isolated from each other over the first well region 2225, and an emitter metal layer 2216 over the second well region 2213.

Specifically, in the first thermistor region of the temperature sensing region 222, the first electrode 2223 and the second electrode 2224 are located above the first polysilicon layer 2222 and are both electrically connected to the first polysilicon layer 2222. In the second thermistor of the temperature sensing region 222, the third electrode 2228 and the fourth electrode 2229 are located above the substrate 201, the third electrode 2228 is electrically connected to the first conductivity type source region 2227, and the fourth electrode 2229 is electrically connected to both the first conductivity type source region 2227 and the second conductivity type source region 2226.

In the IGBT cell area 221, the emitter metal layer 2216 is electrically connected to both the second conductivity type source area 2214 and the first conductivity type source area 2215.

S207: high-energy ions of the second conductivity type are implanted under the substrate 201, and a second conductivity type collector layer 202 is formed under the substrate 201.

S208: as shown in fig. 8e, a collector metal layer 203 electrically connected to the collector layer 202 is formed under the collector layer 202.

The embodiment of the present disclosure provides an IGBT chip 200 with a planar gate structure, in which a positive temperature coefficient thermistor (PTC) and a negative temperature coefficient thermistor (NTC) are integrated in an IGBT cell area 220, and an electrical signal generated by a temperature change is amplified by using the serial connection of the NTC and the PTC resistor, so as to improve temperature detection sensitivity, further improve the performance and reliability of the IGBT chip 200, expand the application range of the IGBT chip 200, reduce the module size, and improve the power density of the module. Moreover, each part of the temperature sensing region 222 is the same as each part of the IGBT cell region 221, so that the additional cost is low and the process stability is good.

EXAMPLE III

As shown in fig. 9, on the basis of the first embodiment, the present embodiment provides an IGBT chip 300 with a trench gate structure, which includes a terminal protection region 310 and a cell region 320. The cell area 320 is located in the middle of the IGBT chip 300, and the terminal protection area 310 is located at the edge of the IGBT chip 300, surrounding the cell area 320.

The cell region 320 includes an IGBT cell region 321 and a temperature sensing region 322. The temperature sensing region 322 may be located at any position of the cell region 320, and the embodiment takes the case where the temperature sensing region 322 is located at the edge of the cell region 320 as an example.

The terminal protection region 310 and the cell region 320 each include the substrate 101 of the IGBT chip, the collector layer 302, and the collector metal layer 303.

Illustratively, the substrate 101 is a first conductivity type substrate. Collector layer 302 is a collector layer of the second conductivity type and is located below substrate 101. Collector metal layer 303 is situated under collector layer 302 and forms an ohmic contact with collector layer 302.

The termination protection region 310 includes a field limiting ring 3101 to implement a withstand voltage function. Illustratively, field limiting rings 3101 are spaced apart within the substrate, the upper surface of field limiting rings 3101 is flush with the upper surface of substrate 301, and the depth of field limiting rings 3101 is not limited herein.

In addition to the substrate 301, the IGBT cell region 321 further includes a gate oxide layer 3211, a gate 3212, a second well region 3213, a second conductive type source region 3214, a first conductive type source region 3215, and an emitter metal layer 3216.

A gate trench is formed in the substrate 301 in the IGBT cell region 321, the depth of the gate trench is greater than that of the second well region 3213, and a gate oxide layer 3211 is formed on the bottom and wall of the gate trench to isolate a gate 3212 formed in the gate trench from the first conductive type source region 3215, the second well region 3213, and the substrate 301.

The second well 3213 is a well of the second conductivity type, and is located in the cell area 321 and the substrate 301, and has an upper surface flush with an upper surface of the substrate 301.

In the IGBT cell, the second conductivity type source region 3214 is located in the center of the well region between the two gate trenches, and the upper surface of the second conductivity type source region is flush with the upper surface of the substrate 301. The first conductive type source region 3215 is located in the second well region 3213 and on two sides of the second conductive type source region 3214, two ends of the first conductive type source region 3215 are respectively connected to the gate trench and the second conductive type source region 3214, and an upper surface of the first conductive type source region 3215 is flush with an upper surface of the substrate 301. Emitter metal layer 3216 is located over second conductive-type source region 3214 and first conductive-type source region 3215 while forming an electrical connection with second conductive-type source region 3214 and first conductive-type source region 3215.

It is understood that the IGBT cell region 321 is an IGBT cell having a trench gate structure.

The temperature sensing region 322 includes a substrate 101, a field oxide layer 3221, a first polysilicon layer 3222, a second polysilicon layer 3223, a first electrode 3224, a second electrode 3225, and a third electrode 3226.

A field oxide layer 3221 is located over the substrate 101 for isolating the polysilicon layer from the substrate 101.

The first polysilicon layer 3222 and the second polysilicon layer 3223 are disposed side by side over the field oxide layer 3221.

The first polysilicon layer 3222 is polysilicon treated in a silicide (silicide) manner, and has a positive temperature coefficient of resistance, as in the gate 3212 in the IGBT cell region 321, and the first polysilicon layer 3222 is used to form a positive temperature coefficient thermistor (PTC).

The second polysilicon layer 3223 is not treated with a silicide (salicide) process, and has a negative temperature coefficient of resistance, and the second polysilicon layer 3223 is used to form a negative temperature coefficient thermistor (NTC).

A first electrode 3224 is positioned over the first polysilicon layer 3222 and is electrically connected to the first polysilicon layer 3222, a second electrode 3225 is positioned over the second polysilicon layer 3223 and is electrically connected to the second polysilicon layer 3223, and a third electrode 3226 is positioned over the first polysilicon layer 3222 and the second polysilicon layer 3223 and is simultaneously electrically connected to the first polysilicon layer 3222 and the second polysilicon layer 3223. Wherein the first electrode 3224, the second electrode 3225, and the third electrode 3226 are isolated from one another.

First electrode 3224, second electrode 3225, third electrode 3226, and emitter metal layer 3216 are the same metal layer, and may be a metal having low contact resistivity, such as aluminum or titanium.

The first polysilicon layer 3222(PTC) and the second polysilicon layer 3223(NTC) are connected in series by the third electrode 3226.

In this embodiment, the connection mode of the first polysilicon layer 3222 and the second polysilicon layer 3223 may also be a parallel connection mode or a series-parallel connection hybrid mode.

It should be noted that the preparation method of the IGBT chip 300 with a trench gate structure provided in this embodiment is similar to the preparation method of the IGBT chip 100 with a planar gate structure in the first embodiment, and only the difference between the preparation processes of the trench gate and the planar gate exists, so the preparation method of the IGBT chip 300 with a trench gate structure is not described in detail in this embodiment.

The embodiment of the present disclosure provides an IGBT chip 300 with a trench gate structure, in which a positive temperature coefficient thermistor (PTC) and a negative temperature coefficient thermistor (NTC) are integrated in an IGBT cell area 320, and an electrical signal generated by a temperature change is amplified by using the serial connection of the NTC and the PTC resistor, so that the temperature detection sensitivity is improved, the performance and reliability of the IGBT chip 300 are further improved, the application range of the IGBT chip 300 is expanded, the module volume can be reduced, and the power density of the module is improved. Moreover, each part of the temperature sensing area 322 is the same as each part of the IGBT cellular area 321, so that the additional cost is low, and the process stability is good.

Example four

As shown in fig. 10, on the basis of the second embodiment, the present embodiment provides another IGBT chip 400, which includes a terminal protection region 410 and a cell region 420. The cell region 420 includes an IGBT cell region 421 and a temperature sensing region 422. The temperature sensing area 422 can be located at any position of the cell area 420, and the embodiment takes the case that the temperature sensing area 422 is located at the edge of the cell area 420 as an example.

The terminal protection region 410 and the cell region 420 each include the substrate 401, the collector layer 402, and the collector metal layer 403 of the IGBT chip.

Illustratively, the substrate 401 is a first conductivity type substrate. The collector layer 402 is a collector layer of the second conductivity type, and is located below the substrate 401. Collector metal layer 403 is located below collector layer 402 and forms an ohmic contact with collector layer 402.

The terminal protection region 410 includes a field limiting ring 4101 to implement a withstand voltage function. Illustratively, the field limiting rings 4101 are spaced apart within the substrate, the upper surface of the field limiting rings 4101 is flush with the upper surface of the substrate 401, and the depth of the field limiting rings 4101 is not limited herein.

The IGBT cell region 421 includes a gate oxide layer 4211, a gate electrode 4212, a second well region 4213, a second conductive type source region 4214, a first conductive type source region 4215, and an emitter metal layer 4216.

A gate trench having a depth larger than that of the second well region 4213 is provided in the substrate 401 within the IGBT cell region 421, and a gate oxide layer 4211 is provided on the bottom and wall portions of the gate trench for isolating the gate 4212 provided in the gate trench from the first conductivity type source region 4215, the second well region 4213, and the substrate 401.

The second well 4213 is a well of the second conductivity type, and is located in the cell region 421 and the substrate 401, and has an upper surface flush with an upper surface of the substrate 401.

In the IGBT cell, the second conductivity type source region 4214 is located in the center of the second well region between the two gate trenches, and the upper surface of the second conductivity type source region is flush with the upper surface of the substrate 401. The first conductive type source region 4215 is located in the second well region 4213 and on two sides of the second conductive type source region 4214, two ends of the first conductive type source region 4215 are respectively connected to the gate trench and the second conductive type source region 4214, and an upper surface of the first conductive type source region 4215 is flush with an upper surface of the substrate 401. An emitter metal layer 4216 is positioned over the second conductive-type source regions 4214 and the first conductive-type source regions 4215 and simultaneously forms an electrical connection with the second conductive-type source regions 4214 and the first conductive-type source regions 4215.

It is understood that the IGBT cell region 421 is an IGBT cell having a trench gate structure.

Temperature sensing region 422 includes substrate 401, a first thermistor region (not labeled), and a second thermistor region (not labeled).

A first thermistor region is located over the substrate 401, and the first thermistor region includes a field oxide layer 4221, a first polysilicon layer 4222, a first electrode 4223, and a second electrode 4224.

In the first thermistor region, a field oxide layer 4221 is located above the substrate 401 for isolating the polysilicon layer from the substrate 401.

The first polysilicon layer 4222 is located over the field oxide layer 4221. In this embodiment, the first polysilicon layer 4222 is not treated with silicide (silicide) like the gate electrode 4212 in the IGBT cell region 421, so the first polysilicon layer 4222 has a negative temperature coefficient of resistance, and the first polysilicon layer 4222 is used to form a negative temperature coefficient thermistor (NTC).

A first electrode 4223 and a second electrode 4224 are located above the first polysilicon layer 4222, both making electrical connection with the first polysilicon layer 4222. Wherein the first electrode 4223 and the second electrode 4224 are isolated from each other.

The second thermistor region includes a first well region 4225, a second conductivity type source region 4226, a first conductivity type source region 4227, a third electrode 4228 and a fourth electrode 4229 disposed within the substrate 401.

In the second thermistor region, the first well region 4225 is a second conductivity type well region, and the doping concentration is the same as that of the second well region 4213 in the IGBT cell region 421.

First conductivity-type source regions 4227 are located within the first well region 4225. Second-conductivity-type source regions 4226 are also located within the first well region 4225 and adjoin the first-conductivity-type source regions 4227. An upper surface of the first well region 4225, an upper surface of the first conductive-type source region 4227, and an upper surface of the second conductive-type source region 4226 are all flush with an upper surface of the substrate 101.

A third electrode 4228 is positioned over the first-conductivity-type source regions 4227 and is electrically connected to the first-conductivity-type source regions 4227. The fourth electrode 4229 is positioned above a boundary of the first conductive-type source region 4227 and the second conductive-type source region 4226 while forming an electrical connection with the first conductive-type source region 4227 and the second conductive-type source region 4226. Wherein the third electrode 4228 and the fourth electrode 4229 are isolated from each other.

In the temperature sensing region 422, the first electrode 4223, the second electrode 4224, the third electrode 4228, the fourth electrode 4229, and the emitter metal layer 4216 in the IGBT cell region 421 are the same metal layer, and may be a metal having low contact resistivity, such as aluminum or titanium.

In the second thermistor region, the resistance of the first conductive type source region 4227 has a positive temperature coefficient, and the first conductive type source region 4227 is used to constitute a positive temperature coefficient thermistor (PTC). The second conductivity type source region 4226 functions to lead out the first well region 4225, and the second conductivity type source region 4226 and the first conductivity type source region 4227 are adjoined in order to prevent the potential of the first well region 4225 from floating to deplete the first conductivity type source region 4227 in resistance.

In the temperature sensing region 422, a first thermistor region (NTC) and a second thermistor region (PTC) are connected in series by a second electrode 4224 and a third electrode 4228.

It should be noted that the preparation method of the IGBT chip 400 with the trench gate structure provided in this embodiment is similar to the preparation method of the IGBT chip 200 with the planar gate structure in the second embodiment, and only the difference between the preparation processes of the trench gate and the planar gate exists, so the preparation method of the IGBT chip 400 with the trench gate structure is not described in detail in this embodiment.

The embodiment of the present disclosure provides an IGBT chip 400, in which a positive temperature coefficient thermistor (PTC) and a negative temperature coefficient thermistor (NTC) are integrated in an IGBT cell area 420, and the NTC and the PTC resistor are connected in series to amplify an electrical signal generated by a temperature change, thereby improving temperature detection sensitivity, further improving performance and reliability of the IGBT chip 400, expanding an application range of the IGBT chip 400, reducing a module size, and improving a power density of the module. Moreover, all parts of the temperature sensing area 422 are the same as all parts of the IGBT cellular area 421, the additional cost is low, and the process stability is good.

EXAMPLE five

The present embodiment provides an operating circuit principle of a temperature sensor.

The conventional circuit principle of integrating the NTC in the power module is shown in fig. 11a, and the conventional circuit principle of integrating the NTC in the IGBT chip is shown in fig. 11 b.

The present disclosure provides an IGBT chip integrating a PTC and an NTC within an IGBT cell region, which can be connected in series, for example, as shown in fig. 12a and 12 b; the PTC and NTC may also be connected in parallel, for example as shown in fig. 12 c. When PTC is polysilicon treated by means of Silicide, the resistance and temperature change relationship of the PTC is as shown in fig. 13, the resistance of the polysilicon increases with the increase of temperature, and the temperature coefficient of resistance of the polysilicon increases with the increase of the polysilicon width (W); when NTC is polysilicon that has not been treated by means of Silicide, the resistance and temperature change relationship of the NTC is shown in fig. 14, and the resistance of the polysilicon decreases with increasing temperature; when the PTC is the first conductive type source region, the resistance and temperature change relationship thereof is as shown in fig. 15, the resistance of the source region increases with the increase of temperature, and the temperature coefficient of resistance of the source region increases with the increase of the source region width (W).

Taking the IGBT chip 100 provided in the first embodiment as an example, the PTC is polysilicon processed by using Silicide, and the NTC is polysilicon not processed by using Silicide, at this time, the PTC and the NTC only have a difference in the Silicide process, and only need to adjust the Mask in the Silicide process, so that no additional process is needed. And the NTC polysilicon and the PTC polysilicon are etched simultaneously, so that the deviation of the width (W) and the length (L) of the two resistors is almost the same, and the process stability is further improved. When the temperature is detected, the problem of resistance value fluctuation caused by process fluctuation in the semiconductor process is avoided. And the temperature coefficient required by the design can be obtained by adjusting the W and L of the resistor.

Illustratively, when the PTC and NTC are connected in series, a schematic of the circuit is shown in fig. 12a, for example. PTC has a resistance of R _P NTC with a resistance of R _N At this time, the PTC and NTC operate as follows:

a. the temperature coefficient sensitivity is delta R/(R delta T), wherein delta R is an absolute value, if 2 NPCs or 2 PTC are connected in series, the total sensitivity is equal to 2 delta R/(2R delta T) or delta R/(R delta T), and the sensitivity is kept unchanged; if PTC and NTC are connected in series, the total sensitivity is equal to Δ R _N /(R _N *△T)+△R _P /(R _P Δ T), this overall sensitivity being greater than Δ R _N /(R _N Δ T) or Δ R _P /(R _P Δ T), the temperature coefficient sensitivity using a PTC and NTC series is greater than that of a pure 2 NPC or 2 PTC series.

b. When the two ends of the temperature sensor are externally connected with a current source (fixed current), the voltage difference V between the two ends of the PTC is _P The voltage difference V between two terminals of NTC _N Are all directly detectable, V _P And (absolute value) and V _N The change value (absolute value) of (A) can be directly reflected by a change in temperature, V _p And V _N Is larger than the voltage variation value detected when only the NTC resistor is used.

c. When the two ends of the temperature sensor are externally connected with a voltage source (fixed voltage), the voltage V at the two ends of the NTC is _N The temperature-dependent change curve is shown in FIG. 16, when Δ R _N ＝ΔR _P The total resistance R of NTC and PTC is kept constant, the current I is constant, and V is _N ＝I*R _N ，V _N Decreases linearly with increasing temperature, and R _N The change trends of the two are consistent; when Δ R is _N <ΔR _P The total resistance R of the NTC and PTC increases, the current decreases, V _N ＝I*R _N ，R _N Also decreases with temperature, therefore V _N An accelerated decrease with increasing temperature; when Δ R is _N >ΔR _P The total resistance R of the NTC and PTC decreases, the current increases, V _P ＝I*R _P ，R _P Also increases with temperature, so V _P The rise is accelerated with increasing temperature. Obtaining V by reasonable chip design _N (or V) _P ) The temperature detection is realized according to the temperature change relationship (or the voltage division ratio is according to the temperature change relationship).

The embodiment provides an IGBT chip, wherein the NTC and the PTC are integrated in a cell area of the IGBT chip, and an electrical signal generated by temperature change is amplified by using a serial connection mode of the NTC and the PTC, so that temperature detection sensitivity is improved, performance and reliability of the IGBT chip are further improved, and an application range of the IGBT chip is expanded.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.

Claims

1. An IGBT chip is characterized by comprising a terminal protection area and a cellular area;

the cell area comprises an IGBT cell area and a temperature sensing area;

2. The IGBT chip according to claim 1, wherein the first polysilicon layer and the second polysilicon layer are connected in series, in parallel, or in a mixture of series and parallel by the third electrode.

3. An IGBT chip is characterized by comprising a terminal protection area and a cellular area;

the cell area comprises an IGBT cell area and a temperature sensing area;

4. The IGBT chip of claim 3, wherein the first and second thermistor regions are connected in series, in parallel, or in a combination thereof by the second and third electrodes.

5. The IGBT chip according to any one of claims 1 to 4, wherein the IGBT cell area comprises the substrate, a plurality of second well regions of the second conductivity type arranged at intervals in the substrate, source regions of the second conductivity type arranged in the second well regions, source regions of the first conductivity type arranged in the second well regions and at two sides of the source regions of the second conductivity type, a gate oxide layer arranged above the substrate between two adjacent second well regions and covering the substrate and the second well regions and the source regions of the first conductivity type in the second well regions, a gate electrode arranged above the gate oxide layer, and an emitter metal layer arranged above the substrate and electrically connected with the source regions of the first conductivity type and the source regions of the second conductivity type in the second well regions.

6. The IGBT chip according to any one of claims 1 to 4, wherein the IGBT cell area comprises the substrate, a plurality of gate trenches arranged at intervals in the substrate, a gate arranged in the gate trench, a gate oxide layer arranged between the gate trench and the gate, a second well region of the second conductivity type arranged between two adjacent gate trenches, a source region of the second conductivity type arranged in the second well region, source regions of the first conductivity type arranged in the second well region and at two sides of the source region of the second conductivity type, and an emitter metal layer arranged above the substrate and electrically connected with the source regions of the first conductivity type and the source regions of the second conductivity type in the second well region; the depth of the gate trench is greater than that of the second well region, and two ends of the first conduction type source region in the second well region are respectively connected with the gate trench and the second conduction type source region in the second well region.

7. The IGBT chip according to any one of claims 1 to 4, wherein the termination protection region comprises the substrate and field limiting rings spaced within the substrate.

8. A method for manufacturing an IGBT chip according to claim 1 or 2, characterized by comprising:

providing a first conductive type substrate;

depositing a polysilicon layer above the field oxide layer and the gate oxide layer, and etching the polysilicon layer to form a first polysilicon layer and a second polysilicon layer spaced from each other above the field oxide layer, respectively, and to form a gate above the gate oxide layer; wherein the gate is isolated from the second well region, the first conductivity type source region in the second well region, and the substrate by the gate oxide layer;

9. A method for preparing the IGBT chip according to claim 3 or 4, characterized by comprising:

providing a first conductive type substrate;