CN115632067A - IGBT device structure and preparation method thereof - Google Patents
IGBT device structure and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention provides an IGBT device structure and a preparation method thereof, wherein the IGBT device structure comprises: a substrate comprising opposing first and second faces; the IGBT body region is arranged in the IGBT drift region; an IGBT emitter region; arranged in the IGBT body region; the IGBT collector region is arranged on the second surface of the substrate; the IGBT grid electrode is arranged on the substrate and comprises a grid dielectric layer, a polycrystalline silicon layer positioned on the grid dielectric layer and a negative temperature coefficient material layer arranged on the polycrystalline silicon layer, the resistance of the polycrystalline silicon layer is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer is reduced along with the increase of the temperature in the working process of the device. The invention can keep the grid resistance of the IGBT device unchanged along with the temperature rise in the working process of the device, reduce the switching loss of the device and improve the application frequency of the IGBT device.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to an IGBT device structure and a preparation method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar junction Transistor) and MOS (Insulated Gate field effect Transistor). The IGBT device has the advantages of low saturation voltage, high current density, low driving power and high switching speed, and is suitable for a power supply management system with the withstand voltage of over 600V.
Fig. 1 shows that the gate resistance RG of the igbt fluctuates along with the junction temperature of the device, and it can be seen that the gate resistance RG of the device also increases with the increase of the junction temperature, and the gate resistance RG increases more significantly with the increase of the temperature. The increase in the resistance of the gate resistor RG increases the switching loss of the device, and particularly, the switching loss increases sharply in high frequency applications, thereby affecting the high frequency applications of the device.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide an IGBT device structure and a method for manufacturing the same, which are used to solve the problem that the gate resistance RG of the device increases with the increase of junction temperature, thereby causing large switching loss of the device in the prior art.
To achieve the above and other related objects, the present invention provides an IGBT device structure, including: a substrate comprising opposing first and second faces; the IGBT body region is arranged in the IGBT drift region; an IGBT emitter region; the IGBT body region is arranged in the IGBT body region; the IGBT collector region is arranged on the second surface of the substrate; the IGBT grid electrode is arranged on the substrate and comprises a grid dielectric layer, a polycrystalline silicon layer positioned on the grid dielectric layer and a negative temperature coefficient material layer arranged on the polycrystalline silicon layer, the resistance of the polycrystalline silicon layer is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer is reduced along with the increase of the temperature in the working process of the device.
Optionally, the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer are set so that the resistance of the polycrystalline silicon layer, which increases with the increase of the temperature during the operation of the device, is equal to the resistance of the negative temperature coefficient material layer, which decreases with the increase of the temperature during the operation of the device.
Optionally, the negative temperature coefficient material layer comprises Si, coO, niO, mnO, cuO, znO, mgO, fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 One or a combination of two or more of them.
The IGBT drift region is arranged between the IGBT collector region and the IGBT drift region.
The IGBT device further comprises an insulating layer, wherein a contact hole is formed in the insulating layer, metal layers are arranged on the contact hole and the insulating layer, and the metal layers are respectively connected with the emitting region and the negative temperature coefficient material layer connected with the IGBT grid electrode and embedded into the negative temperature coefficient material layer by a certain depth.
The IGBT device comprises a metal layer, a plurality of IGBT body regions and a plurality of IGBT emitting regions, an isolation structure is arranged between every two adjacent IGBT body regions, and the metal layer is connected with the plurality of IGBT emitting regions.
The IGBT grid is arranged in a ring shape and surrounds the periphery of the IGBT emitting area.
The invention also provides a preparation method of the IGBT device structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first side and a second side which are opposite; forming an IGBT body region in the IGBT drift region; forming an IGBT emitter region in the IGBT body region; forming an IGBT collector region on the second surface of the substrate; depositing a gate dielectric layer and a polysilicon layer on the substrate, forming an IGBT grid electrode through a first photoetching process and etching, depositing a negative temperature coefficient material layer, and reserving the negative temperature coefficient material layer on the IGBT grid electrode through a second photoetching process and etching, wherein the first photoetching process and the second photoetching process are realized on the basis of the same photomask, the resistance of the polysilicon layer is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer is reduced along with the increase of the temperature in the working process of the device.
Optionally, the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer are set so that the resistance of the polycrystalline silicon layer, which increases with the increase of the temperature during the operation of the device, is equal to the resistance of the negative temperature coefficient material layer, which decreases with the increase of the temperature during the operation of the device.
Optionally, the negative temperature coefficient material layer comprises Si, coO, niO, mnO, cuO, znO, mgO, fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 One or a combination of two or more of them.
Optionally, the preparation method further comprises the steps of: forming a field stop layer on a second surface of the substrate, wherein the field stop layer is arranged between the IGBT collector region and the IGBT drift region; and forming an insulating layer on the first surface of the substrate, forming a contact hole in the insulating layer, arranging metal layers on the contact hole and the insulating layer, wherein the metal layers are respectively connected with the emitting region and the negative temperature coefficient material layer connected with the IGBT grid electrode and are embedded into the negative temperature coefficient material layer for a certain depth.
The IGBT device comprises a metal layer, a plurality of IGBT body regions and a plurality of IGBT emitting regions, an isolation structure is arranged between every two adjacent IGBT body regions, and the metal layer is connected with the plurality of IGBT emitting regions.
The IGBT grid is arranged in a ring shape and surrounds the periphery of the IGBT emitting area.
As described above, the IGBT device structure and the method for manufacturing the same according to the present invention have the following beneficial effects:
according to the invention, the negative temperature coefficient material layer is arranged on the IGBT grid electrode and is jointly used as the grid electrode, and the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer are set, so that the resistance of the polycrystalline silicon layer, which is increased along with the increase of the temperature in the working process of the device, is equal to the resistance of the negative temperature coefficient material layer, which is decreased along with the increase of the temperature in the working process of the device, thereby keeping the grid resistance of the IGBT device unchanged along with the increase of the temperature in the working process of the device, reducing the switching loss of the device and improving the application frequency of the IGBT device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is to be understood that the drawings in the following description are of some embodiments of the application only.
Fig. 1 shows a schematic diagram of a variation curve of a gate resistance RG actually measured at different temperatures of a conventional IGBT device.
Fig. 2 to fig. 7 show schematic structural diagrams presented in steps of a method for manufacturing an IGBT device structure according to an embodiment of the present invention.
Fig. 8 is a schematic plan structure diagram of the IGBT device structure according to the embodiment of the present invention.
Fig. 9 shows the temperature versus switching loss for an IGBT device.
Description of the element reference numerals
101 IGBT drift region
102. Trench gate
103 IGBT body region
104 IGBT emitter region
105. Gate dielectric layer
106. Polycrystalline silicon layer
107. Negative temperature coefficient material layer
108. Insulating layer
109. Emitter metal
110. Grid metal
111 IGBT collector region
112. Collector electrode
113. Field stop layer
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 7, the present embodiment provides an IGBT device structure including: a substrate comprising opposing first and second faces; the IGBT drift region 101 is arranged on the first surface of the substrate, and the IGBT drift region 101 can be formed in the substrate by doping or formed by directly doping corresponding elements in the preparation process of the substrate; an IGBT body region 103 disposed in the IGBT drift region 101; an IGBT emitter region 104; is arranged in the IGBT body region 103; an IGBT collector region 111 provided on the second surface of the substrate; the IGBT grid electrode is arranged on the substrate and comprises a grid dielectric layer 105, a polycrystalline silicon layer 106 located on the grid dielectric layer 105 and a negative temperature coefficient material layer 107 arranged on the polycrystalline silicon layer 106, the resistance of the polycrystalline silicon layer 106 is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer 107 is reduced along with the increase of the temperature in the working process of the device.
In this embodiment, the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer 107 are set so that the resistance of the polysilicon layer 106, which increases with the increase of the temperature during the operation of the device, is equal to the resistance of the negative temperature coefficient material layer 107, which decreases with the increase of the temperature during the operation of the device, so that the gate resistance of the IGBT device remains unchanged with the increase of the temperature during the operation of the device, the switching loss of the device is reduced, and the application frequency of the IGBT device is increased.
In one embodiment, the substrate may be, for example, a silicon substrate, which may also include other semiconductors, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe), among others. The substrate may include a compound semiconductor and/or an alloy semiconductor such as gallium nitride, gallium arsenide, and the like. In addition, the substrate may also be strained to improve performance.
As shown in fig. 7, in one embodiment, the IGBT device further includes a field stop layer 113, and the field stop layer 113 is disposed between the IGBT collector region 111 and the IGBT drift region 101.
As shown in fig. 7, in an embodiment, the IGBT device further includes an insulating layer 108, a material of the insulating layer 108 may be, for example, silicon dioxide, silicon oxynitride, silicon nitride, etc., a contact hole is formed in the insulating layer 108, an emitter metal 109 and a gate metal 110 are disposed on the contact hole and the insulating layer 108, wherein the emitter metal 109 and the gate metal 110 may be formed by etching the same metal layer, the material of the emitter metal 109 and the gate metal 110 may be, for example, copper, aluminum, gold, titanium nitride, tantalum nitride, or a combination thereof, the emitter metal 109 connects to the IGBT emitter region, the gate metal 110 connects to the negative temperature coefficient material layer 107 of the IGBT gate, and the gate metal 110 is embedded into the negative temperature coefficient material layer 107 by a depth, so as to increase a contact area between the gate metal 110 and the negative temperature coefficient material layer 107, and reduce contact resistance.
As shown in fig. 7, in one embodiment, the IGBT body region 103 and the IGBT emitter region 104 are provided in plural, and the emitter metal is simultaneously connected to the plurality of IGBT emitter regions 104, so as to improve the current density of the IGBT device and improve the driving capability of the IGBT device.
As shown in fig. 8, in one embodiment, the IGBT gate is configured in a ring shape, such as a rectangular ring, a rounded rectangular ring, an elliptical ring, a circular ring, etc., and the IGBT gate surrounds the periphery of the IGBT emitter region 104.
The polysilicon layer 106 of the IGBT gate is doped with impurities with different polarities to adjust the work function thereof, so as to adjust the threshold voltage of the IGBT device, for example, phosphorus oxychloride (POCl) 3 ) In-situ doping is performed, and the electrical characteristics of the polysilicon layer 106 are subjected to temperature variation after dopingThe resistance of the negative temperature coefficient material layer 107 of the present application decreases with the temperature increase during the device operation process, so that the resistance of the polysilicon layer 106 that increases with the temperature increase during the device operation process is equal to the resistance of the negative temperature coefficient material layer 107 that decreases with the temperature increase during the device operation process, thereby keeping the gate resistance of the IGBT device constant with the temperature increase during the device operation process, reducing the device switching loss, and increasing the application frequency of the IGBT device. In one embodiment, the negative temperature coefficient material layer 107 includes Si, coO, niO, mnO, cuO, znO, mgO, fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 2 Or a combination of two or more thereof.
In one embodiment, the IGBT drift region 101 is lightly doped N-type, the IGBT body region 103 is doped P-type, the IGBT emitter region 104 is heavily doped N-type, the field stop layer 113 is doped N-type with a doping concentration greater than that of the IGBT drift region 101, the IGBT collector region 111 is heavily doped P-type, and the IGBT collector region 111 is further formed with a collector 112.
Fig. 9 shows a temperature-switching loss relationship curve of the IGBT device, where the curve Etotal-1 is a temperature-switching loss relationship curve of the conventional IGBT device, and the curve Etotal-2 is a temperature-switching loss relationship curve of the IGBT device of this embodiment, as can be seen from fig. 9, this embodiment can effectively reduce the switching loss of the IGBT.
As shown in fig. 2 to fig. 8, this embodiment further provides a method for manufacturing an IGBT device structure, and the basic structure of the IGBT device structure can refer to the above embodiment, where the method includes the following steps:
as shown in fig. 2, step 1) is first performed to provide a substrate, where the substrate includes a first side and a second side opposite to the first side; an IGBT body region 103 is formed in the IGBT drift region 101.
As shown in fig. 3, then step 2) is performed to form an IGBT emitter region 104 in the IGBT body region 103;
as shown in fig. 4 to 5, step 3) is then performed, a gate dielectric layer 105 and a polysilicon layer 106 are deposited on the substrate, an IGBT gate is formed through a first photolithography process and etching, a negative temperature coefficient material layer 107 is deposited, and the negative temperature coefficient material layer 107 on the IGBT gate is remained through a second photolithography process and etching, wherein the first photolithography process and the second photolithography process are implemented based on the same photomask, the resistance of the polysilicon layer 106 increases with the increase of temperature during the operation of the device, and the resistance of the negative temperature coefficient material layer 107 decreases with the increase of temperature during the operation of the device.
As shown in fig. 6, step 4) is then performed to form an insulating layer 108 on the first surface of the substrate, form a contact hole in the insulating layer 108, dispose a metal layer on the contact hole and the insulating layer 108, connect the emitter metal to the emitter region, connect the gate metal to the negative temperature coefficient material layer 107 of the IGBT gate, and embed the gate metal into the negative temperature coefficient material layer 107 by a certain depth.
As shown in fig. 7, step 5) is finally performed to form a field stop layer 113 on the second surface of the substrate, and form an IGBT collector region 111 on the second surface of the substrate, where the field stop layer 113 is disposed between the IGBT collector region 111 and the IGBT drift region 101.
In one embodiment, the negative temperature coefficient, resistivity and thickness of the negative temperature coefficient material layer 107 are set such that the resistance of the polysilicon layer 106 that increases with increasing temperature during device operation is equal to the resistance of the negative temperature coefficient material layer 107 that decreases with increasing temperature during device operation.
In one embodiment, the negative temperature coefficient material layer 107 includes Si, coO, niO, mnO, cuO, znO, mgO, fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 2 Or a combination of two or more thereof.
In one embodiment, the IGBT gate is arranged in a ring shape, and the IGBT gate surrounds the periphery of the IGBT emitter region 104.
As described above, the IGBT device structure and the method for manufacturing the same according to the present invention have the following beneficial effects:
according to the invention, the negative temperature coefficient material layer 107 is arranged on the IGBT gate to be used as the gate together, and the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer 107 are arranged, so that the resistance of the polycrystalline silicon layer 106, which is increased along with the increase of the temperature in the working process of the device, is equal to the resistance of the negative temperature coefficient material layer 107, which is decreased along with the increase of the temperature in the working process of the device, thereby keeping the gate resistance of the IGBT device unchanged along with the increase of the temperature in the working process of the device, reducing the switching loss of the device and improving the application frequency of the IGBT device.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (13)
1. An IGBT device structure, characterized in that the IGBT device structure comprises:
a substrate comprising opposing first and second faces;
the IGBT body region is arranged in the IGBT drift region;
an IGBT emitter region; the IGBT body region is arranged in the IGBT body region;
the IGBT collector region is arranged on the second surface of the substrate;
the IGBT grid electrode is arranged on the substrate and comprises a grid dielectric layer, a polycrystalline silicon layer positioned on the grid dielectric layer and a negative temperature coefficient material layer arranged on the polycrystalline silicon layer, the resistance of the polycrystalline silicon layer is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer is reduced along with the increase of the temperature in the working process of the device.
2. The IGBT device structure of claim 1, wherein: the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer are set so that the resistance of the polycrystalline silicon layer, which increases with the increase of the temperature in the working process of the device, is equal to the resistance of the negative temperature coefficient material layer, which decreases with the increase of the temperature in the working process of the device.
3. The IGBT device structure of claim 1, wherein: the negative temperature coefficient material layer comprises Si, coO, niO, mnO, cuO, znO, mgO and Fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 Or a combination of two or more thereof.
4. The IGBT device structure of claim 1, wherein: the IGBT drift region is arranged between the IGBT collector region and the IGBT drift region.
5. The IGBT device structure of claim 1, wherein: the IGBT device further comprises an insulating layer, wherein a contact hole is formed in the insulating layer, metal layers are arranged on the contact hole and the insulating layer, and the metal layers are respectively connected with the emitting region and the negative temperature coefficient material layer connected with the IGBT grid electrode and embedded into the negative temperature coefficient material layer by a certain depth.
6. The IGBT device structure of claim 5, wherein: the IGBT device comprises a metal layer, a plurality of IGBT body regions and a plurality of IGBT emitting regions, an isolation structure is arranged between every two adjacent IGBT body regions, and the metal layer is connected with the plurality of IGBT emitting regions.
7. The IGBT device structure of claim 1, wherein: the IGBT grid is arranged in a ring shape and surrounds the periphery of the IGBT emitting region.
8. A preparation method of an IGBT device structure is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a first side and a second side which are opposite;
forming an IGBT drift region on the first surface of the substrate;
forming an IGBT body region in the IGBT drift region;
forming an IGBT emitter region in the IGBT body region;
forming an IGBT collector region on the second surface of the substrate;
depositing a gate dielectric layer and a polysilicon layer on the substrate, forming an IGBT gate through a first photoetching process and etching, depositing a negative temperature coefficient material layer, and reserving the negative temperature coefficient material layer on the IGBT gate through a second photoetching process and etching, wherein the first photoetching process and the second photoetching process are realized on the basis of the same photomask, the resistance of the polysilicon layer is increased along with the increase of the temperature in the working process of the device, and the resistance of the negative temperature coefficient material layer is reduced along with the increase of the temperature in the working process of the device.
9. The method of manufacturing an IGBT device structure according to claim 8, characterized in that: the negative temperature coefficient, the resistivity and the thickness of the negative temperature coefficient material layer are set so that the resistance of the polycrystalline silicon layer, which increases with the increase of the temperature in the working process of the device, is equal to the resistance of the negative temperature coefficient material layer, which decreases with the increase of the temperature in the working process of the device.
10. The method for manufacturing an IGBT device structure according to claim 8, characterized in that: the negative temperature coefficient material layer comprises Si, coO, niO, mnO, cuO, znO, mgO and Fe 2 O 3 、Cr 2 O 3 、Al 2 O 3 、ZrO 2 And TiO 2 One or two ofCombinations of the above.
11. The method for manufacturing an IGBT device structure according to claim 8, characterized in that: further comprising the steps of:
forming a field stop layer on a second surface of the substrate, wherein the field stop layer is arranged between the IGBT collector region and the IGBT drift region of the IGB drift region;
and forming an insulating layer on the first surface of the substrate, forming a contact hole in the insulating layer, and arranging metal layers on the contact hole and the insulating layer, wherein the metal layers are respectively connected with the emitting region and the negative temperature coefficient material layer connected with the IGBT grid electrode and are embedded into the negative temperature coefficient material layer for a certain depth.
12. The method of manufacturing an IGBT device structure according to claim 11, characterized in that: the IGBT device comprises a metal layer, a plurality of IGBT body regions and a plurality of IGBT emitting regions, an isolation structure is arranged between every two adjacent IGBT body regions, and the metal layer is connected with the plurality of IGBT emitting regions.
13. The method for manufacturing an IGBT device structure according to claim 8, characterized in that: the IGBT grid is arranged in a ring shape and surrounds the periphery of the IGBT emitting area.
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| WO2017029748A1 (en) * | 2015-08-20 | 2017-02-23 | 株式会社日立製作所 | Semiconductor device, power module, power converter, vehicle, and train carriage |
| CN111954931A (en) * | 2018-03-28 | 2020-11-17 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN113035950A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | IGBT chip and preparation method thereof |
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| CN102024793A (en) * | 2009-08-25 | 2011-04-20 | 英飞凌科技奥地利有限公司 | Semiconductor component |
| WO2017029748A1 (en) * | 2015-08-20 | 2017-02-23 | 株式会社日立製作所 | Semiconductor device, power module, power converter, vehicle, and train carriage |
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Application publication date: 20230120 |