CN115588614A - Preparation method of trench gate IGBT, trench gate IGBT and chip - Google Patents

Preparation method of trench gate IGBT, trench gate IGBT and chip Download PDF

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Publication number
CN115588614A
CN115588614A CN202211350011.3A CN202211350011A CN115588614A CN 115588614 A CN115588614 A CN 115588614A CN 202211350011 A CN202211350011 A CN 202211350011A CN 115588614 A CN115588614 A CN 115588614A
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layer
region
photomask
forming
drift layer
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杨磊
刘杰
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Shenzhen Xiner Semiconductor Technology Co Ltd
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Shenzhen Xiner Semiconductor Technology Co Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The invention belongs to the technical field of power devices and provides a trench gate IGBT, a preparation method thereof and a chip. And forming an alignment mark on the surface of the wafer by using the photomask, determining a scribing way and a chip area, and facilitating alignment of each layer of photomask. Then injecting P-type doping ions to the front side of the drift layer under the covering of the isolation layer in the terminal area to form a plurality of P-type rings in the terminal area, forming a plurality of grooves in the cellular area, forming a gate oxide layer in each groove, depositing a polysilicon material to form a polysilicon layer, injecting P-type doping ions to the front side of the drift layer to form a P-type well region, then injecting N-type doping ions to form an N-type source region and a stop ring region, injecting P-type doping ions from a contact hole on the dielectric layer to form an ohmic contact impurity layer on the N-type source region, depositing a metal material to obtain a gate electrode, an emission electrode and a terminal metal layer, and forming an IGBT structure under the condition of not using a polysilicon photomask by designing a novel process and a novel structure, thereby saving the polysilicon photomask.

Description

Preparation method of trench gate IGBT, trench gate IGBT and chip
Technical Field
The invention belongs to the technical field of power devices, and particularly relates to a preparation method of a trench gate IGBT, the trench gate IGBT and a chip.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic power device formed by combining a Bipolar Junction Transistor (BJT) and a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The IGBT has the characteristics of simple control and high input impedance of the MOSFET, has the characteristics of reduced on-state voltage and large current capacity of the BJT, and is widely applied to the fields of new energy, medical treatment, industrial automation, rail transit and the like.
Since the birth of the IGBT, improving the performance and reducing the cost have been the development direction of the IGBT technology. In order to reduce the conduction voltage drop of the IGBT, the groove gate structure is applied to the IGBT device, a transverse channel is changed into a longitudinal channel, so that the groove gate structure is formed, the JFET (junction field effect transistor) resistance can be eliminated, the cell size is reduced, the cell density is improved, the channel resistance is reduced, and the performance which is more excellent than that of a planar gate is obtained.
However, in the existing trench gate IGBT device, polysilicon needs to be modified by designing a polysilicon etching mask, which not only results in a complex preparation process, but also increases the production cost of the device.
Disclosure of Invention
The invention aims to provide a preparation method of a trench gate IGBT, the trench gate IGBT and a chip, and aims to solve the problems that in an existing trench gate IGBT device, due to the fact that polysilicon needs to be modified by designing a polysilicon etching photomask, the preparation process is complex, and the production cost of the device is increased.
The first aspect of the embodiments of the present invention provides a method for manufacturing a trench gate IGBT, where the method includes:
forming an alignment mark at a preset position on the front surface of the drift layer by using a first photomask; the alignment mark is used for determining a chip area, and the chip area comprises a cellular area and a terminal area;
forming a thermal oxide layer on the front surface of the drift layer, and etching the thermal oxide layer under a second photomask to form an isolation layer with a preset pattern; wherein the isolation layer is located within the termination region;
injecting P-type doped ions into the front surface of the drift layer by taking a third photomask as a mask so as to form a plurality of P-type rings in the terminal area;
forming a plurality of grooves on the front surface of the drift layer by adopting a fourth photomask, and forming a gate oxide layer in each groove; wherein a plurality of the trenches are located in the cell region;
depositing a polycrystalline silicon material on the front surface of the drift layer, and etching the polycrystalline silicon material to form a polycrystalline silicon layer in the groove;
injecting P-type doped ions into the front surface of the drift layer to form a P-type well region, and injecting N-type doped ions into the front surface of the drift layer by adopting a fifth photomask to form an N-type source region and a stop ring region;
forming a dielectric layer, and forming a contact hole on the dielectric layer by adopting a sixth photomask;
injecting P-type doped ions into the contact hole by taking the dielectric layer as a mask to form an ohmic contact impurity layer, depositing a metal material, and etching the metal material under the covering of a seventh photomask to obtain a gate electrode, an emission electrode and a terminal metal layer; the emitting electrode is in contact with the ohmic contact impurity layer, and the terminal metal layer is in contact with the P-type ring and the cut-off ring region;
and forming a buffer layer on the back surface of the drift layer, injecting P-type doped ions into the back surface of the buffer layer to form a collector region, and sputtering a metal material on the collector region to form a collector.
In one embodiment, the doping concentration of the P-type ring is greater than the doping concentration of the P-type well region.
In one embodiment, the depth of the P-type ring is greater than the depth of the P-type well region.
In one embodiment, the forming of the alignment mark at the predetermined position on the front surface of the drift layer by using the first photomask includes:
and forming the alignment mark in the scribing street of the drift layer by adopting the first photomask, wherein the alignment mark is positioned in the diagonal area of the scribing street, and the chip area is surrounded by the scribing street.
In one embodiment, said forming a plurality of trenches on the front surface of said drift layer and a gate oxide layer in each of said trenches with a fourth mask includes:
etching the drift layer under the cover of the fourth photomask to form a plurality of grooves in a cellular area on the drift layer;
and forming the gate oxide layer on the surface of each groove in a thermal oxidation mode.
In one embodiment, the depositing a polysilicon material on the front surface of the drift layer and performing an etching process on the polysilicon material to form a polysilicon layer in the trench includes:
and depositing polycrystalline silicon on the front surface of the drift layer, and etching the polycrystalline silicon material on the surface of the drift layer under the photomask-free condition until the drift layer is exposed so as to retain the polycrystalline silicon in the groove.
In one embodiment, the forming a dielectric layer and forming a contact hole on the dielectric layer by using a sixth mask includes:
forming the dielectric layer in a cellular region on the front surface of the drift layer by depositing silicon nitride or silicon oxide;
etching the dielectric layer under the cover of the fifth photomask to form a plurality of contact holes on the dielectric layer;
wherein the contact holes are arranged between adjacent trenches.
In one embodiment, the depositing the metal material and etching the metal material under the mask of the seventh mask to obtain the gate electrode, the emitter electrode and the terminal metal layer includes:
depositing a metal material on the dielectric layer, and etching the metal material under the cover of the seventh photomask to form a gate electrode and an emitter electrode in the cell area and a terminal metal layer in the terminal area;
wherein the emitter electrode is positioned above the polysilicon layer, and the emitter electrode is in contact with the ohmic contact impurity layer.
The second aspect of the embodiments of the present application further provides a trench gate IGBT prepared by the preparation method as described in any one of the above.
The third aspect of the embodiments of the present application further provides a chip, where the chip includes the trench gate IGBT as described above; or the chip comprises the trench gate IGBT prepared by the preparation method.
The embodiment of the application provides a trench gate IGBT (insulated gate bipolar transistor), a preparation method thereof and a chip, wherein an alignment mark is formed at a preset position on the front surface of a drift layer by adopting a first photomask to determine a chip area comprising a cellular area and a terminal area, then an isolation layer with a preset pattern is formed in the terminal area, P-type doping ions are injected to the front surface of the drift layer under the covering of the isolation layer to form a plurality of P-type rings in the terminal area, a plurality of grooves are formed in the cellular area, a gate oxide layer is formed in each groove, a polycrystalline silicon material is deposited in each groove, a polycrystalline silicon layer is formed in each groove, P-type doping ions are injected to the front surface of the drift layer to form a P-type well region, then N-type doping ions are injected to form an N-type source region and a stop ring region, P-type doping ions are injected to form an ohmic contact impurity layer on the N-type source region through a contact hole on a dielectric layer, a metal material is deposited to obtain a gate electrode, an emission electrode and a terminal metal layer, an IGBT structure is formed without using a polycrystalline silicon mask, the problem that the performance of the IGBT is not influenced is saved, and the problem that the process of the IGBT structure is complicated and the polycrystalline silicon etching process is high in need is solved.
Drawings
Fig. 1 is a schematic flow diagram of a method for manufacturing a trench gate IGBT according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of forming an alignment mark according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a chip region 200 according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a trench gate IGBT according to an embodiment of the present invention.
Fig. 5 is a schematic top view of a trench gate IGBT according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the existing trench gate IGBT device, polysilicon needs to be modified by designing a polysilicon etching photomask, so that the preparation process is complex, and the production cost of the device is increased.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a trench gate IGBT, and referring to fig. 1, the method in the embodiment includes steps S100 to S900.
In step S100, an alignment mark is formed at a predetermined position on the front surface of the drift layer by using a first mask.
Specifically, referring to fig. 2, an alignment mark 101 is formed at a predetermined position of the drift layer for position reference in a subsequent process step, wherein the alignment mark 101 is used to determine a scribe lane 102 and set a reference for a dicing process of a subsequent device, and a chip region 200 is surrounded by the scribe lane 102.
In one embodiment, the step S100 of forming the alignment mark at the predetermined position on the front surface of the drift layer by using the first mask includes: and forming the alignment mark in the scribing channel of the drift layer by adopting the first photomask.
In this embodiment, as shown in fig. 2, the alignment mark 101 is located in a diagonal region of the scribe lane 102, the chip region 200 of the trench gate IGBT is surrounded by the scribe lane 102, and the scribe lane 102 is arranged in a grid on the drift layer.
In the present embodiment, the position of the alignment mark 101 is determined by the first photomask, for example, the alignment mark is formed by etching a designated region on the front surface of the drift layer, the alignment mark 101 is disposed in a diagonal region of the scribe lane 102, the scribe lane 102 is used for cutting the chip substrate, the chip region 200 of each trench gate IGBT is surrounded by the scribe lane 102, and as shown in fig. 3, the chip region 200 includes a cell region 201 and a terminal region 202, and the cell region 201 is surrounded by the terminal region 202.
In step S200, a thermal oxide layer is formed on the front surface of the drift layer, and the thermal oxide layer is etched under a second mask to form an isolation layer with a predetermined pattern.
In the present embodiment, as shown in fig. 4, the isolation layer 502 is disposed in the terminal region 202 in the chip region 200, and a plurality of bar-shaped through holes are disposed on the isolation layer.
Specifically, a thermal oxide layer is formed on the drift layer 401, and then the thermal oxide layer is etched under the cover of the second mask to form the isolation layer 502 with a preset pattern.
In one embodiment, the plurality of stripe-shaped vias on the isolation layer 502 are arranged in parallel.
In one embodiment, the plurality of stripe-shaped vias on the isolation layer 502 are parallel to the scribe lanes 102.
In step S300, P-type dopant ions are implanted into the front surface of the drift layer to form a P-type ring by using the third mask as a mask.
In this embodiment, as shown in fig. 4, the position of the P-type ring 301 is determined by using the third mask as a mask, the cell region 201 and the predetermined stop ring region are covered by the third mask, and then P-type doped ions are implanted into the drift layer 401 through the strip-shaped through hole on the isolation layer 502 to form the P-type ring 301 by implanting the P-type doped ions into the front surface of the drift layer 401. Specifically, the P-type rings 301 are located in the termination region 202, and the dotted line B in fig. 4 indicates that the number of P-type rings 301 may be plural, the distance between adjacent P-type rings 301 is L1, and the P-type rings 301 near the boundary between the termination region 202 and the cell region 201 are in contact with the P-type well region 407.
In one embodiment, the bar-shaped through hole is located in a central region of the P-type ring 301, and the P-type ring 301 may be axially symmetrically disposed with respect to the bar-shaped through hole.
In some embodiments, the doping ions in the P-type ring 301 are of a different type than the doping ions in the drift layer 401, e.g., the P-type ring 301 is P-type doped and the drift layer 401 is N-type doped.
In some embodiments, the N-type dopant ions doped in the drift layer 401 may be phosphorous ions, nitrogen ions, or the like.
In some embodiments, the P-type dopant ions doped in the P-type ring 301 may be aluminum ions, boron ions, or the like.
In step S400, a fourth mask is used to form a plurality of trenches on the front surface of the drift layer, and a gate oxide layer is formed in each of the trenches.
In this embodiment, as shown in fig. 4, a fourth mask may be used to mask the cell regions 201, and the fourth mask determines the positions of the trenches, and a plurality of trenches are formed in the cell regions 201 on the front surface of the drift layer 401 by etching the drift layer 401, and a gate oxide layer 405 is formed in each trench by extending the plurality of trenches into the drift layer 401.
In a specific application embodiment, the drift layer 401 may serve as a drift region, and the doping type thereof is N-type doping.
In one embodiment, in step S400, forming a plurality of trenches on the front surface of the drift layer by using a fourth mask, and forming a gate oxide layer in each of the trenches, specifically includes: etching the drift layer 401 under the cover of the fourth mask to form a plurality of trenches in the cell region 201 on the drift layer 401; a gate oxide layer 405 is formed on the surface of each trench by means of thermal oxidation.
In this embodiment, the trench position is determined by a fourth mask, and then the cell region 201 on the front surface of the drift layer 401 is etched under the coverage of the fourth mask to form a plurality of trenches in the cell region 201 on the front surface of the drift layer 401, and further, the inner surface of each trench is oxidized by thermal oxidation to obtain silicon oxide, which is used as the gate oxide layer 405.
In some embodiments, the plurality of grooves are arranged in parallel.
In some embodiments, the distance between adjacent trenches is equal.
In some embodiments, the width of the trench is 0.1-0.5um.
In some embodiments, the width of the trench in the cell region 201 is less than the width of the P-type ring 301 in the termination region 202.
In step S500, a polysilicon material is deposited on the front surface of the drift layer 401, and the polysilicon material is etched to form a polysilicon layer 406 in the trench.
In this embodiment, as shown in fig. 4, a polysilicon material is deposited on the front surface of the drift layer 401 formed in step S400, then the polysilicon material on the front surface of the drift layer 401 is removed, only the polysilicon material in the trench is retained, and a polysilicon layer 406 is formed in the trench, at this time, only the polysilicon material in the trench is disposed in the IGBT device, and all the polysilicon material in the terminal region 202 is removed by etching, so that after the deposition of the polysilicon material, etching with a photomask is not required, and all etching is performed directly, thereby omitting a photomask and one-time photolithography, and greatly saving the cost.
In this embodiment, step S500 specifically includes: and depositing a polysilicon material on the front surface of the drift layer 401, and performing non-differential etching treatment on the polysilicon material on the front surface of the drift layer 401 under the photomask-free condition until the drift layer 401 is exposed so as to retain the polysilicon material in the groove.
In this embodiment, the polysilicon material deposited on the front surface of the drift layer 401 is etched indiscriminately until the front surface of the drift layer 401 is exposed, and at this time, because the etching rates are the same, the polysilicon in the trench is retained, and the polysilicon material deposited in the termination region 202 is completely removed, and only the polysilicon material in the trench is retained, thereby forming the polysilicon layer 406 in the trench.
In step S600, P-type doped ions are implanted into the front surface of the drift layer 401 to form a P-type well region 407, and N-type doped ions are implanted into the front surface of the drift layer 401 by using a fifth mask to form an N-type source region 408 and a stop ring region 302.
In the present embodiment, the N-type source region 408 is located on the P-well region 407, since the drift layer 401 has a plurality of trenches on the front surface thereof for filling the polysilicon material to form the polysilicon layer 406, the P-well region 407 is divided into a plurality of sub-well regions, and the N-type source regions 408 are respectively located on the P-well regions 407.
The stop ring region 302 is located at an edge of the termination region 202, at this time, the stop ring region 302 and the P-well region 407 are located at two sides of the P-type ring 301, a plurality of P-type rings 301 are disposed between the stop ring region 302 and the P-well region 407, and a distance between the stop ring region 302 and its adjacent P-type ring 301 is greater than a distance between the adjacent P-type rings 301.
In one embodiment, as shown in fig. 4, the distance between the stop ring area 302 and the adjacent P-type ring 301 is L2, the distance between the adjacent P-type rings 301 is L1, and L2 is greater than L1.
In one embodiment, L2 is at least three times L1.
In some embodiments, the depth of P-well 407 may be 0.1-0.7um.
In some embodiments, the thickness of P-type well region 407 is less than the distance between adjacent trenches. In a specific embodiment, aluminum ions are implanted into the front surface of the drift layer 401, and the aluminum ions enter the drift layer 401 through the region of the drift layer between adjacent trenches, so that a P-type well region 407 is formed in the drift layer 401, and a PN junction is formed between the P-type well region 407 and the drift layer 401.
In one embodiment, the thickness of P-type well region 407 is less than the thickness of polysilicon layer 406.
In one embodiment, under the masking of the fifth mask, phosphorus ions or nitrogen ions are implanted into the front surface of the drift layer 401 to form the N-type source region 408 and the stop ring region 302.
In one embodiment, the thickness of N-type source region 408 is less than one-half the thickness of P-type well region 407.
In one embodiment, the doping concentration of the P-type ring 301 is greater than the doping concentration of the P-type well region 407.
In one embodiment, the doping concentration of the P-type ring 301 is at least every 10 times the doping concentration of the P-type well region 407.
In one embodiment, the thickness of the P-type ring 301 is greater than the thickness of the P-type well region 407.
In step S700, a dielectric layer 501 is formed, and a contact hole is formed on the dielectric layer 501 using a sixth mask.
In this embodiment, as shown in fig. 4, a dielectric layer 501 is formed on the N-type source region 408 and the polysilicon layer 406, the position of the contact hole on the dielectric layer 501 is determined by a sixth mask, and then the dielectric layer 501 is etched under the mask of the sixth mask to form a plurality of contact holes on the dielectric layer 501, wherein the contact holes extend into the P-type well region 407, at this time, the N-type source region 408 between adjacent polysilicon layers 406 is divided into two parts, and the two parts of the N-type source region 408 are located on two sides of the contact hole respectively.
In one embodiment, a dielectric layer 501 covers the N-type source region 408, the polysilicon layer 406, and the gate oxide layer 405, and the contact holes are located between adjacent sub-well regions.
In some embodiments, in step S700, a dielectric layer 501 may be formed on the surfaces of the N-type source region 408 and the polysilicon layer 406 by depositing a silicon nitride material or a silicon oxide, and then the dielectric layer 501 is etched under the cover of the sixth mask to form a plurality of contact holes.
In step S800, as shown in fig. 4 and 5, P-type dopant ions are implanted into the contact holes using the dielectric layer 501 as a mask to form an ohmic contact impurity layer 409, a metal material is deposited, and the metal material is etched under the mask of a seventh mask to form a gate electrode 530, an emitter electrode 521, and a termination metal layer 522.
In this embodiment, gate electrode 530 is disposed on dielectric layer 501, and in this case, dielectric layer 501 is disposed between gate electrode 530 and drift layer 401, i.e. there is neither P-type well region 407 nor polysilicon layer 406 under gate electrode 530, and emitter electrode 521 covers dielectric layer 501 over P-type well region 407 and polysilicon layer 406.
In one embodiment, the emitter electrode 521 is in contact with the ohmic contact impurity layer 409, and the terminal metal layer 522 is in contact with the P-type ring 301 and the cutoff ring region 302.
In this embodiment, there are a plurality of terminal metal layers 522, and the plurality of terminal metal layers 522 are respectively connected to the plurality of P-type rings 301 and the stop ring area 302.
In one embodiment, terminal metal layer 522 is L-shaped in vertical cross-section, as shown in fig. 4, and terminal metal layer 522 is rectangular in horizontal cross-section, as shown in fig. 5.
In one embodiment, the plurality of terminal metal layers 522 are horizontally disposed.
In one embodiment, the plurality of terminal metal layers 522 may be connected to different voltages, so that the electric field of the terminal region 202 is adjusted by connecting different voltages, for example, the cut-off ring region 302 is connected to an external voltage through its corresponding terminal metal layer 522, so as to ensure that there is no potential difference at the chip edge even when the chip edge is subjected to a high voltage, and at this time, the electric field is cut off at the cut-off ring region 302.
In one embodiment, the plurality of P-type rings 301 are coupled to an external voltage through their corresponding terminal metal layers 522 to direct the electric field in the P-type rings 301 to the outside, thereby improving the curvature of the device.
In one embodiment, the external voltage applied to the terminal metal layer 522 correspondingly connected to the P-type rings 301 gradually increases from the region near the cell region 201 to the region far from the cell region 201.
In one embodiment, the voltage values of the external voltages applied to the terminal metal layers 522 connected to the P-type rings 301 are arranged in an equal difference manner.
In one embodiment, the thickness of the isolation layer 502 is greater than the thickness of the dielectric layer 501.
In one embodiment, the thickness of the isolation layer 502 is 120um.
In step S900, a buffer layer 402 is formed on the back surface of the drift layer 401, P-type dopant ions are implanted into the back surface of the buffer layer 402 to form a collector region 403, and a collector 523 is formed by sputtering a metal material on the collector region 403.
In the present embodiment, the buffer layer 402 is provided between the collector region 403 and the drift layer 401, and the collector region 403 is provided between the buffer layer 402 and the collector 523.
In one embodiment, the doping concentration of the drift layer 401 is less than the doping concentration of the buffer layer 402.
In one embodiment, the drift layer 401 and the buffer layer 402 are doped with N-type dopant ions.
The embodiment of the application also provides a trench gate IGBT, and the trench gate IGBT is prepared by the preparation method of any one of the above.
In the embodiment, a chip region of a trench gate IGBT is composed of a cell region and a terminal region, the cell region is surrounded by the terminal region, P-type doping ions are injected to the front surface of a drift layer under the covering of an isolation layer in the terminal region to form a plurality of P-type rings in the terminal region, a plurality of trenches are formed in the cell region, a gate oxide layer is formed in each trench, a polycrystalline silicon material is deposited to form a polycrystalline silicon layer, P-type doping ions are injected to the front surface of the drift layer to form a P-type well region, then N-type doping ions are injected to form an N-type source region and a stop ring region, P-type doping ions are injected from a contact hole in a dielectric layer to form an ohmic contact layer on the N-type source region, and a metal material is deposited to obtain a gate electrode, an emitter electrode and a terminal metal layer.
The embodiment of the application further provides a chip, and the chip comprises the trench gate IGBT.
In one embodiment, the chip comprises the trench gate IGBT prepared by the preparation method described in any one of the above.
In this embodiment, an integrated circuit is disposed in a chip, the trench gate IGBT is applied to the integrated circuit, the integrated circuit is formed on a wafer substrate, and the trench gate IGBT in the integrated circuit may be the trench gate IGBT according to any of the embodiments.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the above division of the doped regions is merely illustrated, and in practical applications, the above functional region allocation can be performed by different doped regions according to needs, that is, the internal structure of the device is divided into different doped regions to perform all or part of the above-described functions.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist alone physically, or two or more doped regions are integrated in one functional region, and the integrated functional regions may be implemented by using the same type of doped ions, or may be implemented by using multiple types of doped ions together. In addition, the specific names of the doped regions are only for the convenience of distinguishing from each other, and are not used to limit the scope of the present application. For a specific working process of the middle doped region in the method for manufacturing the device, reference may be made to a corresponding process in the foregoing method embodiment, which is not described herein again.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.

Claims (10)

1. A preparation method of a trench gate IGBT is characterized by comprising the following steps:
forming an alignment mark at a preset position on the front surface of the drift layer by adopting a first photomask; the alignment mark is used for determining a chip area, and the chip area comprises a cellular area and a terminal area;
forming a thermal oxidation layer on the front surface of the drift layer, and etching the thermal oxidation layer under a second photomask to form an isolation layer with a preset pattern; wherein the isolation layer is located within the termination region;
injecting P-type doped ions into the front surface of the drift layer by taking a third photomask as a mask so as to form a plurality of P-type rings in the terminal region;
forming a plurality of grooves on the front surface of the drift layer by adopting a fourth photomask, and forming a gate oxide layer in each groove; wherein a plurality of the trenches are located in the cell region;
depositing a polycrystalline silicon material on the front surface of the drift layer, and etching the polycrystalline silicon material to form a polycrystalline silicon layer in the groove;
injecting P-type doped ions into the front surface of the drift layer to form a P-type well region, and injecting N-type doped ions into the front surface of the drift layer by adopting a fifth photomask to form an N-type source region and a stop ring region;
forming a dielectric layer, and forming a contact hole on the dielectric layer by adopting a sixth photomask;
injecting P-type doped ions into the contact hole by taking the dielectric layer as a mask to form an ohmic contact impurity layer, depositing a metal material, and etching the metal material under the covering of a seventh photomask to obtain a gate electrode, an emission electrode and a terminal metal layer; the emitting electrode is in contact with the ohmic contact impurity layer, and the terminal metal layer is in contact with the P-type ring and the cut-off ring region;
and forming a buffer layer on the back surface of the drift layer, injecting P-type doped ions into the back surface of the buffer layer to form a collector region, and sputtering a metal material on the collector region to form a collector.
2. The method of claim 1, wherein a doping concentration of the P-type ring is greater than a doping concentration of the P-type well region.
3. The method of claim 2, wherein a depth of the P-type ring is greater than a depth of the P-type well region.
4. The method according to any one of claims 1 to 3, wherein the forming of the alignment mark at the predetermined position on the front surface of the drift layer by using the first mask comprises:
and forming the alignment mark in the scribing street of the drift layer by adopting the first photomask, wherein the alignment mark is positioned in the diagonal area of the scribing street, and the chip area is surrounded by the scribing street.
5. The method of any of claims 1-3, wherein said forming a plurality of trenches in a front surface of said drift layer and a gate oxide layer in each of said trenches using a fourth mask comprises:
etching the drift layer under the cover of the fourth photomask to form a plurality of grooves in a cellular area on the drift layer;
and forming the gate oxide layer on the surface of each groove in a thermal oxidation mode.
6. The method according to claim 1, wherein depositing a polysilicon material on the front surface of the drift layer and etching the polysilicon material to form a polysilicon layer in the trench comprises:
and depositing polycrystalline silicon on the front surface of the drift layer, and etching the polycrystalline silicon material on the surface of the drift layer under the photomask-free condition until the drift layer is exposed so as to retain the polycrystalline silicon in the groove.
7. The method of claim 1, wherein forming a dielectric layer and forming a contact hole in the dielectric layer using a sixth mask comprises:
forming the dielectric layer in a cellular region on the front surface of the drift layer by depositing silicon nitride or silicon oxide;
etching the dielectric layer under the cover of the fifth photomask to form a plurality of contact holes on the dielectric layer;
wherein the contact hole is arranged between the adjacent grooves.
8. The method of claim 1, wherein the depositing the metal material and etching the metal material under the mask of a seventh mask to obtain the gate electrode, the emitter electrode and the terminal metal layer comprises:
depositing a metal material on the dielectric layer, and etching the metal material under the cover of the seventh photomask to form a gate electrode and an emitter electrode in the cell area and a terminal metal layer in the terminal area;
wherein the emitter electrode is positioned above the polysilicon layer, and the emitter electrode is in contact with the ohmic contact impurity layer.
9. A trench gate IGBT, characterized in that the trench gate IGBT is prepared by the preparation method according to any one of claims 1-8.
10. A chip comprising the trench gate IGBT of claim 9; or the chip comprises a chip produced by the production method according to any one of claims 1 to 8.
CN202211350011.3A 2022-10-31 2022-10-31 Preparation method of trench gate IGBT, trench gate IGBT and chip Pending CN115588614A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117133800A (en) * 2023-10-25 2023-11-28 合肥海图微电子有限公司 Insulated gate bipolar transistor and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117133800A (en) * 2023-10-25 2023-11-28 合肥海图微电子有限公司 Insulated gate bipolar transistor and manufacturing method thereof
CN117133800B (en) * 2023-10-25 2024-03-26 合肥海图微电子有限公司 Insulated gate bipolar transistor and manufacturing method thereof

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